Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 0 5 100.00
Crosses 6 0 6 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
instr_type_cp 3 0 3 100.00 100 1 1 0
key_cp 2 0 2 100.00 100 1 1 2


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
key_instr_cross 6 0 6 100.00 100 1 1 0


Summary for Variable instr_type_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for instr_type_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
others 4907 1 T44 80 T45 197 T46 67
instr_types[0] 5892 1 T44 211 T45 331 T46 215
instr_types[1] 3976348 1 T3 22 T6 16718 T7 16175



Summary for Variable key_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3985394 1 T3 22 T6 16718 T7 16175
auto[1] 1753 1 T44 112 T45 241 T46 75



Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 0 6 100.00


Automatically Generated Cross Bins for key_instr_cross

Bins
key_cpinstr_type_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] others 4608 1 T44 47 T45 156 T46 54
auto[0] instr_types[0] 5134 1 T44 142 T45 254 T46 178
auto[0] instr_types[1] 3975652 1 T3 22 T6 16718 T7 16175
auto[1] others 299 1 T44 33 T45 41 T46 13
auto[1] instr_types[0] 758 1 T44 69 T45 77 T46 37
auto[1] instr_types[1] 696 1 T44 10 T45 123 T46 25

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%