Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	26559	1		T315	15452		T316	8455		T317	2652
rd_lvl[2]	44782	1		T318	1300		T315	11172		T319	2512
rd_lvl[3]	8166	1		T318	796		T320	850		T319	2223
rd_lvl[4]	23245	1		T232	5207		T318	154		T321	1365
rd_lvl[5]	10979	1		T232	1205		T318	392		T321	571
rd_lvl[6]	19582	1		T318	354		T321	50		T320	174
rd_lvl[7]	13006	1		T318	61		T321	65		T320	204
rd_lvl[8]	11471	1		T318	62		T321	109		T320	52
rd_lvl[9]	4266	1		T318	62		T322	1		T323	516
rd_lvl[10]	7130	1		T187	188		T318	3		T320	4
rd_lvl[11]	3214	1		T67	525		T187	712		T318	2
rd_lvl[12]	4666	1		T67	1147		T187	1		T263	270
rd_lvl[13]	4066	1		T30	302		T187	29		T263	162
rd_lvl[14]	10387	1		T30	1429		T200	60		T324	524
rd_lvl[15]	4185	1		T6	565		T7	192		T263	126