Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	319006	1		T1	2		T2	1		T3	2
all_pins[1]	319006	1		T1	2		T2	1		T3	2
all_pins[2]	319006	1		T1	2		T2	1		T3	2
all_pins[3]	319006	1		T1	2		T2	1		T3	2
all_pins[4]	319006	1		T1	2		T2	1		T3	2
all_pins[5]	319006	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1589162	1		T1	12		T2	6		T3	12
values[0x1]	324874	1		T6	5910		T7	1043		T30	3462
transitions[0x0=>0x1]	291523	1		T6	3520		T7	703		T30	3462
transitions[0x1=>0x0]	291505	1		T6	3520		T7	703		T30	3462

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	318845	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	161	1		T249	4		T250	1		T251	2
all_pins[0]	transitions[0x0=>0x1]	84	1		T250	1		T251	1		T308	5
all_pins[0]	transitions[0x1=>0x0]	60	1		T249	1		T250	3		T309	3
all_pins[1]	values[0x0]	318869	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	137	1		T249	5		T250	3		T251	1
all_pins[1]	transitions[0x0=>0x1]	113	1		T249	5		T250	2		T251	1
all_pins[1]	transitions[0x1=>0x0]	5691	1		T6	1195		T7	170		T344	1075
all_pins[2]	values[0x0]	313291	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	5715	1		T6	1195		T7	170		T344	1075
all_pins[2]	transitions[0x0=>0x1]	42	1		T250	2		T309	1		T310	1
all_pins[2]	transitions[0x1=>0x0]	196362	1		T6	565		T7	223		T30	1731
all_pins[3]	values[0x0]	116971	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	202035	1		T6	1760		T7	393		T30	1731
all_pins[3]	transitions[0x0=>0x1]	174511	1		T6	565		T7	223		T30	1731
all_pins[3]	transitions[0x1=>0x0]	89236	1		T6	1760		T7	310		T30	1731
all_pins[4]	values[0x0]	202246	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	116760	1		T6	2955		T7	480		T30	1731
all_pins[4]	transitions[0x0=>0x1]	116742	1		T6	2955		T7	480		T30	1731
all_pins[4]	transitions[0x1=>0x0]	48	1		T249	1		T250	1		T251	1
all_pins[5]	values[0x0]	318940	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	66	1		T249	2		T250	1		T251	3
all_pins[5]	transitions[0x0=>0x1]	31	1		T249	1		T251	2		T309	1
all_pins[5]	transitions[0x1=>0x0]	108	1		T249	3		T251	1		T309	1