Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T249	4		T250	4		T251	7
all_values[1]	269	1		T249	4		T250	4		T251	7
all_values[2]	269	1		T249	4		T250	4		T251	7
all_values[3]	269	1		T249	4		T250	4		T251	7
all_values[4]	269	1		T249	4		T250	4		T251	7
all_values[5]	269	1		T249	4		T250	4		T251	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	896	1		T249	10		T250	16		T251	22
auto[1]	718	1		T249	14		T250	8		T251	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	517	1		T249	6		T250	5		T251	13
auto[1]	1097	1		T249	18		T250	19		T251	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	927	1		T249	14		T250	10		T251	24
auto[1]	687	1		T249	10		T250	14		T251	18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	73	1		T249	1		T250	1		T251	3
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T249	2		T251	2		T308	2
all_values[0]	auto[1]	auto[0]	auto[1]	70	1		T250	2		T251	1		T309	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T249	1		T250	1		T251	1
all_values[1]	auto[0]	auto[0]	auto[1]	90	1		T250	1		T251	2		T308	4
all_values[1]	auto[0]	auto[1]	auto[1]	61	1		T249	1		T250	1		T251	1
all_values[1]	auto[1]	auto[0]	auto[1]	70	1		T249	1		T250	2		T251	3
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T249	2		T251	1		T309	2
all_values[2]	auto[0]	auto[0]	auto[0]	81	1		T249	2		T250	1		T251	2
all_values[2]	auto[0]	auto[1]	auto[0]	84	1		T249	1		T250	1		T251	3
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T249	1		T250	1		T251	2
all_values[2]	auto[1]	auto[1]	auto[1]	44	1		T250	1		T309	1		T308	1
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T250	2		T251	2		T309	4
all_values[3]	auto[0]	auto[1]	auto[0]	65	1		T249	2		T251	3		T308	2
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T249	1		T250	1		T251	1
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T249	1		T250	1		T251	1
all_values[4]	auto[0]	auto[0]	auto[0]	72	1		T251	1		T308	2		T310	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1		T250	1		T251	1		T308	1
all_values[4]	auto[0]	auto[1]	auto[0]	36	1		T309	2		T311	1		T312	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T249	3		T250	1		T251	1
all_values[4]	auto[1]	auto[0]	auto[1]	51	1		T249	1		T250	2		T251	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T251	3		T309	1		T308	2
all_values[5]	auto[0]	auto[0]	auto[0]	52	1		T249	1		T251	1		T309	2
all_values[5]	auto[0]	auto[0]	auto[1]	23	1		T313	1		T311	1		T314	2
all_values[5]	auto[0]	auto[1]	auto[0]	40	1		T250	1		T251	1		T308	2
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T249	1		T251	1		T309	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T249	2		T250	2		T251	2
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T250	1		T251	2		T309	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal