| T1072 |
/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1707097761 |
|
|
Jul 01 01:48:23 PM PDT 24 |
Jul 01 01:51:05 PM PDT 24 |
3634901600 ps |
| T1073 |
/workspace/coverage/default/63.flash_ctrl_otp_reset.861324078 |
|
|
Jul 01 01:49:36 PM PDT 24 |
Jul 01 01:51:48 PM PDT 24 |
160150800 ps |
| T1074 |
/workspace/coverage/default/48.flash_ctrl_connect.1877601569 |
|
|
Jul 01 01:49:19 PM PDT 24 |
Jul 01 01:49:35 PM PDT 24 |
16090600 ps |
| T1075 |
/workspace/coverage/default/64.flash_ctrl_otp_reset.1067957796 |
|
|
Jul 01 01:49:39 PM PDT 24 |
Jul 01 01:51:55 PM PDT 24 |
74952500 ps |
| T1076 |
/workspace/coverage/default/7.flash_ctrl_rand_ops.3961496683 |
|
|
Jul 01 01:42:12 PM PDT 24 |
Jul 01 01:57:21 PM PDT 24 |
146593200 ps |
| T1077 |
/workspace/coverage/default/52.flash_ctrl_otp_reset.75080192 |
|
|
Jul 01 01:49:24 PM PDT 24 |
Jul 01 01:51:16 PM PDT 24 |
42789100 ps |
| T1078 |
/workspace/coverage/default/7.flash_ctrl_invalid_op.4240306389 |
|
|
Jul 01 01:42:12 PM PDT 24 |
Jul 01 01:43:37 PM PDT 24 |
2127235900 ps |
| T1079 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.2673653739 |
|
|
Jul 01 01:42:22 PM PDT 24 |
Jul 01 01:45:24 PM PDT 24 |
12993486200 ps |
| T1080 |
/workspace/coverage/default/11.flash_ctrl_re_evict.1763642019 |
|
|
Jul 01 01:44:20 PM PDT 24 |
Jul 01 01:44:58 PM PDT 24 |
971523600 ps |
| T1081 |
/workspace/coverage/default/7.flash_ctrl_smoke.5568359 |
|
|
Jul 01 01:42:07 PM PDT 24 |
Jul 01 01:45:40 PM PDT 24 |
28105800 ps |
| T1082 |
/workspace/coverage/default/6.flash_ctrl_sec_info_access.3971661961 |
|
|
Jul 01 01:41:57 PM PDT 24 |
Jul 01 01:43:31 PM PDT 24 |
5918029800 ps |
| T1083 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.3723631626 |
|
|
Jul 01 01:47:19 PM PDT 24 |
Jul 01 01:49:14 PM PDT 24 |
43421400 ps |
| T1084 |
/workspace/coverage/default/0.flash_ctrl_otp_reset.1318961244 |
|
|
Jul 01 01:34:16 PM PDT 24 |
Jul 01 01:36:35 PM PDT 24 |
723066200 ps |
| T1085 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep.1708835021 |
|
|
Jul 01 01:34:47 PM PDT 24 |
Jul 01 01:35:08 PM PDT 24 |
79365700 ps |
| T1086 |
/workspace/coverage/default/44.flash_ctrl_sec_info_access.1019199196 |
|
|
Jul 01 01:48:57 PM PDT 24 |
Jul 01 01:50:16 PM PDT 24 |
642567800 ps |
| T1087 |
/workspace/coverage/default/31.flash_ctrl_disable.148428689 |
|
|
Jul 01 01:47:51 PM PDT 24 |
Jul 01 01:48:53 PM PDT 24 |
16066100 ps |
| T1088 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.2788229377 |
|
|
Jul 01 01:36:52 PM PDT 24 |
Jul 01 01:37:26 PM PDT 24 |
32301300 ps |
| T1089 |
/workspace/coverage/default/33.flash_ctrl_smoke.3011891231 |
|
|
Jul 01 01:47:58 PM PDT 24 |
Jul 01 01:50:50 PM PDT 24 |
522285800 ps |
| T1090 |
/workspace/coverage/default/12.flash_ctrl_otp_reset.138955417 |
|
|
Jul 01 01:44:35 PM PDT 24 |
Jul 01 01:46:34 PM PDT 24 |
42353500 ps |
| T1091 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2451091442 |
|
|
Jul 01 01:47:42 PM PDT 24 |
Jul 01 01:50:34 PM PDT 24 |
5876174300 ps |
| T1092 |
/workspace/coverage/default/10.flash_ctrl_mp_regions.434860946 |
|
|
Jul 01 01:43:47 PM PDT 24 |
Jul 01 01:57:57 PM PDT 24 |
11325527800 ps |
| T1093 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.368931462 |
|
|
Jul 01 01:36:41 PM PDT 24 |
Jul 01 01:37:58 PM PDT 24 |
9904221500 ps |
| T1094 |
/workspace/coverage/default/66.flash_ctrl_connect.1931347618 |
|
|
Jul 01 01:49:38 PM PDT 24 |
Jul 01 01:49:56 PM PDT 24 |
50945300 ps |
| T1095 |
/workspace/coverage/default/17.flash_ctrl_mp_regions.50875375 |
|
|
Jul 01 01:45:54 PM PDT 24 |
Jul 01 01:51:18 PM PDT 24 |
27151637100 ps |
| T336 |
/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1960983346 |
|
|
Jul 01 01:46:36 PM PDT 24 |
Jul 01 01:47:13 PM PDT 24 |
37061300 ps |
| T1096 |
/workspace/coverage/default/4.flash_ctrl_serr_counter.3001634530 |
|
|
Jul 01 01:40:29 PM PDT 24 |
Jul 01 01:41:39 PM PDT 24 |
1271544600 ps |
| T1097 |
/workspace/coverage/default/34.flash_ctrl_alert_test.947772836 |
|
|
Jul 01 01:48:10 PM PDT 24 |
Jul 01 01:49:07 PM PDT 24 |
48107600 ps |
| T1098 |
/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2701117657 |
|
|
Jul 01 01:46:51 PM PDT 24 |
Jul 01 01:47:31 PM PDT 24 |
785556600 ps |
| T1099 |
/workspace/coverage/default/36.flash_ctrl_alert_test.3550874182 |
|
|
Jul 01 01:48:19 PM PDT 24 |
Jul 01 01:49:12 PM PDT 24 |
181218200 ps |
| T1100 |
/workspace/coverage/default/25.flash_ctrl_intr_rd.4208039864 |
|
|
Jul 01 01:47:13 PM PDT 24 |
Jul 01 01:49:07 PM PDT 24 |
6788571800 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3427013407 |
|
|
Jul 01 01:41:32 PM PDT 24 |
Jul 01 01:43:22 PM PDT 24 |
10012362600 ps |
| T1102 |
/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4231255269 |
|
|
Jul 01 01:44:59 PM PDT 24 |
Jul 01 01:45:32 PM PDT 24 |
94343100 ps |
| T370 |
/workspace/coverage/default/15.flash_ctrl_sec_info_access.3404982822 |
|
|
Jul 01 01:45:32 PM PDT 24 |
Jul 01 01:46:39 PM PDT 24 |
1473043700 ps |
| T1103 |
/workspace/coverage/default/4.flash_ctrl_error_prog_win.3797380715 |
|
|
Jul 01 01:40:09 PM PDT 24 |
Jul 01 01:56:01 PM PDT 24 |
709685300 ps |
| T1104 |
/workspace/coverage/default/31.flash_ctrl_alert_test.1519924630 |
|
|
Jul 01 01:47:59 PM PDT 24 |
Jul 01 01:48:57 PM PDT 24 |
131520000 ps |
| T1105 |
/workspace/coverage/default/49.flash_ctrl_smoke.4105333630 |
|
|
Jul 01 01:49:18 PM PDT 24 |
Jul 01 01:51:27 PM PDT 24 |
65221500 ps |
| T1106 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.1413159408 |
|
|
Jul 01 01:42:13 PM PDT 24 |
Jul 01 01:56:44 PM PDT 24 |
1270304500 ps |
| T1107 |
/workspace/coverage/default/45.flash_ctrl_disable.2784020732 |
|
|
Jul 01 01:49:03 PM PDT 24 |
Jul 01 01:49:32 PM PDT 24 |
60620800 ps |
| T70 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4034165496 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:45 AM PDT 24 |
105128800 ps |
| T71 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1471153767 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
328587300 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1698925284 |
|
|
Jul 01 11:05:20 AM PDT 24 |
Jul 01 11:13:14 AM PDT 24 |
3725464100 ps |
| T1108 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3833363659 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
12638500 ps |
| T1109 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1000896362 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
22830700 ps |
| T249 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.373945326 |
|
|
Jul 01 11:05:54 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
16969100 ps |
| T1110 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.797282416 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
13684600 ps |
| T1111 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4060747651 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
29663500 ps |
| T1112 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3672763165 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
29946000 ps |
| T97 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4257505866 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:40 AM PDT 24 |
56639600 ps |
| T98 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3514195769 |
|
|
Jul 01 11:05:41 AM PDT 24 |
Jul 01 11:05:57 AM PDT 24 |
176655900 ps |
| T201 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1686801341 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
356616100 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1897703829 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:05:43 AM PDT 24 |
65395200 ps |
| T244 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1454204176 |
|
|
Jul 01 11:05:43 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
129269100 ps |
| T225 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3348943360 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
33344500 ps |
| T243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3004017431 |
|
|
Jul 01 11:05:32 AM PDT 24 |
Jul 01 11:06:47 AM PDT 24 |
6329508300 ps |
| T204 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.482445629 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
36262100 ps |
| T236 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1575228042 |
|
|
Jul 01 11:05:38 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
83734900 ps |
| T202 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3505276342 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
224705400 ps |
| T203 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2293969450 |
|
|
Jul 01 11:05:46 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
95968500 ps |
| T237 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3190790659 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:48 AM PDT 24 |
364045400 ps |
| T250 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4255858882 |
|
|
Jul 01 11:05:21 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
52324800 ps |
| T251 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1207543363 |
|
|
Jul 01 11:05:50 AM PDT 24 |
Jul 01 11:06:04 AM PDT 24 |
18074900 ps |
| T309 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2812996641 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
45239800 ps |
| T238 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.348705846 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:57 AM PDT 24 |
125232200 ps |
| T1113 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2818349963 |
|
|
Jul 01 11:05:47 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
21677500 ps |
| T1114 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.606764397 |
|
|
Jul 01 11:05:20 AM PDT 24 |
Jul 01 11:05:36 AM PDT 24 |
12077200 ps |
| T226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2539163534 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:38 AM PDT 24 |
16986200 ps |
| T1115 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.320596886 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
95451700 ps |
| T276 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2039322837 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
49086300 ps |
| T205 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.985445480 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:11:53 AM PDT 24 |
203245600 ps |
| T1116 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3782842569 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:52 AM PDT 24 |
14318800 ps |
| T206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3221432350 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:13:09 AM PDT 24 |
746311800 ps |
| T219 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1244068414 |
|
|
Jul 01 11:05:43 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
33666500 ps |
| T1117 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4030522675 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:05:42 AM PDT 24 |
18731900 ps |
| T1118 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.156717222 |
|
|
Jul 01 11:05:41 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
12040600 ps |
| T308 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.896016956 |
|
|
Jul 01 11:05:51 AM PDT 24 |
Jul 01 11:06:06 AM PDT 24 |
50327100 ps |
| T1119 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4011221379 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
285289700 ps |
| T274 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2687135672 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:57 AM PDT 24 |
191255400 ps |
| T310 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.548386792 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:05:39 AM PDT 24 |
48640000 ps |
| T1120 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2691450844 |
|
|
Jul 01 11:05:38 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
69726600 ps |
| T397 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3149283859 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:06:10 AM PDT 24 |
452405300 ps |
| T1121 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3204316354 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
34475900 ps |
| T220 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.840320427 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:05:43 AM PDT 24 |
253307100 ps |
| T1122 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1314119036 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:06:02 AM PDT 24 |
12689000 ps |
| T313 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2813184790 |
|
|
Jul 01 11:05:59 AM PDT 24 |
Jul 01 11:06:13 AM PDT 24 |
27840500 ps |
| T311 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1524526900 |
|
|
Jul 01 11:05:57 AM PDT 24 |
Jul 01 11:06:12 AM PDT 24 |
47533200 ps |
| T275 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1291795225 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:06:39 AM PDT 24 |
6765515100 ps |
| T312 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.503593597 |
|
|
Jul 01 11:05:52 AM PDT 24 |
Jul 01 11:06:07 AM PDT 24 |
49541500 ps |
| T1123 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3426994441 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
50952100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3716120408 |
|
|
Jul 01 11:05:50 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
43196600 ps |
| T1125 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1611493965 |
|
|
Jul 01 11:05:40 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
16424500 ps |
| T222 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1578372170 |
|
|
Jul 01 11:05:41 AM PDT 24 |
Jul 01 11:18:24 AM PDT 24 |
1316818300 ps |
| T278 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1682392312 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
102799600 ps |
| T221 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1558098187 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
190507800 ps |
| T245 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.191139695 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:12:13 AM PDT 24 |
1440216900 ps |
| T1126 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3677103882 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
19553100 ps |
| T1127 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3957197409 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
63000200 ps |
| T246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.169991785 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
61640200 ps |
| T277 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2990893628 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:51 AM PDT 24 |
215833400 ps |
| T1128 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3677124887 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:06:10 AM PDT 24 |
63120600 ps |
| T279 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4182568741 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
810319400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.400481809 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
80792800 ps |
| T314 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4275288513 |
|
|
Jul 01 11:06:01 AM PDT 24 |
Jul 01 11:06:15 AM PDT 24 |
56107800 ps |
| T1130 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3170615639 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:45 AM PDT 24 |
14769800 ps |
| T1131 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1482316175 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
16383600 ps |
| T256 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3325300909 |
|
|
Jul 01 11:05:32 AM PDT 24 |
Jul 01 11:18:21 AM PDT 24 |
1653690300 ps |
| T1132 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1154713037 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
14473600 ps |
| T1133 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2863623221 |
|
|
Jul 01 11:05:52 AM PDT 24 |
Jul 01 11:06:07 AM PDT 24 |
17610300 ps |
| T1134 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.204440492 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:05:45 AM PDT 24 |
13125700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2514604490 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:45 AM PDT 24 |
16806200 ps |
| T1136 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2087813451 |
|
|
Jul 01 11:05:12 AM PDT 24 |
Jul 01 11:05:28 AM PDT 24 |
78648100 ps |
| T1137 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1064478767 |
|
|
Jul 01 11:05:40 AM PDT 24 |
Jul 01 11:05:53 AM PDT 24 |
41241700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2925217433 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
1148960000 ps |
| T307 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1930042290 |
|
|
Jul 01 11:05:43 AM PDT 24 |
Jul 01 11:06:00 AM PDT 24 |
426045400 ps |
| T247 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1807157440 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
57949900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3215772735 |
|
|
Jul 01 11:05:57 AM PDT 24 |
Jul 01 11:06:12 AM PDT 24 |
106470500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.696332462 |
|
|
Jul 01 11:05:46 AM PDT 24 |
Jul 01 11:06:07 AM PDT 24 |
120950800 ps |
| T345 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2240758365 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:11:59 AM PDT 24 |
1102615300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2196927910 |
|
|
Jul 01 11:05:32 AM PDT 24 |
Jul 01 11:05:49 AM PDT 24 |
312419500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.414465112 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
323534800 ps |
| T346 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3561092182 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:18:14 AM PDT 24 |
682307100 ps |
| T257 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1555735152 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:13:37 AM PDT 24 |
1633190000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.623581715 |
|
|
Jul 01 11:05:49 AM PDT 24 |
Jul 01 11:06:03 AM PDT 24 |
27323600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.967816533 |
|
|
Jul 01 11:05:54 AM PDT 24 |
Jul 01 11:06:10 AM PDT 24 |
21097500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3330400403 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:33 AM PDT 24 |
15413100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.400377627 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
627556000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3457964306 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:49 AM PDT 24 |
1312305500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.800031893 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:05:46 AM PDT 24 |
38261800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4146454468 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:38 AM PDT 24 |
52540000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.717140249 |
|
|
Jul 01 11:06:06 AM PDT 24 |
Jul 01 11:06:20 AM PDT 24 |
60661000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1647451532 |
|
|
Jul 01 11:05:12 AM PDT 24 |
Jul 01 11:05:42 AM PDT 24 |
934381500 ps |
| T1152 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3596515638 |
|
|
Jul 01 11:05:21 AM PDT 24 |
Jul 01 11:05:38 AM PDT 24 |
352293000 ps |
| T252 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3835728481 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
200371800 ps |
| T348 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2971597104 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:11:54 AM PDT 24 |
241319500 ps |
| T1153 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1407025980 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:59 AM PDT 24 |
148193500 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2465648171 |
|
|
Jul 01 11:05:21 AM PDT 24 |
Jul 01 11:05:36 AM PDT 24 |
151368400 ps |
| T1155 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2106997459 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
127700400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.334243298 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
197107600 ps |
| T347 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2132771340 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:20:47 AM PDT 24 |
2164722800 ps |
| T258 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.898012878 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:13:30 AM PDT 24 |
811838000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.237752315 |
|
|
Jul 01 11:05:40 AM PDT 24 |
Jul 01 11:05:55 AM PDT 24 |
29767900 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3804885763 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:55 AM PDT 24 |
70169600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3212041133 |
|
|
Jul 01 11:05:46 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
16884800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1096874586 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:05:43 AM PDT 24 |
38916500 ps |
| T253 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3306031731 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
57712100 ps |
| T280 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2559564333 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
737383800 ps |
| T254 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.148958336 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
119469800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1948834151 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
19028100 ps |
| T281 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.4146547876 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:39 AM PDT 24 |
216226400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1457059 |
|
|
Jul 01 11:05:53 AM PDT 24 |
Jul 01 11:06:08 AM PDT 24 |
23754300 ps |
| T227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2280571049 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:37 AM PDT 24 |
57145300 ps |
| T1162 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.431957142 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:52 AM PDT 24 |
24954300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2452405507 |
|
|
Jul 01 11:05:19 AM PDT 24 |
Jul 01 11:05:34 AM PDT 24 |
55674600 ps |
| T228 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.859278289 |
|
|
Jul 01 11:05:17 AM PDT 24 |
Jul 01 11:05:31 AM PDT 24 |
17991300 ps |
| T352 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2003375364 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:18:20 AM PDT 24 |
996514200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.335125835 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
101795100 ps |
| T282 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3823587895 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:54 AM PDT 24 |
94359100 ps |
| T1165 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2913354942 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
14929500 ps |
| T255 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.217821137 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
63308200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1177494255 |
|
|
Jul 01 11:05:19 AM PDT 24 |
Jul 01 11:05:33 AM PDT 24 |
12477500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.4271681933 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:51 AM PDT 24 |
26719700 ps |
| T259 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3610093910 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:55 AM PDT 24 |
71849800 ps |
| T229 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1218114798 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:38 AM PDT 24 |
21018200 ps |
| T1168 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3033266717 |
|
|
Jul 01 11:05:31 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
32950300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.214465137 |
|
|
Jul 01 11:05:44 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
155433200 ps |
| T1170 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.215433517 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:05:46 AM PDT 24 |
40456200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3054009097 |
|
|
Jul 01 11:05:48 AM PDT 24 |
Jul 01 11:06:02 AM PDT 24 |
15228000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4040760479 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
13412500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3322553266 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:05:39 AM PDT 24 |
15004700 ps |
| T1174 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3969574997 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
34675100 ps |
| T1175 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2146076377 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
30538700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3466804328 |
|
|
Jul 01 11:05:48 AM PDT 24 |
Jul 01 11:06:02 AM PDT 24 |
41099200 ps |
| T1177 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3856992354 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:12:06 AM PDT 24 |
344716200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1575831926 |
|
|
Jul 01 11:05:42 AM PDT 24 |
Jul 01 11:05:59 AM PDT 24 |
76690600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.4220958765 |
|
|
Jul 01 11:05:54 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
26401700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3191781782 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
103160100 ps |
| T1181 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3999812648 |
|
|
Jul 01 11:05:47 AM PDT 24 |
Jul 01 11:06:04 AM PDT 24 |
13789000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.581722477 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:55 AM PDT 24 |
353746100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.801676930 |
|
|
Jul 01 11:06:02 AM PDT 24 |
Jul 01 11:06:17 AM PDT 24 |
14146200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.239965543 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:40 AM PDT 24 |
26013800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1039537636 |
|
|
Jul 01 11:05:17 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
8157721100 ps |
| T1186 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.4038356925 |
|
|
Jul 01 11:05:57 AM PDT 24 |
Jul 01 11:06:12 AM PDT 24 |
26407900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1869685677 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:53 AM PDT 24 |
21876400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3872549758 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:06:12 AM PDT 24 |
54026800 ps |
| T1189 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2456410503 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
44024800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3083263267 |
|
|
Jul 01 11:05:19 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
71972600 ps |
| T1191 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2947558555 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
19124000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3417850099 |
|
|
Jul 01 11:05:27 AM PDT 24 |
Jul 01 11:13:07 AM PDT 24 |
1544438400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1948519863 |
|
|
Jul 01 11:05:43 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
245492400 ps |
| T1194 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1555237688 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:51 AM PDT 24 |
146897200 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2113876265 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:06:06 AM PDT 24 |
495243000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2143326641 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:06:03 AM PDT 24 |
20244700 ps |
| T1197 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1278987187 |
|
|
Jul 01 11:05:51 AM PDT 24 |
Jul 01 11:06:06 AM PDT 24 |
14595500 ps |
| T1198 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3061838704 |
|
|
Jul 01 11:05:43 AM PDT 24 |
Jul 01 11:06:00 AM PDT 24 |
153125100 ps |
| T1199 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1719137738 |
|
|
Jul 01 11:05:28 AM PDT 24 |
Jul 01 11:05:42 AM PDT 24 |
59005100 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2674252700 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:56 AM PDT 24 |
87609100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1249947336 |
|
|
Jul 01 11:06:02 AM PDT 24 |
Jul 01 11:06:17 AM PDT 24 |
17402100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3377533636 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:06:18 AM PDT 24 |
3165188800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2842632745 |
|
|
Jul 01 11:05:50 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
99160700 ps |
| T1204 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4049587680 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
14868300 ps |
| T1205 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2605322305 |
|
|
Jul 01 11:06:01 AM PDT 24 |
Jul 01 11:06:15 AM PDT 24 |
118677900 ps |
| T1206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2246884375 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:05:40 AM PDT 24 |
71671900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2099093145 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:42 AM PDT 24 |
35678600 ps |
| T1208 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1463010820 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
74673500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3529273901 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:05:36 AM PDT 24 |
30611100 ps |
| T1210 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3015670641 |
|
|
Jul 01 11:05:31 AM PDT 24 |
Jul 01 11:05:49 AM PDT 24 |
294003900 ps |
| T1211 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2175261632 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
78876200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1715348985 |
|
|
Jul 01 11:05:46 AM PDT 24 |
Jul 01 11:06:02 AM PDT 24 |
17986500 ps |
| T350 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1026701817 |
|
|
Jul 01 11:05:31 AM PDT 24 |
Jul 01 11:13:13 AM PDT 24 |
4095379500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2261287561 |
|
|
Jul 01 11:06:02 AM PDT 24 |
Jul 01 11:06:16 AM PDT 24 |
25939600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4196762682 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:50 AM PDT 24 |
15000000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1549223089 |
|
|
Jul 01 11:05:39 AM PDT 24 |
Jul 01 11:05:59 AM PDT 24 |
119974800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.875699558 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:47 AM PDT 24 |
22966300 ps |
| T1217 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2256053873 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:06:06 AM PDT 24 |
1961857900 ps |
| T1218 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1547303432 |
|
|
Jul 01 11:05:54 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
55992200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3040268837 |
|
|
Jul 01 11:05:41 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
36839500 ps |
| T1220 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.254962198 |
|
|
Jul 01 11:05:13 AM PDT 24 |
Jul 01 11:05:52 AM PDT 24 |
87128700 ps |
| T353 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1169312072 |
|
|
Jul 01 11:05:20 AM PDT 24 |
Jul 01 11:20:30 AM PDT 24 |
1325104500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2458647737 |
|
|
Jul 01 11:05:52 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
68243200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3083161091 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:06:27 AM PDT 24 |
5197761900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3342486949 |
|
|
Jul 01 11:05:35 AM PDT 24 |
Jul 01 11:05:49 AM PDT 24 |
13275700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2153403255 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:53 AM PDT 24 |
21729400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1327233176 |
|
|
Jul 01 11:05:36 AM PDT 24 |
Jul 01 11:05:51 AM PDT 24 |
29327700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1543079160 |
|
|
Jul 01 11:05:23 AM PDT 24 |
Jul 01 11:05:37 AM PDT 24 |
29134200 ps |
| T1227 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3025860656 |
|
|
Jul 01 11:05:41 AM PDT 24 |
Jul 01 11:06:01 AM PDT 24 |
639909100 ps |
| T349 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1388168881 |
|
|
Jul 01 11:05:29 AM PDT 24 |
Jul 01 11:18:05 AM PDT 24 |
1453610300 ps |
| T260 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1796094127 |
|
|
Jul 01 11:05:25 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
114259300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1431288504 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:06:05 AM PDT 24 |
299177700 ps |
| T1229 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4293120513 |
|
|
Jul 01 11:05:56 AM PDT 24 |
Jul 01 11:06:11 AM PDT 24 |
69503900 ps |
| T1230 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.4171988980 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
12494700 ps |
| T1231 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2606801148 |
|
|
Jul 01 11:05:33 AM PDT 24 |
Jul 01 11:05:52 AM PDT 24 |
78415300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3654807588 |
|
|
Jul 01 11:05:37 AM PDT 24 |
Jul 01 11:05:52 AM PDT 24 |
15716900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2737489438 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:44 AM PDT 24 |
18887500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1727030630 |
|
|
Jul 01 11:05:54 AM PDT 24 |
Jul 01 11:06:09 AM PDT 24 |
59299800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2612775334 |
|
|
Jul 01 11:05:14 AM PDT 24 |
Jul 01 11:05:28 AM PDT 24 |
14849100 ps |
| T1236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3737540687 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:13:06 AM PDT 24 |
1397837000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.91455301 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:40 AM PDT 24 |
79947700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.655386910 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:05:45 AM PDT 24 |
94939400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1001429912 |
|
|
Jul 01 11:05:30 AM PDT 24 |
Jul 01 11:05:48 AM PDT 24 |
35721100 ps |
| T1240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.292774800 |
|
|
Jul 01 11:05:18 AM PDT 24 |
Jul 01 11:05:35 AM PDT 24 |
482278000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2129259722 |
|
|
Jul 01 11:05:46 AM PDT 24 |
Jul 01 11:06:02 AM PDT 24 |
161795100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2962554581 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:05:59 AM PDT 24 |
141311000 ps |
| T1243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.800402094 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:05:36 AM PDT 24 |
54939100 ps |
| T1244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1296096180 |
|
|
Jul 01 11:05:45 AM PDT 24 |
Jul 01 11:06:04 AM PDT 24 |
266024500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2338185249 |
|
|
Jul 01 11:05:34 AM PDT 24 |
Jul 01 11:05:55 AM PDT 24 |
119648200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3466526337 |
|
|
Jul 01 11:05:12 AM PDT 24 |
Jul 01 11:05:30 AM PDT 24 |
180879600 ps |
| T1247 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2930372970 |
|
|
Jul 01 11:05:22 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
53357200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.99238886 |
|
|
Jul 01 11:05:39 AM PDT 24 |
Jul 01 11:05:58 AM PDT 24 |
93782900 ps |
| T351 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2640246024 |
|
|
Jul 01 11:05:32 AM PDT 24 |
Jul 01 11:20:48 AM PDT 24 |
8350985300 ps |
| T1249 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2209337371 |
|
|
Jul 01 11:05:24 AM PDT 24 |
Jul 01 11:05:41 AM PDT 24 |
14223400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3180785921 |
|
|
Jul 01 11:05:26 AM PDT 24 |
Jul 01 11:06:03 AM PDT 24 |
327014500 ps |