Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18539	1		T108	1395		T66	61		T67	7
full_word	4107967	1		T2	36800		T3	3		T6	16183

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4126227	1		T2	36800		T3	3		T6	16183
auto[TlIntgErrCmd]	101	1		T67	2		T109	4		T227	2
auto[TlIntgErrData]	106	1		T67	3		T109	7		T227	4
auto[TlIntgErrBoth]	72	1		T67	2		T109	7		T227	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4102279	1		T2	36800		T3	3		T6	16183
auto[1]	24227	1		T108	1717		T66	84		T67	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1187	1		T108	61		T66	8		T226	38
auto[TlIntgErrNone]	partial	auto[1]	17096	1		T108	1334		T66	53		T226	328
auto[TlIntgErrNone]	full_word	auto[0]	4100983	1		T2	36800		T3	3		T6	16183
auto[TlIntgErrNone]	full_word	auto[1]	6961	1		T108	383		T66	31		T226	80
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T67	2		T109	1		T227	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T109	3		T227	1		T286	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T366	1		T286	1		T295	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T368	1		T369	1		T367	2
auto[TlIntgErrData]	partial	auto[0]	45	1		T67	3		T109	2		T227	2
auto[TlIntgErrData]	partial	auto[1]	54	1		T109	4		T227	2		T244	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T286	1		T295	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T109	1		T371	1		T372	1
auto[TlIntgErrBoth]	partial	auto[0]	21	1		T109	1		T244	1		T366	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T67	2		T109	6		T227	4
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T366	1		T368	1		T293	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24479458	1		T1	134		T2	158280		T3	350
full_word	7856398	1		T1	117		T2	31196		T3	140

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32335556	1		T1	251		T2	189476		T3	490
auto[TlIntgErrCmd]	109	1		T67	2		T109	4		T227	6
auto[TlIntgErrData]	103	1		T67	5		T109	7		T227	1
auto[TlIntgErrBoth]	88	1		T67	3		T109	9		T227	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27885944	1		T1	126		T2	168272		T3	400
auto[1]	4449912	1		T1	125		T2	21204		T3	90

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23790573	1		T1	121		T2	155409		T3	333
auto[TlIntgErrNone]	partial	auto[1]	688615	1		T1	13		T2	2871		T3	17
auto[TlIntgErrNone]	full_word	auto[0]	4095228	1		T1	5		T2	12863		T3	67
auto[TlIntgErrNone]	full_word	auto[1]	3761140	1		T1	112		T2	18333		T3	73
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T109	2		T227	3		T366	4
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T67	2		T109	2		T227	2
auto[TlIntgErrCmd]	full_word	auto[0]	10	1		T227	1		T244	1		T286	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T244	1		T368	1		T293	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T67	3		T109	4		T227	1
auto[TlIntgErrData]	partial	auto[1]	46	1		T67	1		T109	3		T244	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T366	1		T372	1		T373	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T67	1		T368	1		T297	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T67	1		T109	5		T227	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T67	2		T109	3		T227	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T109	1		T367	1		T297	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T286	1		T367	1		-	-