Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1542211844	1538977176	0	0
CheckNGreaterZero_A	4180	4180	0	0
GntImpliesReady_A	1542211844	398251636	0	0
GntImpliesValid_A	1542211844	398251636	0	0
GrantKnown_A	1542211844	1538977176	0	0
IdxKnown_A	1542211844	1538977176	0	0
IndexIsCorrect_A	1542211844	398251636	0	0
NoReadyValidNoGrant_A	1542211844	178516624	0	0
Priority_A	1542211844	422270858	0	0
ReadyAndValidImplyGrant_A	1542211844	398251636	0	0
ReqAndReadyImplyGrant_A	1542211844	398251636	0	0
ReqImpliesValid_A	1542211844	422270858	0	0
ValidKnown_A	1542211844	1538977176	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	1538977176	0	0
T1	7360	6716	0	0
T2	1538736	1538420	0	0
T3	7736	7188	0	0
T6	601916	601416	0	0
T7	675696	675116	0	0
T11	15388	12500	0	0
T12	1540168	1540100	0	0
T17	6216	5844	0	0
T18	1080412	1080152	0	0
T19	4744	4412	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4180	4180	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	398251636	0	0
T1	7360	138	0	0
T2	1538736	516148	0	0
T3	7736	364	0	0
T6	601916	85038	0	0
T7	675696	89520	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	16642	0	0
T57	0	2168	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	398251636	0	0
T1	7360	138	0	0
T2	1538736	516148	0	0
T3	7736	364	0	0
T6	601916	85038	0	0
T7	675696	89520	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	16642	0	0
T57	0	2168	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	1538977176	0	0
T1	7360	6716	0	0
T2	1538736	1538420	0	0
T3	7736	7188	0	0
T6	601916	601416	0	0
T7	675696	675116	0	0
T11	15388	12500	0	0
T12	1540168	1540100	0	0
T17	6216	5844	0	0
T18	1080412	1080152	0	0
T19	4744	4412	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	1538977176	0	0
T1	7360	6716	0	0
T2	1538736	1538420	0	0
T3	7736	7188	0	0
T6	601916	601416	0	0
T7	675696	675116	0	0
T11	15388	12500	0	0
T12	1540168	1540100	0	0
T17	6216	5844	0	0
T18	1080412	1080152	0	0
T19	4744	4412	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	398251636	0	0
T1	7360	138	0	0
T2	1538736	516148	0	0
T3	7736	364	0	0
T6	601916	85038	0	0
T7	675696	89520	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	16642	0	0
T57	0	2168	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	178516624	0	0
T1	3680	512	0	0
T2	1538736	181318	0	0
T3	7736	778	0	0
T6	601916	133868	0	0
T7	675696	239672	0	0
T11	15388	2048	0	0
T12	1540168	2109952	0	0
T17	6216	256	0	0
T18	1080412	984	0	0
T19	4744	256	0	0
T27	0	24	0	0
T28	124276	33260	0	0
T34	0	50256	0	0
T57	0	958	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	422270858	0	0
T1	7360	138	0	0
T2	1538736	589430	0	0
T3	7736	364	0	0
T6	601916	96226	0	0
T7	675696	93342	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	20936	0	0
T57	0	2264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	398251636	0	0
T1	7360	138	0	0
T2	1538736	516148	0	0
T3	7736	364	0	0
T6	601916	85038	0	0
T7	675696	89520	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	16642	0	0
T57	0	2168	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	398251636	0	0
T1	7360	138	0	0
T2	1538736	516148	0	0
T3	7736	364	0	0
T6	601916	85038	0	0
T7	675696	89520	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	16642	0	0
T57	0	2168	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	422270858	0	0
T1	7360	138	0	0
T2	1538736	589430	0	0
T3	7736	364	0	0
T6	601916	96226	0	0
T7	675696	93342	0	0
T11	15388	566	0	0
T12	1540168	514650	0	0
T17	6216	64	0	0
T18	1080412	532920	0	0
T19	4744	64	0	0
T27	0	6	0	0
T28	0	20936	0	0
T57	0	2264	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542211844	1538977176	0	0
T1	7360	6716	0	0
T2	1538736	1538420	0	0
T3	7736	7188	0	0
T6	601916	601416	0	0
T7	675696	675116	0	0
T11	15388	12500	0	0
T12	1540168	1540100	0	0
T17	6216	5844	0	0
T18	1080412	1080152	0	0
T19	4744	4412	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385552961	384744294	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	385552961	100324808	0	0
GntImpliesValid_A	385552961	100324808	0	0
GrantKnown_A	385552961	384744294	0	0
IdxKnown_A	385552961	384744294	0	0
IndexIsCorrect_A	385552961	100324808	0	0
NoReadyValidNoGrant_A	385552961	45254335	0	0
Priority_A	385552961	106425500	0	0
ReadyAndValidImplyGrant_A	385552961	100324808	0	0
ReqAndReadyImplyGrant_A	385552961	100324808	0	0
ReqImpliesValid_A	385552961	106425500	0	0
ValidKnown_A	385552961	384744294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	45254335	0	0
T1	1840	256	0	0
T2	384684	47382	0	0
T3	1934	367	0	0
T6	150479	29395	0	0
T7	168924	65303	0	0
T11	3847	1024	0	0
T12	385042	530688	0	0
T17	1554	128	0	0
T18	270103	339	0	0
T19	1186	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	106425500	0	0
T1	1840	64	0	0
T2	384684	144462	0	0
T3	1934	175	0	0
T6	150479	23643	0	0
T7	168924	25369	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	106425500	0	0
T1	1840	64	0	0
T2	384684	144462	0	0
T3	1934	175	0	0
T6	150479	23643	0	0
T7	168924	25369	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385552961	384744294	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	385552961	100324808	0	0
GntImpliesValid_A	385552961	100324808	0	0
GrantKnown_A	385552961	384744294	0	0
IdxKnown_A	385552961	384744294	0	0
IndexIsCorrect_A	385552961	100324808	0	0
NoReadyValidNoGrant_A	385552961	45254335	0	0
Priority_A	385552961	106425500	0	0
ReadyAndValidImplyGrant_A	385552961	100324808	0	0
ReqAndReadyImplyGrant_A	385552961	100324808	0	0
ReqImpliesValid_A	385552961	106425500	0	0
ValidKnown_A	385552961	384744294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	45254335	0	0
T1	1840	256	0	0
T2	384684	47382	0	0
T3	1934	367	0	0
T6	150479	29395	0	0
T7	168924	65303	0	0
T11	3847	1024	0	0
T12	385042	530688	0	0
T17	1554	128	0	0
T18	270103	339	0	0
T19	1186	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	106425500	0	0
T1	1840	64	0	0
T2	384684	144462	0	0
T3	1934	175	0	0
T6	150479	23643	0	0
T7	168924	25369	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	100324808	0	0
T1	1840	64	0	0
T2	384684	126270	0	0
T3	1934	175	0	0
T6	150479	20063	0	0
T7	168924	24478	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	106425500	0	0
T1	1840	64	0	0
T2	384684	144462	0	0
T3	1934	175	0	0
T6	150479	23643	0	0
T7	168924	25369	0	0
T11	3847	283	0	0
T12	385042	129428	0	0
T17	1554	32	0	0
T18	270103	67451	0	0
T19	1186	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385552961	384744294	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	385552961	98801010	0	0
GntImpliesValid_A	385552961	98801010	0	0
GrantKnown_A	385552961	384744294	0	0
IdxKnown_A	385552961	384744294	0	0
IndexIsCorrect_A	385552961	98801010	0	0
NoReadyValidNoGrant_A	385552961	44003977	0	0
Priority_A	385552961	104709929	0	0
ReadyAndValidImplyGrant_A	385552961	98801010	0	0
ReqAndReadyImplyGrant_A	385552961	98801010	0	0
ReqImpliesValid_A	385552961	104709929	0	0
ValidKnown_A	385552961	384744294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	44003977	0	0
T2	384684	43277	0	0
T3	1934	22	0	0
T6	150479	37539	0	0
T7	168924	54533	0	0
T11	3847	0	0	0
T12	385042	524288	0	0
T17	1554	0	0	0
T18	270103	153	0	0
T19	1186	0	0	0
T27	0	12	0	0
T28	62138	16630	0	0
T34	0	25128	0	0
T57	0	479	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	104709929	0	0
T1	1840	5	0	0
T2	384684	150253	0	0
T3	1934	7	0	0
T6	150479	24470	0	0
T7	168924	21302	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	10468	0	0
T57	0	1132	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	104709929	0	0
T1	1840	5	0	0
T2	384684	150253	0	0
T3	1934	7	0	0
T6	150479	24470	0	0
T7	168924	21302	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	10468	0	0
T57	0	1132	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385552961	384744294	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	385552961	98801010	0	0
GntImpliesValid_A	385552961	98801010	0	0
GrantKnown_A	385552961	384744294	0	0
IdxKnown_A	385552961	384744294	0	0
IndexIsCorrect_A	385552961	98801010	0	0
NoReadyValidNoGrant_A	385552961	44003977	0	0
Priority_A	385552961	104709929	0	0
ReadyAndValidImplyGrant_A	385552961	98801010	0	0
ReqAndReadyImplyGrant_A	385552961	98801010	0	0
ReqImpliesValid_A	385552961	104709929	0	0
ValidKnown_A	385552961	384744294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	44003977	0	0
T2	384684	43277	0	0
T3	1934	22	0	0
T6	150479	37539	0	0
T7	168924	54533	0	0
T11	3847	0	0	0
T12	385042	524288	0	0
T17	1554	0	0	0
T18	270103	153	0	0
T19	1186	0	0	0
T27	0	12	0	0
T28	62138	16630	0	0
T34	0	25128	0	0
T57	0	479	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	104709929	0	0
T1	1840	5	0	0
T2	384684	150253	0	0
T3	1934	7	0	0
T6	150479	24470	0	0
T7	168924	21302	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	10468	0	0
T57	0	1132	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	98801010	0	0
T1	1840	5	0	0
T2	384684	131804	0	0
T3	1934	7	0	0
T6	150479	22456	0	0
T7	168924	20282	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	8321	0	0
T57	0	1084	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	104709929	0	0
T1	1840	5	0	0
T2	384684	150253	0	0
T3	1934	7	0	0
T6	150479	24470	0	0
T7	168924	21302	0	0
T11	3847	0	0	0
T12	385042	127897	0	0
T17	1554	0	0	0
T18	270103	199009	0	0
T19	1186	0	0	0
T27	0	3	0	0
T28	0	10468	0	0
T57	0	1132	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	384744294	0	0
T1	1840	1679	0	0
T2	384684	384605	0	0
T3	1934	1797	0	0
T6	150479	150354	0	0
T7	168924	168779	0	0
T11	3847	3125	0	0
T12	385042	385025	0	0
T17	1554	1461	0	0
T18	270103	270038	0	0
T19	1186	1103	0	0