Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.96			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.27	100.00	89.08			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T71,T72,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T18,T27

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T71,T72,T81
0	0	1	-	-	Covered	T3,T18,T27
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5335619	0	0
UpdateCheck_A	2147483647	5335610	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5335619	0	0
T2	3077472	44465	0	0
T3	15472	27	0	0
T4	0	1024	0	0
T5	0	84	0	0
T6	1203832	29872	0	0
T7	1351392	31068	0	0
T11	30776	0	0	0
T12	3080336	0	0	0
T17	12432	0	0	0
T18	2160824	93	0	0
T19	9488	0	0	0
T20	0	146	0	0
T27	0	25	0	0
T28	497104	19809	0	0
T34	0	21193	0	0
T57	0	116	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5335610	0	0
T2	3077472	44465	0	0
T3	15472	27	0	0
T4	0	1024	0	0
T5	0	84	0	0
T6	1203832	29872	0	0
T7	1351392	31068	0	0
T11	30776	0	0	0
T12	3080336	0	0	0
T17	12432	0	0	0
T18	2160824	93	0	0
T19	9488	0	0	0
T20	0	146	0	0
T27	0	25	0	0
T28	497104	19809	0	0
T34	0	21193	0	0
T57	0	116	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T71,T72,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T18,T4

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T71,T72,T81
0	0	1	-	-	Covered	T3,T18,T4
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	642284	0	0
UpdateCheck_A	385552961	642282	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642284	0	0
T2	384684	5576	0	0
T3	1934	7	0	0
T4	0	256	0	0
T6	150479	3670	0	0
T7	168924	4145	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	14	0	0
T19	1186	0	0	0
T27	0	6	0	0
T28	62138	2872	0	0
T34	0	3270	0	0
T57	0	18	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642282	0	0
T2	384684	5576	0	0
T3	1934	7	0	0
T4	0	256	0	0
T6	150479	3670	0	0
T7	168924	4145	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	14	0	0
T19	1186	0	0	0
T27	0	6	0	0
T28	62138	2872	0	0
T34	0	3270	0	0
T57	0	18	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T71,T72,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T4,T5

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T71,T72,T81
0	0	1	-	-	Covered	T18,T4,T5
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	642236	0	0
UpdateCheck_A	385552961	642234	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642236	0	0
T2	384684	5622	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3672	0	0
T7	168924	4132	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	14	0	0
T19	1186	0	0	0
T27	0	5	0	0
T28	62138	2873	0	0
T34	0	3277	0	0
T57	0	17	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642234	0	0
T2	384684	5622	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3672	0	0
T7	168924	4132	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	14	0	0
T19	1186	0	0	0
T27	0	5	0	0
T28	62138	2873	0	0
T34	0	3277	0	0
T57	0	17	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T72,T81,T82

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T4,T5

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T72,T81,T82
0	0	1	-	-	Covered	T18,T4,T5
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	642317	0	0
UpdateCheck_A	385552961	642317	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642317	0	0
T2	384684	5660	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3671	0	0
T7	168924	4150	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	13	0	0
T19	1186	0	0	0
T27	0	5	0	0
T28	62138	2885	0	0
T34	0	3293	0	0
T57	0	18	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	642317	0	0
T2	384684	5660	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3671	0	0
T7	168924	4150	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	13	0	0
T19	1186	0	0	0
T27	0	5	0	0
T28	62138	2885	0	0
T34	0	3293	0	0
T57	0	18	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T72,T82,T83

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T27,T4

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T72,T82,T83
0	0	1	-	-	Covered	T18,T27,T4
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	641720	0	0
UpdateCheck_A	385552961	641717	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	641720	0	0
T2	384684	5592	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3667	0	0
T7	168924	4142	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	13	0	0
T19	1186	0	0	0
T27	0	6	0	0
T28	62138	2862	0	0
T34	0	3276	0	0
T57	0	18	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	641717	0	0
T2	384684	5592	0	0
T3	1934	5	0	0
T4	0	256	0	0
T6	150479	3667	0	0
T7	168924	4142	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	13	0	0
T19	1186	0	0	0
T27	0	6	0	0
T28	62138	2862	0	0
T34	0	3276	0	0
T57	0	18	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T83,T84,T85

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T5,T20

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T83,T14,T84
0	0	1	-	-	Covered	T18,T5,T20
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	692089	0	0
UpdateCheck_A	385552961	692088	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	692089	0	0
T2	384684	5526	0	0
T3	1934	2	0	0
T5	0	21	0	0
T6	150479	3806	0	0
T7	168924	3626	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2079	0	0
T34	0	2020	0	0
T57	0	12	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	692088	0	0
T2	384684	5526	0	0
T3	1934	2	0	0
T5	0	21	0	0
T6	150479	3806	0	0
T7	168924	3626	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2079	0	0
T34	0	2020	0	0
T57	0	12	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T83,T84,T85

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T5,T20

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T83,T14,T84
0	0	1	-	-	Covered	T18,T5,T20
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	691801	0	0
UpdateCheck_A	385552961	691801	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691801	0	0
T2	384684	5485	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3797	0	0
T7	168924	3620	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2079	0	0
T34	0	2019	0	0
T57	0	11	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691801	0	0
T2	384684	5485	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3797	0	0
T7	168924	3620	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2079	0	0
T34	0	2019	0	0
T57	0	11	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T83,T84,T85

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T5,T20

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T83,T14,T84
0	0	1	-	-	Covered	T18,T5,T20
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	691711	0	0
UpdateCheck_A	385552961	691711	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691711	0	0
T2	384684	5510	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3798	0	0
T7	168924	3622	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2080	0	0
T34	0	2019	0	0
T57	0	11	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691711	0	0
T2	384684	5510	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3798	0	0
T7	168924	3622	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	10	0	0
T19	1186	0	0	0
T27	0	1	0	0
T28	62138	2080	0	0
T34	0	2019	0	0
T57	0	11	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T83,T84,T85

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T18,T5,T20

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T83,T14,T84
0	0	1	-	-	Covered	T18,T5,T20
0	0	0	1	-	Covered	T2,T3,T6
0	0	0	0	1	Covered	T2,T3,T6
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	385552961	691461	0	0
UpdateCheck_A	385552961	691460	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691461	0	0
T2	384684	5494	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3791	0	0
T7	168924	3631	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	9	0	0
T19	1186	0	0	0
T20	0	146	0	0
T28	62138	2079	0	0
T34	0	2019	0	0
T57	0	11	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385552961	691460	0	0
T2	384684	5494	0	0
T3	1934	1	0	0
T5	0	21	0	0
T6	150479	3791	0	0
T7	168924	3631	0	0
T11	3847	0	0	0
T12	385042	0	0	0
T17	1554	0	0	0
T18	270103	9	0	0
T19	1186	0	0	0
T20	0	146	0	0
T28	62138	2079	0	0
T34	0	2019	0	0
T57	0	11	0	0