Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi 100.00 100.00 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
67.86 35.71 100.00 gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
71.43 42.86 100.00 gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_sec_buf.u_prim_sec_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 22080 20148 0 0
T2 4616208 4615260 0 0
T3 23208 21564 0 0
T6 1805748 1804248 0 0
T7 2027088 2025348 0 0
T11 46164 37500 0 0
T12 4620504 4620300 0 0
T17 18648 17532 0 0
T18 3241236 3240456 0 0
T19 14232 13236 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 385553117 384744450 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 385553117 384744450 0 0
T1 1840 1679 0 0
T2 384684 384605 0 0
T3 1934 1797 0 0
T6 150479 150354 0 0
T7 168924 168779 0 0
T11 3847 3125 0 0
T12 385042 385025 0 0
T17 1554 1461 0 0
T18 270103 270038 0 0
T19 1186 1103 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%