Line Coverage for Module :
flash_mp
| Line No. | Total | Covered | Percent |
TOTAL | | 76 | 76 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 129 | 1 | 1 | 100.00 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 179 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
ALWAYS | 185 | 0 | 0 | |
ALWAYS | 185 | 2 | 2 | 100.00 |
CONT_ASSIGN | 191 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
CONT_ASSIGN | 198 | 1 | 1 | 100.00 |
CONT_ASSIGN | 201 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 206 | 1 | 1 | 100.00 |
CONT_ASSIGN | 209 | 1 | 1 | 100.00 |
CONT_ASSIGN | 212 | 1 | 1 | 100.00 |
CONT_ASSIGN | 215 | 1 | 1 | 100.00 |
ALWAYS | 240 | 10 | 10 | 100.00 |
CONT_ASSIGN | 262 | 1 | 1 | 100.00 |
CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
CONT_ASSIGN | 269 | 1 | 1 | 100.00 |
CONT_ASSIGN | 270 | 1 | 1 | 100.00 |
CONT_ASSIGN | 271 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
CONT_ASSIGN | 281 | 1 | 1 | 100.00 |
CONT_ASSIGN | 289 | 1 | 1 | 100.00 |
CONT_ASSIGN | 290 | 1 | 1 | 100.00 |
CONT_ASSIGN | 291 | 1 | 1 | 100.00 |
CONT_ASSIGN | 292 | 1 | 1 | 100.00 |
CONT_ASSIGN | 293 | 1 | 1 | 100.00 |
CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
CONT_ASSIGN | 295 | 1 | 1 | 100.00 |
CONT_ASSIGN | 296 | 1 | 1 | 100.00 |
CONT_ASSIGN | 301 | 1 | 1 | 100.00 |
ALWAYS | 307 | 6 | 6 | 100.00 |
CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 318 | 1 | 1 | 100.00 |
CONT_ASSIGN | 319 | 1 | 1 | 100.00 |
CONT_ASSIGN | 324 | 1 | 1 | 100.00 |
CONT_ASSIGN | 325 | 1 | 1 | 100.00 |
CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
CONT_ASSIGN | 375 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
78 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
100 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
121 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
149 |
9 |
9 |
174 |
1 |
1 |
179 |
1 |
1 |
180 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
195 |
1 |
1 |
198 |
1 |
1 |
201 |
1 |
1 |
204 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
243 |
1 |
1 |
245 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
257 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
266 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
271 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
281 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
291 |
1 |
1 |
292 |
1 |
1 |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
301 |
1 |
1 |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
|
|
|
MISSING_ELSE |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
319 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
375 |
1 |
1 |
Cond Coverage for Module :
flash_mp
| Total | Covered | Percent |
Conditions | 139 | 137 | 98.56 |
Logical | 139 | 137 | 98.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (if_sel_i == HwSel)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (req_part_i == FlashPartData)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 105
EXPRESSION (req_part_i == FlashPartInfo)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 129
EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 132
EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
--1-- --------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T28,T34,T31 |
LINE 132
SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
-----------1---------- ------2----- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T37,T93,T94 |
0 | 1 | 0 | Unreachable | |
1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 154
EXPRESSION (req_i & ((~hw_sel)))
--1-- -----2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (req_i & hw_sel)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 174
EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 186
EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
---------1--------- --------2------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T18,T12,T5 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T12,T24,T25 |
1 | 1 | 1 | Covered | T18,T12,T5 |
LINE 186
SUB-EXPRESSION (bank_addr == i[0])
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 204
EXPRESSION (bk_erase_i & ((|bk_erase_en)))
-----1---- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T12,T5 |
1 | 0 | Covered | T153,T126,T231 |
1 | 1 | Covered | T18,T5,T22 |
LINE 215
EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
--1-- ------2------ -----------------------------------3-----------------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T2,T43,T155 |
LINE 215
SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
-----1---- ------2----- --------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T18,T5,T22 |
0 | 0 | 1 | 0 | Covered | T18,T12,T5 |
0 | 1 | 0 | 0 | Covered | T1,T2,T12 |
1 | 0 | 0 | 0 | Covered | T2,T3,T6 |
LINE 242
EXPRESSION (hw_sel && req_i)
---1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 245
EXPRESSION
Number Term
1 (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) &&
2 (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) &&
3 (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T14 |
1 | Covered | T1,T2,T3 |
LINE 245
SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 263
EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 273
EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
------1------ -----2---- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T18,T5,T22 |
1 | 0 | 1 | Covered | T5,T20,T45 |
1 | 1 | 0 | Covered | T153,T126,T231 |
1 | 1 | 1 | Covered | T153,T125,T126 |
LINE 281
EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
--1-- ------2------ -----------------------------------3-----------------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T11 |
LINE 281
SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
-----1---- ------2----- --------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T153,T125,T126 |
0 | 0 | 1 | 0 | Covered | T11,T12,T13 |
0 | 1 | 0 | 0 | Covered | T2,T3,T12 |
1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 289
EXPRESSION (req_i & (data_rd_en | info_rd_en))
--1-- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 289
SUB-EXPRESSION (data_rd_en | info_rd_en)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
LINE 290
EXPRESSION (req_i & (data_prog_en | info_prog_en))
--1-- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T27 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 290
SUB-EXPRESSION (data_prog_en | info_prog_en)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T12 |
1 | 0 | Covered | T1,T2,T12 |
LINE 291
EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T20,T102 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T11,T12 |
LINE 291
SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T11,T12,T13 |
1 | 0 | Covered | T18,T12,T5 |
LINE 292
EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T5,T22 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T5,T22 |
LINE 292
SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T18,T5,T22 |
LINE 293
EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
--1-- ------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T6,T18 |
1 | 1 | Covered | T1,T2,T3 |
LINE 293
SUB-EXPRESSION (data_scramble_en | info_scramble_en)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 294
EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
--1-- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 294
SUB-EXPRESSION (data_ecc_en | info_ecc_en)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 295
EXPRESSION (req_i & (data_he_en | info_he_en))
--1-- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T28 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 295
SUB-EXPRESSION (data_he_en | info_he_en)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T6,T18 |
LINE 296
EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
--1- ---2-- -----3---- -----4----
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Covered | T18,T5,T22 |
0 | 0 | 1 | 0 | Covered | T18,T11,T12 |
0 | 1 | 0 | 0 | Covered | T1,T2,T3 |
1 | 0 | 0 | 0 | Covered | T1,T2,T3 |
LINE 316
EXPRESSION (rd_done_i | txn_err)
----1---- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 317
EXPRESSION (prog_done_i | txn_err)
-----1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 318
EXPRESSION (erase_done_i | txn_err)
------1----- ---2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T11 |
1 | 0 | Covered | T18,T12,T13 |
LINE 324
EXPRESSION (pg_erase_o | bk_erase_o)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T5,T22 |
1 | 0 | Covered | T18,T11,T12 |
LINE 325
EXPRESSION (erase_valid & erase_suspend_i)
-----1----- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T178,T185 |
1 | 0 | Covered | T18,T11,T12 |
1 | 1 | Covered | T18,T95,T96 |
LINE 326
EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
------------------1----------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T18,T95,T96 |
1 | 0 | Covered | T18,T178,T185 |
LINE 326
SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
-------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T95,T96 |
1 | 1 | Covered | T18,T178,T185 |
LINE 326
SUB-EXPRESSION (erase_suspend_o & erase_done_o)
-------1------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T18,T95,T96 |
1 | 1 | Covered | T18,T95,T96 |
Branch Coverage for Module :
flash_mp
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
TERNARY |
129 |
2 |
2 |
100.00 |
TERNARY |
174 |
2 |
2 |
100.00 |
TERNARY |
263 |
2 |
2 |
100.00 |
IF |
242 |
2 |
2 |
100.00 |
IF |
307 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 129 (data_part_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 174 (hw_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 263 (hw_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 242 if ((hw_sel && req_i))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_ni))
-2-: 309 if (txn_err)
-3-: 311 if (no_allowed_txn)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T11 |
0 |
0 |
1 |
Covered |
T1,T2,T11 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_mp
Assertion Details
BankEraseData_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
8717982 |
0 |
0 |
T5 |
0 |
131080 |
0 |
0 |
T7 |
168924 |
0 |
0 |
0 |
T11 |
3847 |
0 |
0 |
0 |
T12 |
385042 |
0 |
0 |
0 |
T13 |
241186 |
0 |
0 |
0 |
T18 |
270103 |
262488 |
0 |
0 |
T19 |
1186 |
0 |
0 |
0 |
T22 |
0 |
131080 |
0 |
0 |
T27 |
2255 |
0 |
0 |
0 |
T28 |
62138 |
0 |
0 |
0 |
T61 |
110629 |
0 |
0 |
0 |
T64 |
2954 |
0 |
0 |
0 |
T156 |
0 |
65540 |
0 |
0 |
T232 |
0 |
327700 |
0 |
0 |
T233 |
0 |
458780 |
0 |
0 |
T234 |
0 |
458780 |
0 |
0 |
T235 |
0 |
65540 |
0 |
0 |
T236 |
0 |
65540 |
0 |
0 |
T237 |
0 |
589860 |
0 |
0 |
BankEraseInfo_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
10486402 |
0 |
0 |
T55 |
1573 |
0 |
0 |
0 |
T92 |
66504 |
0 |
0 |
0 |
T125 |
163937 |
117972 |
0 |
0 |
T126 |
0 |
393240 |
0 |
0 |
T127 |
0 |
589860 |
0 |
0 |
T128 |
0 |
65542 |
0 |
0 |
T129 |
0 |
393240 |
0 |
0 |
T144 |
160949 |
0 |
0 |
0 |
T153 |
779646 |
262160 |
0 |
0 |
T158 |
0 |
655400 |
0 |
0 |
T159 |
0 |
655400 |
0 |
0 |
T160 |
0 |
65540 |
0 |
0 |
T161 |
0 |
589860 |
0 |
0 |
T177 |
565172 |
0 |
0 |
0 |
T206 |
385778 |
0 |
0 |
0 |
T233 |
532079 |
0 |
0 |
0 |
T238 |
156765 |
0 |
0 |
0 |
T239 |
120857 |
0 |
0 |
0 |
DataReqToInfo_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
241849228 |
0 |
0 |
T1 |
1840 |
5 |
0 |
0 |
T2 |
384684 |
302579 |
0 |
0 |
T3 |
1934 |
14 |
0 |
0 |
T6 |
150479 |
88782 |
0 |
0 |
T7 |
168924 |
129021 |
0 |
0 |
T8 |
0 |
30 |
0 |
0 |
T11 |
3847 |
0 |
0 |
0 |
T12 |
385042 |
360652 |
0 |
0 |
T17 |
1554 |
0 |
0 |
0 |
T18 |
270103 |
266792 |
0 |
0 |
T19 |
1186 |
0 |
0 |
0 |
T27 |
0 |
84 |
0 |
0 |
T57 |
0 |
1908 |
0 |
0 |
InReqOutReq_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
268294289 |
0 |
0 |
T1 |
1840 |
343 |
0 |
0 |
T2 |
384684 |
313495 |
0 |
0 |
T3 |
1934 |
556 |
0 |
0 |
T6 |
150479 |
89102 |
0 |
0 |
T7 |
168924 |
129341 |
0 |
0 |
T11 |
3847 |
1309 |
0 |
0 |
T12 |
385042 |
362824 |
0 |
0 |
T17 |
1554 |
160 |
0 |
0 |
T18 |
270103 |
266952 |
0 |
0 |
T19 |
1186 |
160 |
0 |
0 |
InfoReqToData_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
26445061 |
0 |
0 |
T1 |
1840 |
338 |
0 |
0 |
T2 |
384684 |
10916 |
0 |
0 |
T3 |
1934 |
542 |
0 |
0 |
T6 |
150479 |
320 |
0 |
0 |
T7 |
168924 |
320 |
0 |
0 |
T11 |
3847 |
1309 |
0 |
0 |
T12 |
385042 |
21712 |
0 |
0 |
T17 |
1554 |
160 |
0 |
0 |
T18 |
270103 |
160 |
0 |
0 |
T19 |
1186 |
160 |
0 |
0 |
NoReqWhenErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
380242474 |
129954 |
0 |
0 |
T1 |
1840 |
18 |
0 |
0 |
T2 |
384684 |
1330 |
0 |
0 |
T3 |
1934 |
0 |
0 |
0 |
T4 |
0 |
480 |
0 |
0 |
T6 |
150479 |
0 |
0 |
0 |
T7 |
168924 |
0 |
0 |
0 |
T11 |
2270 |
0 |
0 |
0 |
T12 |
385017 |
0 |
0 |
0 |
T17 |
1554 |
0 |
0 |
0 |
T18 |
270103 |
0 |
0 |
0 |
T19 |
1186 |
0 |
0 |
0 |
T28 |
0 |
422 |
0 |
0 |
T34 |
0 |
20 |
0 |
0 |
T39 |
0 |
494 |
0 |
0 |
T40 |
0 |
170 |
0 |
0 |
T43 |
0 |
452 |
0 |
0 |
T62 |
0 |
1148 |
0 |
0 |
T155 |
0 |
96 |
0 |
0 |
bkEraseEnOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
19204384 |
0 |
0 |
T5 |
0 |
131080 |
0 |
0 |
T7 |
168924 |
0 |
0 |
0 |
T11 |
3847 |
0 |
0 |
0 |
T12 |
385042 |
0 |
0 |
0 |
T13 |
241186 |
0 |
0 |
0 |
T18 |
270103 |
262488 |
0 |
0 |
T19 |
1186 |
0 |
0 |
0 |
T22 |
0 |
131080 |
0 |
0 |
T27 |
2255 |
0 |
0 |
0 |
T28 |
62138 |
0 |
0 |
0 |
T61 |
110629 |
0 |
0 |
0 |
T64 |
2954 |
0 |
0 |
0 |
T125 |
0 |
117972 |
0 |
0 |
T153 |
0 |
262160 |
0 |
0 |
T156 |
0 |
65540 |
0 |
0 |
T232 |
0 |
327700 |
0 |
0 |
T233 |
0 |
458780 |
0 |
0 |
T234 |
0 |
458780 |
0 |
0 |
T235 |
0 |
65540 |
0 |
0 |
hwInfoRuleOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
153801769 |
0 |
0 |
T1 |
1840 |
320 |
0 |
0 |
T2 |
384684 |
160 |
0 |
0 |
T3 |
1934 |
320 |
0 |
0 |
T6 |
150479 |
320 |
0 |
0 |
T7 |
168924 |
320 |
0 |
0 |
T11 |
3847 |
1309 |
0 |
0 |
T12 |
385042 |
362824 |
0 |
0 |
T17 |
1554 |
160 |
0 |
0 |
T18 |
270103 |
160 |
0 |
0 |
T19 |
1186 |
160 |
0 |
0 |
invalidReqOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
268164291 |
0 |
0 |
T1 |
1840 |
325 |
0 |
0 |
T2 |
384684 |
312165 |
0 |
0 |
T3 |
1934 |
556 |
0 |
0 |
T6 |
150479 |
89102 |
0 |
0 |
T7 |
168924 |
129341 |
0 |
0 |
T11 |
3847 |
1308 |
0 |
0 |
T12 |
385042 |
362824 |
0 |
0 |
T17 |
1554 |
160 |
0 |
0 |
T18 |
270103 |
266952 |
0 |
0 |
T19 |
1186 |
160 |
0 |
0 |
requestTypesOnehot_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385553117 |
268164291 |
0 |
0 |
T1 |
1840 |
325 |
0 |
0 |
T2 |
384684 |
312165 |
0 |
0 |
T3 |
1934 |
556 |
0 |
0 |
T6 |
150479 |
89102 |
0 |
0 |
T7 |
168924 |
129341 |
0 |
0 |
T11 |
3847 |
1308 |
0 |
0 |
T12 |
385042 |
362824 |
0 |
0 |
T17 |
1554 |
160 |
0 |
0 |
T18 |
270103 |
266952 |
0 |
0 |
T19 |
1186 |
160 |
0 |
0 |