SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.96 | 100.00 | 93.75 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.85 | 97.12 | 94.40 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.89 | 97.67 | 84.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10450 | 10450 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21690 |
gen_no_flops.OutputDelay_A | 758519012 | 756901678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10450 | 10450 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T11 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 18400 | 16790 | 0 | 0 |
T2 | 3846840 | 3846050 | 0 | 0 |
T3 | 19340 | 17970 | 0 | 0 |
T6 | 1504790 | 1503540 | 0 | 0 |
T7 | 1689240 | 1687790 | 0 | 0 |
T11 | 38470 | 31250 | 0 | 0 |
T12 | 3850420 | 3850250 | 0 | 0 |
T17 | 6450 | 5520 | 0 | 0 |
T18 | 2701030 | 2700380 | 0 | 0 |
T19 | 4000 | 3170 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21690 |
T1 | 14720 | 13384 | 0 | 24 |
T2 | 3077472 | 3076816 | 0 | 24 |
T3 | 15472 | 14328 | 0 | 24 |
T6 | 1203832 | 1202784 | 0 | 24 |
T7 | 1351392 | 1350184 | 0 | 24 |
T11 | 30776 | 24784 | 0 | 24 |
T12 | 3080336 | 3080192 | 0 | 24 |
T17 | 5160 | 4416 | 0 | 0 |
T18 | 2160824 | 2160280 | 0 | 24 |
T19 | 3200 | 2536 | 0 | 0 |
T28 | 0 | 0 | 0 | 24 |
T64 | 0 | 0 | 0 | 24 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 758519012 | 756901678 | 0 | 0 |
T1 | 3680 | 3358 | 0 | 0 |
T2 | 769368 | 769210 | 0 | 0 |
T3 | 3868 | 3594 | 0 | 0 |
T6 | 300958 | 300708 | 0 | 0 |
T7 | 337848 | 337558 | 0 | 0 |
T11 | 7694 | 6250 | 0 | 0 |
T12 | 770084 | 770050 | 0 | 0 |
T17 | 1290 | 1104 | 0 | 0 |
T18 | 540206 | 540076 | 0 | 0 |
T19 | 800 | 634 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259662 | 378450995 | 0 | 0 |
gen_flops.OutputDelay_A | 379259662 | 378419156 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378450995 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259662 | 378419156 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259506 | 378450839 | 0 | 0 |
gen_no_flops.OutputDelay_A | 379259506 | 378450839 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378450839 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378450839 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379234256 | 378425589 | 0 | 0 |
gen_flops.OutputDelay_A | 379234256 | 378393900 | 0 | 2580 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379234256 | 378425589 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379234256 | 378393900 | 0 | 2580 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259506 | 378450839 | 0 | 0 |
gen_no_flops.OutputDelay_A | 379259506 | 378450839 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378450839 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378450839 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1045 | 1045 | 0 | 0 |
OutputsKnown_A | 379259506 | 378450839 | 0 | 0 |
gen_flops.OutputDelay_A | 379259506 | 378419015 | 0 | 2730 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1045 | 1045 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378450839 | 0 | 0 |
T1 | 1840 | 1679 | 0 | 0 |
T2 | 384684 | 384605 | 0 | 0 |
T3 | 1934 | 1797 | 0 | 0 |
T6 | 150479 | 150354 | 0 | 0 |
T7 | 168924 | 168779 | 0 | 0 |
T11 | 3847 | 3125 | 0 | 0 |
T12 | 385042 | 385025 | 0 | 0 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270038 | 0 | 0 |
T19 | 400 | 317 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 379259506 | 378419015 | 0 | 2730 |
T1 | 1840 | 1673 | 0 | 3 |
T2 | 384684 | 384602 | 0 | 3 |
T3 | 1934 | 1791 | 0 | 3 |
T6 | 150479 | 150348 | 0 | 3 |
T7 | 168924 | 168773 | 0 | 3 |
T11 | 3847 | 3098 | 0 | 3 |
T12 | 385042 | 385024 | 0 | 3 |
T17 | 645 | 552 | 0 | 0 |
T18 | 270103 | 270035 | 0 | 3 |
T19 | 400 | 317 | 0 | 0 |
T28 | 0 | 0 | 0 | 3 |
T64 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |