SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 31431068 | 1 | T1 | 30535 | T2 | 403 | T3 | 6411 | |||
auto[1] | 5260253 | 1 | T1 | 7544 | T2 | 94 | T3 | 8704 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36691129 | 1 | T1 | 38079 | T2 | 497 | T3 | 15115 | |||
values[1] | 23 | 1 | T64 | 1 | T201 | 1 | T241 | 1 | |||
values[2] | 5 | 1 | T96 | 1 | T201 | 1 | T241 | 1 | |||
values[3] | 95 | 1 | T64 | 4 | T96 | 3 | T201 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 36691117 | 1 | T1 | 38079 | T2 | 497 | T3 | 15115 | |||
values[1] | 19 | 1 | T96 | 2 | T201 | 2 | T241 | 1 | |||
values[2] | 8 | 1 | T64 | 3 | T236 | 1 | T276 | 1 | |||
values[3] | 107 | 1 | T64 | 8 | T96 | 5 | T201 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 36691031 | 1 | T1 | 38079 | T2 | 497 | T3 | 15115 | |||
auto[TlIntgErrCmd] | 86 | 1 | T64 | 3 | T96 | 3 | T201 | 10 | |||
auto[TlIntgErrData] | 98 | 1 | T64 | 10 | T96 | 3 | T201 | 6 | |||
auto[TlIntgErrBoth] | 106 | 1 | T64 | 7 | T96 | 4 | T201 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4189405 | 0 | T2 | 9 | T14 | 9 | T5 | 40886 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4189205 | 1 | T2 | 9 | T14 | 9 | T5 | 40886 | |||
values[1] | 26 | 1 | T64 | 2 | T201 | 1 | T236 | 1 | |||
values[2] | 5 | 1 | T64 | 1 | T279 | 1 | T350 | 2 | |||
values[3] | 101 | 1 | T64 | 5 | T96 | 3 | T201 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4189232 | 1 | T2 | 9 | T14 | 9 | T5 | 40886 | |||
values[1] | 14 | 1 | T64 | 1 | T201 | 1 | T236 | 1 | |||
values[2] | 7 | 1 | T241 | 1 | T276 | 1 | T272 | 2 | |||
values[3] | 77 | 1 | T64 | 3 | T96 | 4 | T201 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4189131 | 1 | T2 | 9 | T14 | 9 | T5 | 40886 | |||
auto[TlIntgErrCmd] | 101 | 1 | T64 | 6 | T96 | 3 | T201 | 9 | |||
auto[TlIntgErrData] | 74 | 1 | T64 | 7 | T96 | 3 | T201 | 4 | |||
auto[TlIntgErrBoth] | 99 | 1 | T64 | 6 | T96 | 3 | T201 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 81718 | 0 | T63 | 135 | T64 | 1214 | T96 | 617 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 81521 | 1 | T63 | 135 | T64 | 1200 | T96 | 611 | |||
values[1] | 19 | 1 | T64 | 2 | T201 | 3 | T241 | 1 | |||
values[2] | 2 | 1 | T241 | 1 | T351 | 1 | - | - | |||
values[3] | 113 | 1 | T64 | 8 | T96 | 3 | T201 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 81519 | 1 | T63 | 135 | T64 | 1199 | T96 | 609 | |||
values[1] | 12 | 1 | T64 | 1 | T201 | 1 | T236 | 1 | |||
values[2] | 1 | 1 | T64 | 1 | - | - | - | - | |||
values[3] | 102 | 1 | T64 | 9 | T96 | 3 | T201 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 81428 | 1 | T63 | 135 | T64 | 1194 | T96 | 607 | |||
auto[TlIntgErrCmd] | 91 | 1 | T64 | 5 | T96 | 2 | T201 | 10 | |||
auto[TlIntgErrData] | 93 | 1 | T64 | 6 | T96 | 4 | T201 | 6 | |||
auto[TlIntgErrBoth] | 106 | 1 | T64 | 9 | T96 | 4 | T201 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |