Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	28874271	1		T1	21894		T2	321		T3	5753
full_word	7817050	1		T1	16185		T2	176		T3	9362

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36691031	1		T1	38079		T2	497		T3	15115
auto[TlIntgErrCmd]	86	1		T64	3		T96	3		T201	10
auto[TlIntgErrData]	98	1		T64	10		T96	3		T201	6
auto[TlIntgErrBoth]	106	1		T64	7		T96	4		T201	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32125519	1		T1	25910		T2	407		T3	10783
auto[1]	4565802	1		T1	12169		T2	90		T3	4332

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	28148831	1		T1	20325		T2	308		T3	5550
auto[TlIntgErrNone]	partial	auto[1]	725178	1		T1	1569		T2	13		T3	203
auto[TlIntgErrNone]	full_word	auto[0]	3976565	1		T1	5585		T2	99		T3	5233
auto[TlIntgErrNone]	full_word	auto[1]	3840457	1		T1	10600		T2	77		T3	4129
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T96	1		T201	8		T241	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T64	3		T96	2		T201	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T236	1		T272	1		T352	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T279	1		T353	1		T351	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T64	1		T96	1		T201	4
auto[TlIntgErrData]	partial	auto[1]	47	1		T64	8		T96	2		T201	2
auto[TlIntgErrData]	full_word	auto[0]	8	1		T64	1		T276	2		T354	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T274	1		T279	2		T355	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T64	2		T96	1		T201	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T64	4		T96	3		T201	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T64	1		T350	1		T351	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T272	2		T353	1		T355	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19756	1		T63	50		T64	19		T96	9
full_word	4169649	1		T2	9		T14	9		T5	40886

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4189131	1		T2	9		T14	9		T5	40886
auto[TlIntgErrCmd]	101	1		T64	6		T96	3		T201	9
auto[TlIntgErrData]	74	1		T64	7		T96	3		T201	4
auto[TlIntgErrBoth]	99	1		T64	6		T96	3		T201	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4164219	1		T2	9		T14	9		T5	40886
auto[1]	25186	1		T63	62		T64	10		T96	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1180	1		T63	1		T199	2		T200	47
auto[TlIntgErrNone]	partial	auto[1]	18322	1		T63	49		T199	19		T200	408
auto[TlIntgErrNone]	full_word	auto[0]	4162930	1		T2	9		T14	9		T5	40886
auto[TlIntgErrNone]	full_word	auto[1]	6699	1		T63	13		T199	8		T200	70
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T64	2		T201	3		T236	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T64	4		T96	3		T201	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T278	1		T352	1		T356	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T201	1		T276	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	33	1		T64	3		T96	1		T201	2
auto[TlIntgErrData]	partial	auto[1]	37	1		T64	4		T96	2		T201	1
auto[TlIntgErrData]	full_word	auto[0]	1	1		T272	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T201	1		T236	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T64	4		T96	1		T201	1
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T64	2		T96	2		T201	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T272	1		T274	1		T351	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T274	1		T351	1		-	-