Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1595661188	1592323540	0	0
CheckNGreaterZero_A	4192	4192	0	0
GntImpliesReady_A	1595661188	408046403	0	0
GntImpliesValid_A	1595661188	408046403	0	0
GrantKnown_A	1595661188	1592323540	0	0
IdxKnown_A	1595661188	1592323540	0	0
IndexIsCorrect_A	1595661188	408046403	0	0
NoReadyValidNoGrant_A	1595661188	178270213	0	0
Priority_A	1595661188	432193736	0	0
ReadyAndValidImplyGrant_A	1595661188	408046403	0	0
ReqAndReadyImplyGrant_A	1595661188	408046403	0	0
ReqImpliesValid_A	1595661188	432193736	0	0
ValidKnown_A	1595661188	1592323540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	1592323540	0	0
T1	1712728	1649704	0	0
T2	8924	8412	0	0
T3	430668	430356	0	0
T5	1702156	1701808	0	0
T9	3088	2876	0	0
T14	11244	10516	0	0
T15	4108	3832	0	0
T16	7180	6976	0	0
T17	8272	7892	0	0
T18	4696	4440	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4192	4192	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	408046403	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	16562	0	0
T5	1702156	511126	0	0
T6	0	4	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	408046403	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	16562	0	0
T5	1702156	511126	0	0
T6	0	4	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	1592323540	0	0
T1	1712728	1649704	0	0
T2	8924	8412	0	0
T3	430668	430356	0	0
T5	1702156	1701808	0	0
T9	3088	2876	0	0
T14	11244	10516	0	0
T15	4108	3832	0	0
T16	7180	6976	0	0
T17	8272	7892	0	0
T18	4696	4440	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	1592323540	0	0
T1	1712728	1649704	0	0
T2	8924	8412	0	0
T3	430668	430356	0	0
T5	1702156	1701808	0	0
T9	3088	2876	0	0
T14	11244	10516	0	0
T15	4108	3832	0	0
T16	7180	6976	0	0
T17	8272	7892	0	0
T18	4696	4440	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	408046403	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	16562	0	0
T5	1702156	511126	0	0
T6	0	4	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	178270213	0	0
T1	856364	77488	0	0
T2	8924	1032	0	0
T3	430668	2816	0	0
T4	0	591660	0	0
T5	1702156	341010	0	0
T9	3088	322	0	0
T10	3104	0	0	0
T14	11244	730	0	0
T15	4108	256	0	0
T16	7180	294	0	0
T17	8272	316	0	0
T18	4696	256	0	0
T19	0	248	0	0
T20	0	24220	0	0
T26	0	12500	0	0
T35	0	44	0	0
T48	0	4	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	432193736	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	261638	0	0
T5	1702156	598224	0	0
T6	0	8	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	408046403	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	16562	0	0
T5	1702156	511126	0	0
T6	0	4	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	408046403	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	16562	0	0
T5	1702156	511126	0	0
T6	0	4	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	432193736	0	0
T1	856364	279728	0	0
T2	8924	456	0	0
T3	430668	1088	0	0
T4	0	261638	0	0
T5	1702156	598224	0	0
T6	0	8	0	0
T9	3088	88	0	0
T10	3104	0	0	0
T14	11244	478	0	0
T15	4108	64	0	0
T16	7180	966	0	0
T17	8272	1178	0	0
T18	4696	64	0	0
T19	0	614	0	0
T35	0	14	0	0
T36	0	780	0	0
T60	0	9650	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1595661188	1592323540	0	0
T1	1712728	1649704	0	0
T2	8924	8412	0	0
T3	430668	430356	0	0
T5	1702156	1701808	0	0
T9	3088	2876	0	0
T14	11244	10516	0	0
T15	4108	3832	0	0
T16	7180	6976	0	0
T17	8272	7892	0	0
T18	4696	4440	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398915297	398080885	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	398915297	116023998	0	0
GntImpliesValid_A	398915297	116023998	0	0
GrantKnown_A	398915297	398080885	0	0
IdxKnown_A	398915297	398080885	0	0
IndexIsCorrect_A	398915297	116023998	0	0
NoReadyValidNoGrant_A	398915297	47250795	0	0
Priority_A	398915297	122120997	0	0
ReadyAndValidImplyGrant_A	398915297	116023998	0	0
ReqAndReadyImplyGrant_A	398915297	116023998	0	0
ReqImpliesValid_A	398915297	122120997	0	0
ValidKnown_A	398915297	398080885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023998	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023998	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023998	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	47250795	0	0
T1	428182	38744	0	0
T2	2231	460	0	0
T3	107667	1408	0	0
T5	425539	85974	0	0
T9	772	161	0	0
T14	2811	341	0	0
T15	1027	128	0	0
T16	1795	128	0	0
T17	2068	158	0	0
T18	1174	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	122120997	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	126702	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023998	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023998	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	122120997	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	126702	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T14,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398915297	398080885	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	398915297	116023935	0	0
GntImpliesValid_A	398915297	116023935	0	0
GrantKnown_A	398915297	398080885	0	0
IdxKnown_A	398915297	398080885	0	0
IndexIsCorrect_A	398915297	116023935	0	0
NoReadyValidNoGrant_A	398915297	47250756	0	0
Priority_A	398915297	122120973	0	0
ReadyAndValidImplyGrant_A	398915297	116023935	0	0
ReqAndReadyImplyGrant_A	398915297	116023935	0	0
ReqImpliesValid_A	398915297	122120973	0	0
ValidKnown_A	398915297	398080885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023935	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023935	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023935	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	47250756	0	0
T1	428182	38744	0	0
T2	2231	460	0	0
T3	107667	1408	0	0
T5	425539	85974	0	0
T9	772	161	0	0
T14	2811	341	0	0
T15	1027	128	0	0
T16	1795	128	0	0
T17	2068	158	0	0
T18	1174	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	122120973	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	126702	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023935	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	116023935	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	102865	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	122120973	0	0
T1	428182	139864	0	0
T2	2231	208	0	0
T3	107667	544	0	0
T5	425539	126702	0	0
T9	772	44	0	0
T14	2811	163	0	0
T15	1027	32	0	0
T16	1795	471	0	0
T17	2068	589	0	0
T18	1174	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T14,T5
1	0	Covered	T2,T14,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T5
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398915297	398080885	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	398915297	87999235	0	0
GntImpliesValid_A	398915297	87999235	0	0
GrantKnown_A	398915297	398080885	0	0
IdxKnown_A	398915297	398080885	0	0
IndexIsCorrect_A	398915297	87999235	0	0
NoReadyValidNoGrant_A	398915297	41884331	0	0
Priority_A	398915297	93975883	0	0
ReadyAndValidImplyGrant_A	398915297	87999235	0	0
ReqAndReadyImplyGrant_A	398915297	87999235	0	0
ReqImpliesValid_A	398915297	93975883	0	0
ValidKnown_A	398915297	398080885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	41884331	0	0
T2	2231	56	0	0
T3	107667	0	0	0
T4	0	295830	0	0
T5	425539	84531	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	24	0	0
T15	1027	0	0	0
T16	1795	19	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	124	0	0
T20	0	12110	0	0
T26	0	6250	0	0
T35	0	22	0	0
T48	0	2	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	93975883	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	130819	0	0
T5	425539	172410	0	0
T6	0	4	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	93975883	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	130819	0	0
T5	425539	172410	0	0
T6	0	4	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T14,T5
1	0	Covered	T2,T14,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T14,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T5
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T5
1	1	Covered	T2,T14,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T14,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398915297	398080885	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	398915297	87999235	0	0
GntImpliesValid_A	398915297	87999235	0	0
GrantKnown_A	398915297	398080885	0	0
IdxKnown_A	398915297	398080885	0	0
IndexIsCorrect_A	398915297	87999235	0	0
NoReadyValidNoGrant_A	398915297	41884331	0	0
Priority_A	398915297	93975883	0	0
ReadyAndValidImplyGrant_A	398915297	87999235	0	0
ReqAndReadyImplyGrant_A	398915297	87999235	0	0
ReqImpliesValid_A	398915297	93975883	0	0
ValidKnown_A	398915297	398080885	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	41884331	0	0
T2	2231	56	0	0
T3	107667	0	0	0
T4	0	295830	0	0
T5	425539	84531	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	24	0	0
T15	1027	0	0	0
T16	1795	19	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	124	0	0
T20	0	12110	0	0
T26	0	6250	0	0
T35	0	22	0	0
T48	0	2	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	93975883	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	130819	0	0
T5	425539	172410	0	0
T6	0	4	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	87999235	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	8281	0	0
T5	425539	152698	0	0
T6	0	2	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	93975883	0	0
T2	2231	20	0	0
T3	107667	0	0	0
T4	0	130819	0	0
T5	425539	172410	0	0
T6	0	4	0	0
T9	772	0	0	0
T10	1552	0	0	0
T14	2811	76	0	0
T15	1027	0	0	0
T16	1795	12	0	0
T17	2068	0	0	0
T18	1174	0	0	0
T19	0	307	0	0
T35	0	7	0	0
T36	0	390	0	0
T60	0	4825	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398915297	398080885	0	0
T1	428182	412426	0	0
T2	2231	2103	0	0
T3	107667	107589	0	0
T5	425539	425452	0	0
T9	772	719	0	0
T14	2811	2629	0	0
T15	1027	958	0	0
T16	1795	1744	0	0
T17	2068	1973	0	0
T18	1174	1110	0	0