Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25412837 1 T1 68 T2 919 T3 2636
full_word 7938269 1 T1 45 T2 2880 T3 2540



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 33350776 1 T1 113 T2 3799 T3 5176
auto[TlIntgErrCmd] 119 1 T63 6 T192 8 T193 5
auto[TlIntgErrData] 111 1 T63 5 T192 4 T193 3
auto[TlIntgErrBoth] 100 1 T63 9 T192 8 T193 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28790695 1 T1 63 T2 1347 T3 5112
auto[1] 4560411 1 T1 50 T2 2452 T3 64



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 24675840 1 T1 63 T2 710 T3 2627
auto[TlIntgErrNone] partial auto[1] 736690 1 T1 5 T2 209 T3 9
auto[TlIntgErrNone] full_word auto[0] 4114699 1 T2 637 T3 2485 T4 12356
auto[TlIntgErrNone] full_word auto[1] 3823547 1 T1 45 T2 2243 T3 55
auto[TlIntgErrCmd] partial auto[0] 45 1 T63 1 T192 6 T193 2
auto[TlIntgErrCmd] partial auto[1] 67 1 T63 5 T192 2 T193 3
auto[TlIntgErrCmd] full_word auto[0] 2 1 T234 1 T349 1 - -
auto[TlIntgErrCmd] full_word auto[1] 5 1 T234 1 T235 1 T265 2
auto[TlIntgErrData] partial auto[0] 54 1 T63 2 T192 3 T236 3
auto[TlIntgErrData] partial auto[1] 48 1 T63 3 T192 1 T193 2
auto[TlIntgErrData] full_word auto[0] 6 1 T193 1 T236 1 T235 1
auto[TlIntgErrData] full_word auto[1] 3 1 T234 1 T264 1 T350 1
auto[TlIntgErrBoth] partial auto[0] 48 1 T63 5 T192 4 T193 2
auto[TlIntgErrBoth] partial auto[1] 45 1 T63 4 T192 4 T236 6
auto[TlIntgErrBoth] full_word auto[0] 1 1 T349 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 6 1 T236 1 T234 1 T235 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 21158 1 T62 211 T63 19 T94 106
full_word 3913925 1 T2 311 T4 16673 T16 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3934781 1 T2 311 T4 16673 T16 4
auto[TlIntgErrCmd] 92 1 T63 3 T192 8 T193 4
auto[TlIntgErrData] 114 1 T63 9 T192 6 T193 4
auto[TlIntgErrBoth] 96 1 T63 8 T192 5 T193 2



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3908523 1 T2 311 T4 16673 T16 4
auto[1] 26560 1 T62 240 T63 13 T94 111



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1346 1 T62 10 T94 8 T191 32
auto[TlIntgErrNone] partial auto[1] 19543 1 T62 201 T94 98 T191 615
auto[TlIntgErrNone] full_word auto[0] 3907067 1 T2 311 T4 16673 T16 4
auto[TlIntgErrNone] full_word auto[1] 6825 1 T62 39 T94 13 T191 137
auto[TlIntgErrCmd] partial auto[0] 20 1 T192 2 T234 1 T235 2
auto[TlIntgErrCmd] partial auto[1] 59 1 T63 3 T192 6 T193 3
auto[TlIntgErrCmd] full_word auto[0] 5 1 T236 1 T348 1 T349 1
auto[TlIntgErrCmd] full_word auto[1] 8 1 T193 1 T236 1 T264 1
auto[TlIntgErrData] partial auto[0] 47 1 T63 3 T192 2 T236 1
auto[TlIntgErrData] partial auto[1] 54 1 T63 5 T192 4 T193 4
auto[TlIntgErrData] full_word auto[0] 5 1 T235 1 T264 1 T351 1
auto[TlIntgErrData] full_word auto[1] 8 1 T63 1 T236 2 T270 1
auto[TlIntgErrBoth] partial auto[0] 30 1 T63 4 T192 1 T193 1
auto[TlIntgErrBoth] partial auto[1] 59 1 T63 4 T192 2 T193 1
auto[TlIntgErrBoth] full_word auto[0] 3 1 T349 1 T351 1 T352 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T192 2 T349 1 T353 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%