Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1536441312	1533057748	0	0
CheckNGreaterZero_A	4156	4156	0	0
GntImpliesReady_A	1536441312	408060159	0	0
GntImpliesValid_A	1536441312	408060159	0	0
GrantKnown_A	1536441312	1533057748	0	0
IdxKnown_A	1536441312	1533057748	0	0
IndexIsCorrect_A	1536441312	408060159	0	0
NoReadyValidNoGrant_A	1536441312	179483681	0	0
Priority_A	1536441312	431710446	0	0
ReadyAndValidImplyGrant_A	1536441312	408060159	0	0
ReqAndReadyImplyGrant_A	1536441312	408060159	0	0
ReqImpliesValid_A	1536441312	431710446	0	0
ValidKnown_A	1536441312	1533057748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	1533057748	0	0
T1	5496	4912	0	0
T2	181096	180712	0	0
T3	1604908	1604844	0	0
T4	278284	277804	0	0
T5	4936	4732	0	0
T6	986728	939960	0	0
T7	290788	290524	0	0
T11	3608	3348	0	0
T16	10992	10420	0	0
T17	1741896	1741616	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4156	4156	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	408060159	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	47538	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138344	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	16930	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	268410	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	408060159	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	47538	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138344	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	16930	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	268410	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	1533057748	0	0
T1	5496	4912	0	0
T2	181096	180712	0	0
T3	1604908	1604844	0	0
T4	278284	277804	0	0
T5	4936	4732	0	0
T6	986728	939960	0	0
T7	290788	290524	0	0
T11	3608	3348	0	0
T16	10992	10420	0	0
T17	1741896	1741616	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	1533057748	0	0
T1	5496	4912	0	0
T2	181096	180712	0	0
T3	1604908	1604844	0	0
T4	278284	277804	0	0
T5	4936	4732	0	0
T6	986728	939960	0	0
T7	290788	290524	0	0
T11	3608	3348	0	0
T16	10992	10420	0	0
T17	1741896	1741616	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	408060159	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	47538	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138344	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	16930	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	268410	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	179483681	0	0
T1	2748	512	0	0
T2	181096	2846	0	0
T3	1604908	2109952	0	0
T4	278284	129168	0	0
T5	4936	256	0	0
T6	986728	56416	0	0
T7	290788	1334	0	0
T11	3608	394	0	0
T16	10992	772	0	0
T17	1741896	3050	0	0
T19	0	806400	0	0
T23	0	631998	0	0
T39	489118	0	0	0
T40	0	20	0	0
T42	0	94084	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	431710446	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	50516	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138576	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	240398	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	341964	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	408060159	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	47538	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138344	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	16930	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	268410	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	408060159	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	47538	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138344	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	16930	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	268410	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	431710446	0	0
T1	2748	152	0	0
T2	181096	1768	0	0
T3	1604908	514650	0	0
T4	278284	50516	0	0
T5	4936	584	0	0
T6	986728	211728	0	0
T7	290788	138576	0	0
T11	3608	118	0	0
T16	10992	358	0	0
T17	1741896	853350	0	0
T19	0	700728	0	0
T23	0	240398	0	0
T39	489118	0	0	0
T40	0	12	0	0
T42	0	341964	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1536441312	1533057748	0	0
T1	5496	4912	0	0
T2	181096	180712	0	0
T3	1604908	1604844	0	0
T4	278284	277804	0	0
T5	4936	4732	0	0
T6	986728	939960	0	0
T7	290788	290524	0	0
T11	3608	3348	0	0
T16	10992	10420	0	0
T17	1741896	1741616	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110328	383264437	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	384110328	105670418	0	0
GntImpliesValid_A	384110328	105670418	0	0
GrantKnown_A	384110328	383264437	0	0
IdxKnown_A	384110328	383264437	0	0
IndexIsCorrect_A	384110328	105670418	0	0
NoReadyValidNoGrant_A	384110328	46375796	0	0
Priority_A	384110328	111599574	0	0
ReadyAndValidImplyGrant_A	384110328	105670418	0	0
ReqAndReadyImplyGrant_A	384110328	105670418	0	0
ReqImpliesValid_A	384110328	111599574	0	0
ValidKnown_A	384110328	383264437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670418	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670418	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670418	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	46375796	0	0
T1	1374	256	0	0
T2	45274	786	0	0
T3	401227	530688	0	0
T4	69571	40322	0	0
T5	1234	128	0	0
T6	246682	28208	0	0
T7	72697	419	0	0
T11	902	197	0	0
T16	2748	378	0	0
T17	435474	899	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	111599574	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	16015	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2316	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670418	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670418	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	111599574	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	16015	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2316	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110328	383264437	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	384110328	105670481	0	0
GntImpliesValid_A	384110328	105670481	0	0
GrantKnown_A	384110328	383264437	0	0
IdxKnown_A	384110328	383264437	0	0
IndexIsCorrect_A	384110328	105670481	0	0
NoReadyValidNoGrant_A	384110328	46375785	0	0
Priority_A	384110328	111599648	0	0
ReadyAndValidImplyGrant_A	384110328	105670481	0	0
ReqAndReadyImplyGrant_A	384110328	105670481	0	0
ReqImpliesValid_A	384110328	111599648	0	0
ValidKnown_A	384110328	383264437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670481	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670481	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670481	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	46375785	0	0
T1	1374	256	0	0
T2	45274	786	0	0
T3	401227	530688	0	0
T4	69571	40322	0	0
T5	1234	128	0	0
T6	246682	28208	0	0
T7	72697	419	0	0
T11	902	197	0	0
T16	2748	378	0	0
T17	435474	899	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	111599648	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	16015	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2316	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670481	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	105670481	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	15586	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2252	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	111599648	0	0
T1	1374	76	0	0
T2	45274	467	0	0
T3	401227	129428	0	0
T4	69571	16015	0	0
T5	1234	292	0	0
T6	246682	105864	0	0
T7	72697	2316	0	0
T11	902	59	0	0
T16	2748	111	0	0
T17	435474	150723	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T7
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16
1	1	Covered	T2,T3,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T7
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110328	383264437	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	384110328	98359738	0	0
GntImpliesValid_A	384110328	98359738	0	0
GrantKnown_A	384110328	383264437	0	0
IdxKnown_A	384110328	383264437	0	0
IndexIsCorrect_A	384110328	98359738	0	0
NoReadyValidNoGrant_A	384110328	43366050	0	0
Priority_A	384110328	104255720	0	0
ReadyAndValidImplyGrant_A	384110328	98359738	0	0
ReqAndReadyImplyGrant_A	384110328	98359738	0	0
ReqImpliesValid_A	384110328	104255720	0	0
ValidKnown_A	384110328	383264437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359738	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359738	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359738	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	43366050	0	0
T2	45274	637	0	0
T3	401227	524288	0	0
T4	69571	24262	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	248	0	0
T11	902	0	0	0
T16	2748	8	0	0
T17	435474	626	0	0
T19	0	403200	0	0
T23	0	315999	0	0
T39	244559	0	0	0
T40	0	10	0	0
T42	0	47042	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	104255720	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	9243	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66972	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	120199	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	170982	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359738	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359738	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	104255720	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	9243	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66972	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	120199	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	170982	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T16
1	0	Covered	T2,T4,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T16,T7
1	0	Covered	T2,T3,T16
1	1	Covered	T2,T4,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T16
1	1	Covered	T2,T3,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T16,T7
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384110328	383264437	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	384110328	98359522	0	0
GntImpliesValid_A	384110328	98359522	0	0
GrantKnown_A	384110328	383264437	0	0
IdxKnown_A	384110328	383264437	0	0
IndexIsCorrect_A	384110328	98359522	0	0
NoReadyValidNoGrant_A	384110328	43366050	0	0
Priority_A	384110328	104255504	0	0
ReadyAndValidImplyGrant_A	384110328	98359522	0	0
ReqAndReadyImplyGrant_A	384110328	98359522	0	0
ReqImpliesValid_A	384110328	104255504	0	0
ValidKnown_A	384110328	383264437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359522	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359522	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359522	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	43366050	0	0
T2	45274	637	0	0
T3	401227	524288	0	0
T4	69571	24262	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	248	0	0
T11	902	0	0	0
T16	2748	8	0	0
T17	435474	626	0	0
T19	0	403200	0	0
T23	0	315999	0	0
T39	244559	0	0	0
T40	0	10	0	0
T42	0	47042	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	104255504	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	9243	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66972	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	120199	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	170982	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359522	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	98359522	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	8183	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66920	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	8465	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	134205	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	104255504	0	0
T2	45274	417	0	0
T3	401227	127897	0	0
T4	69571	9243	0	0
T5	1234	0	0	0
T6	246682	0	0	0
T7	72697	66972	0	0
T11	902	0	0	0
T16	2748	68	0	0
T17	435474	275952	0	0
T19	0	350364	0	0
T23	0	120199	0	0
T39	244559	0	0	0
T40	0	6	0	0
T42	0	170982	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384110328	383264437	0	0
T1	1374	1228	0	0
T2	45274	45178	0	0
T3	401227	401211	0	0
T4	69571	69451	0	0
T5	1234	1183	0	0
T6	246682	234990	0	0
T7	72697	72631	0	0
T11	902	837	0	0
T16	2748	2605	0	0
T17	435474	435404	0	0