SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27321099 | 1 | T1 | 126 | T2 | 164 | T3 | 506 | |||
auto[1] | 5111617 | 1 | T1 | 12 | T4 | 153 | T5 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 32432500 | 1 | T1 | 138 | T2 | 164 | T3 | 506 | |||
values[1] | 16 | 1 | T206 | 1 | T245 | 2 | T249 | 1 | |||
values[2] | 5 | 1 | T290 | 2 | T287 | 2 | T355 | 1 | |||
values[3] | 112 | 1 | T96 | 11 | T206 | 8 | T245 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 32432515 | 1 | T1 | 138 | T2 | 164 | T3 | 506 | |||
values[1] | 19 | 1 | T96 | 2 | T206 | 1 | T245 | 3 | |||
values[2] | 3 | 1 | T245 | 1 | T290 | 1 | T299 | 1 | |||
values[3] | 100 | 1 | T96 | 6 | T206 | 5 | T245 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 32432396 | 1 | T1 | 138 | T2 | 164 | T3 | 506 | |||
auto[TlIntgErrCmd] | 119 | 1 | T96 | 9 | T206 | 10 | T245 | 5 | |||
auto[TlIntgErrData] | 104 | 1 | T96 | 3 | T206 | 7 | T245 | 2 | |||
auto[TlIntgErrBoth] | 97 | 1 | T96 | 8 | T206 | 3 | T245 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4057293 | 0 | T4 | 93 | T5 | 53 | T6 | 24 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4057086 | 1 | T4 | 93 | T5 | 53 | T6 | 24 | |||
values[1] | 22 | 1 | T206 | 1 | T245 | 1 | T291 | 2 | |||
values[2] | 5 | 1 | T249 | 1 | T287 | 1 | T299 | 1 | |||
values[3] | 104 | 1 | T96 | 7 | T206 | 9 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4057088 | 1 | T4 | 93 | T5 | 53 | T6 | 24 | |||
values[1] | 24 | 1 | T96 | 2 | T206 | 1 | T245 | 1 | |||
values[2] | 8 | 1 | T96 | 1 | T249 | 1 | T291 | 1 | |||
values[3] | 95 | 1 | T96 | 10 | T206 | 5 | T245 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4056987 | 1 | T4 | 93 | T5 | 53 | T6 | 24 | |||
auto[TlIntgErrCmd] | 101 | 1 | T96 | 1 | T206 | 10 | T245 | 5 | |||
auto[TlIntgErrData] | 99 | 1 | T96 | 11 | T206 | 2 | T245 | 8 | |||
auto[TlIntgErrBoth] | 106 | 1 | T96 | 8 | T206 | 5 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 90563 | 0 | T68 | 114 | T95 | 664 | T69 | 139 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 90354 | 1 | T68 | 114 | T95 | 664 | T69 | 139 | |||
values[1] | 21 | 1 | T96 | 3 | T249 | 3 | T291 | 2 | |||
values[2] | 5 | 1 | T291 | 1 | T287 | 1 | T299 | 1 | |||
values[3] | 114 | 1 | T96 | 7 | T206 | 10 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 90347 | 1 | T68 | 114 | T95 | 664 | T69 | 139 | |||
values[1] | 27 | 1 | T96 | 1 | T245 | 2 | T249 | 1 | |||
values[2] | 6 | 1 | T206 | 1 | T245 | 1 | T249 | 1 | |||
values[3] | 103 | 1 | T96 | 4 | T206 | 9 | T245 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 90243 | 1 | T68 | 114 | T95 | 664 | T69 | 139 | |||
auto[TlIntgErrCmd] | 104 | 1 | T96 | 9 | T206 | 5 | T245 | 7 | |||
auto[TlIntgErrData] | 111 | 1 | T96 | 5 | T206 | 8 | T245 | 9 | |||
auto[TlIntgErrBoth] | 105 | 1 | T96 | 6 | T206 | 7 | T245 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |