Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24708976	1		T1	79		T2	161		T3	504
full_word	7723740	1		T1	59		T2	3		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32432396	1		T1	138		T2	164		T3	506
auto[TlIntgErrCmd]	119	1		T96	9		T206	10		T245	5
auto[TlIntgErrData]	104	1		T96	3		T206	7		T245	2
auto[TlIntgErrBoth]	97	1		T96	8		T206	3		T245	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27959262	1		T1	87		T2	155		T3	497
auto[1]	4473454	1		T1	51		T2	9		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24020750	1		T1	73		T2	155		T3	496
auto[TlIntgErrNone]	partial	auto[1]	687937	1		T1	6		T2	6		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	3938372	1		T1	14		T3	1		T4	109
auto[TlIntgErrNone]	full_word	auto[1]	3785337	1		T1	45		T2	3		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T96	2		T206	3		T245	2
auto[TlIntgErrCmd]	partial	auto[1]	67	1		T96	7		T206	5		T245	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T206	1		T291	2		T298	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T206	1		T290	1		T287	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T96	3		T206	1		T291	5
auto[TlIntgErrData]	partial	auto[1]	52	1		T206	5		T245	2		T249	5
auto[TlIntgErrData]	full_word	auto[0]	8	1		T356	1		T357	2		T358	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T206	1		T249	1		T287	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T96	3		T206	2		T245	6
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T96	5		T206	1		T245	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T298	1		T359	1		T289	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T245	2		T249	1		T290	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20499	1		T95	687		T69	62		T96	20
full_word	4036794	1		T4	93		T5	53		T6	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4056987	1		T4	93		T5	53		T6	24
auto[TlIntgErrCmd]	101	1		T96	1		T206	10		T245	5
auto[TlIntgErrData]	99	1		T96	11		T206	2		T245	8
auto[TlIntgErrBoth]	106	1		T96	8		T206	5		T245	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4031446	1		T4	93		T5	53		T6	24
auto[1]	25847	1		T95	972		T69	83		T96	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1293	1		T95	35		T69	7		T97	4
auto[TlIntgErrNone]	partial	auto[1]	18930	1		T95	652		T69	55		T97	47
auto[TlIntgErrNone]	full_word	auto[0]	4030025	1		T4	93		T5	53		T6	24
auto[TlIntgErrNone]	full_word	auto[1]	6739	1		T95	320		T69	28		T97	17
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T245	1		T249	4		T291	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T96	1		T206	8		T245	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T245	1		T291	1		T290	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T206	2		T290	1		T299	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T96	6		T206	1		T245	3
auto[TlIntgErrData]	partial	auto[1]	47	1		T96	5		T245	4		T249	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T206	1		T298	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T245	1		T249	1		T357	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T96	1		T206	2		T245	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T96	7		T206	3		T245	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T290	1		T287	1		T360	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1		T245	3		T291	1		T287	1