Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1555130668	1552011244	0	0
CheckNGreaterZero_A	4172	4172	0	0
GntImpliesReady_A	1555130668	400452450	0	0
GntImpliesValid_A	1555130668	400452450	0	0
GrantKnown_A	1555130668	1552011244	0	0
IdxKnown_A	1555130668	1552011244	0	0
IndexIsCorrect_A	1555130668	400452450	0	0
NoReadyValidNoGrant_A	1555130668	168753799	0	0
Priority_A	1555130668	424493785	0	0
ReadyAndValidImplyGrant_A	1555130668	400452450	0	0
ReqAndReadyImplyGrant_A	1555130668	400452450	0	0
ReqImpliesValid_A	1555130668	424493785	0	0
ValidKnown_A	1555130668	1552011244	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	1552011244	0	0
T1	2644	2412	0	0
T2	13864	11192	0	0
T3	14616	11856	0	0
T4	552792	552544	0	0
T5	272128	271880	0	0
T6	25432	24828	0	0
T7	20576	20188	0	0
T17	4932	4728	0	0
T18	6276	5180	0	0
T19	9856	9552	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4172	4172	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	400452450	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132394	0	0
T6	25432	7788	0	0
T7	20576	3922	0	0
T8	0	1288	0	0
T9	0	20368	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	41066	0	0
T60	0	123676	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	400452450	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132394	0	0
T6	25432	7788	0	0
T7	20576	3922	0	0
T8	0	1288	0	0
T9	0	20368	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	41066	0	0
T60	0	123676	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	1552011244	0	0
T1	2644	2412	0	0
T2	13864	11192	0	0
T3	14616	11856	0	0
T4	552792	552544	0	0
T5	272128	271880	0	0
T6	25432	24828	0	0
T7	20576	20188	0	0
T17	4932	4728	0	0
T18	6276	5180	0	0
T19	9856	9552	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	1552011244	0	0
T1	2644	2412	0	0
T2	13864	11192	0	0
T3	14616	11856	0	0
T4	552792	552544	0	0
T5	272128	271880	0	0
T6	25432	24828	0	0
T7	20576	20188	0	0
T17	4932	4728	0	0
T18	6276	5180	0	0
T19	9856	9552	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	400452450	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132394	0	0
T6	25432	7788	0	0
T7	20576	3922	0	0
T8	0	1288	0	0
T9	0	20368	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	41066	0	0
T60	0	123676	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	168753799	0	0
T1	2644	294	0	0
T2	13864	1340	0	0
T3	14616	1372	0	0
T4	552792	848	0	0
T5	272128	364	0	0
T6	25432	1386	0	0
T7	20576	1316	0	0
T8	0	16	0	0
T9	0	57450	0	0
T17	4932	256	0	0
T18	6276	528	0	0
T19	9856	256	0	0
T23	0	16	0	0
T25	0	1274238	0	0
T45	0	18	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	424493785	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132430	0	0
T6	25432	7788	0	0
T7	20576	4134	0	0
T8	0	1288	0	0
T9	0	21302	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	280740	0	0
T60	0	123676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	400452450	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132394	0	0
T6	25432	7788	0	0
T7	20576	3922	0	0
T8	0	1288	0	0
T9	0	20368	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	41066	0	0
T60	0	123676	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	400452450	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132394	0	0
T6	25432	7788	0	0
T7	20576	3922	0	0
T8	0	1288	0	0
T9	0	20368	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	41066	0	0
T60	0	123676	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	424493785	0	0
T1	2644	88	0	0
T2	13864	360	0	0
T3	14616	368	0	0
T4	552792	266176	0	0
T5	272128	132430	0	0
T6	25432	7788	0	0
T7	20576	4134	0	0
T8	0	1288	0	0
T9	0	21302	0	0
T17	4932	584	0	0
T18	6276	132	0	0
T19	9856	64	0	0
T25	0	280740	0	0
T60	0	123676	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1555130668	1552011244	0	0
T1	2644	2412	0	0
T2	13864	11192	0	0
T3	14616	11856	0	0
T4	552792	552544	0	0
T5	272128	271880	0	0
T6	25432	24828	0	0
T7	20576	20188	0	0
T17	4932	4728	0	0
T18	6276	5180	0	0
T19	9856	9552	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388782667	388002811	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	388782667	104091191	0	0
GntImpliesValid_A	388782667	104091191	0	0
GrantKnown_A	388782667	388002811	0	0
IdxKnown_A	388782667	388002811	0	0
IndexIsCorrect_A	388782667	104091191	0	0
NoReadyValidNoGrant_A	388782667	43649749	0	0
Priority_A	388782667	110124541	0	0
ReadyAndValidImplyGrant_A	388782667	104091191	0	0
ReqAndReadyImplyGrant_A	388782667	104091191	0	0
ReqImpliesValid_A	388782667	110124541	0	0
ValidKnown_A	388782667	388002811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091191	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091191	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091191	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	43649749	0	0
T1	661	128	0	0
T2	3466	670	0	0
T3	3654	686	0	0
T4	138198	128	0	0
T5	68032	146	0	0
T6	6358	551	0	0
T7	5144	344	0	0
T17	1233	128	0	0
T18	1569	264	0	0
T19	2464	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	110124541	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	652	0	0
T6	6358	2268	0	0
T7	5144	1177	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091191	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091191	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	110124541	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	652	0	0
T6	6358	2268	0	0
T7	5144	1177	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388782667	388002811	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	388782667	104091107	0	0
GntImpliesValid_A	388782667	104091107	0	0
GrantKnown_A	388782667	388002811	0	0
IdxKnown_A	388782667	388002811	0	0
IndexIsCorrect_A	388782667	104091107	0	0
NoReadyValidNoGrant_A	388782667	43649751	0	0
Priority_A	388782667	110124455	0	0
ReadyAndValidImplyGrant_A	388782667	104091107	0	0
ReqAndReadyImplyGrant_A	388782667	104091107	0	0
ReqImpliesValid_A	388782667	110124455	0	0
ValidKnown_A	388782667	388002811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091107	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091107	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091107	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	43649751	0	0
T1	661	128	0	0
T2	3466	670	0	0
T3	3654	686	0	0
T4	138198	128	0	0
T5	68032	146	0	0
T6	6358	551	0	0
T7	5144	344	0	0
T17	1233	128	0	0
T18	1569	264	0	0
T19	2464	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	110124455	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	652	0	0
T6	6358	2268	0	0
T7	5144	1177	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091107	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	104091107	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	634	0	0
T6	6358	2268	0	0
T7	5144	1124	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	110124455	0	0
T1	661	32	0	0
T2	3466	180	0	0
T3	3654	184	0	0
T4	138198	32	0	0
T5	68032	652	0	0
T6	6358	2268	0	0
T7	5144	1177	0	0
T17	1233	32	0	0
T18	1569	66	0	0
T19	2464	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T1,T4,T17
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T9
1	1	Covered	T1,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388782667	388002811	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	388782667	96135093	0	0
GntImpliesValid_A	388782667	96135093	0	0
GrantKnown_A	388782667	388002811	0	0
IdxKnown_A	388782667	388002811	0	0
IndexIsCorrect_A	388782667	96135093	0	0
NoReadyValidNoGrant_A	388782667	40727175	0	0
Priority_A	388782667	102122386	0	0
ReadyAndValidImplyGrant_A	388782667	96135093	0	0
ReqAndReadyImplyGrant_A	388782667	96135093	0	0
ReqImpliesValid_A	388782667	102122386	0	0
ValidKnown_A	388782667	388002811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135093	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135093	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135093	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	40727175	0	0
T1	661	19	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	296	0	0
T5	68032	36	0	0
T6	6358	142	0	0
T7	5144	314	0	0
T8	0	8	0	0
T9	0	28725	0	0
T17	1233	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T23	0	8	0	0
T25	0	637119	0	0
T45	0	9	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	102122386	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	890	0	0
T8	0	644	0	0
T9	0	10651	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	140370	0	0
T60	0	61838	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135093	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135093	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	102122386	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	890	0	0
T8	0	644	0	0
T9	0	10651	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	140370	0	0
T60	0	61838	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T17
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T1,T4,T17
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T9
1	1	Covered	T1,T4,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	388782667	388002811	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	388782667	96135059	0	0
GntImpliesValid_A	388782667	96135059	0	0
GrantKnown_A	388782667	388002811	0	0
IdxKnown_A	388782667	388002811	0	0
IndexIsCorrect_A	388782667	96135059	0	0
NoReadyValidNoGrant_A	388782667	40727124	0	0
Priority_A	388782667	102122403	0	0
ReadyAndValidImplyGrant_A	388782667	96135059	0	0
ReqAndReadyImplyGrant_A	388782667	96135059	0	0
ReqImpliesValid_A	388782667	102122403	0	0
ValidKnown_A	388782667	388002811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135059	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135059	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135059	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	40727124	0	0
T1	661	19	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	296	0	0
T5	68032	36	0	0
T6	6358	142	0	0
T7	5144	314	0	0
T8	0	8	0	0
T9	0	28725	0	0
T17	1233	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T23	0	8	0	0
T25	0	637119	0	0
T45	0	9	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	102122403	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	890	0	0
T8	0	644	0	0
T9	0	10651	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	140370	0	0
T60	0	61838	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135059	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	96135059	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	837	0	0
T8	0	644	0	0
T9	0	10184	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	20533	0	0
T60	0	61838	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	102122403	0	0
T1	661	12	0	0
T2	3466	0	0	0
T3	3654	0	0	0
T4	138198	133056	0	0
T5	68032	65563	0	0
T6	6358	1626	0	0
T7	5144	890	0	0
T8	0	644	0	0
T9	0	10651	0	0
T17	1233	260	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	0	140370	0	0
T60	0	61838	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0