Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	100.00	85.85		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.28		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T191
1	0	Covered	T10,T11,T191

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T10,T11,T191

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T191
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T5,T7,T45

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13
1	Covered	T5,T7,T45

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T60,T8
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13
1	Covered	T4,T5,T7

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T60,T10,T23

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T5,T7

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T23
1	1	Covered	T60,T10,T23

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T23
1	1	Covered	T60,T10,T23

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T7
1	1	0	Covered	T4,T5,T7
1	1	1	Covered	T4,T5,T7

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T60,T10,T23
StCalcMask	237	Covered	T60,T10,T23
StCalcPlainEcc	215	Covered	T4,T5,T7
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T7
StPostPack	218	Covered	T4,T5,T7
StPrePack	195	Covered	T5,T7,T45
StReqFlash	237	Covered	T4,T5,T7
StScrambleData	244	Covered	T60,T10,T23
StWaitFlash	270	Covered	T4,T5,T7

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T60,T10,T23
StCalcMask->StScrambleData	244	Covered	T60,T10,T23
StCalcPlainEcc->StCalcMask	237	Covered	T60,T10,T23
StCalcPlainEcc->StReqFlash	237	Covered	T4,T5,T7
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T4,T5,T7
StIdle->StPrePack	195	Covered	T5,T7,T45
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T7
StPackData->StPostPack	218	Covered	T4,T5,T7
StPostPack->StCalcPlainEcc	231	Covered	T4,T5,T7
StPrePack->StPackData	205	Covered	T5,T7,T45
StReqFlash->StIdle	273	Covered	T4,T5,T7
StReqFlash->StWaitFlash	270	Covered	T4,T5,T7
StScrambleData->StCalcEcc	252	Covered	T60,T10,T23
StWaitFlash->StIdle	280	Covered	T4,T5,T7

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T45
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T45
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T7
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T7
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T60,T10,T23
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T7
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T60,T10,T23
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T60,T10,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T60,T10,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T60,T10,T23
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T60,T10,T23
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T7
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T7
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T7
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T7
0	0	1	-	-	Covered	T60,T10,T23
0	0	0	1	-	Covered	T60,T10,T23
0	0	0	0	1	Covered	T4,T5,T7
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	777565334	2447719	0	0
PostPackRule_A	777565334	1920	0	0
PrePackRule_A	777565334	1338	0	0
WidthCheck_A	2086	2086	0	0
u_state_regs_A	777565334	776005622	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777565334	2447719	0	0
T4	138198	4	0	0
T5	136064	1	0	0
T6	12716	0	0	0
T7	10288	3	0	0
T8	0	3	0	0
T9	59461	0	0	0
T17	1233	0	0	0
T18	3138	0	0	0
T19	4928	0	0	0
T23	0	1	0	0
T27	0	648	0	0
T32	0	32	0	0
T36	0	72	0	0
T45	0	2	0	0
T54	3708	0	0	0
T55	2772	0	0	0
T56	2750	0	0	0
T59	0	65920	0	0
T60	197041	1214	0	0
T66	0	32768	0	0
T85	0	170	0	0
T122	0	542	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777565334	1920	0	0
T4	138198	2	0	0
T5	136064	1	0	0
T6	12716	0	0	0
T7	10288	3	0	0
T8	0	2	0	0
T9	59461	0	0	0
T17	1233	0	0	0
T18	3138	0	0	0
T19	4928	0	0	0
T36	0	48	0	0
T42	0	5	0	0
T45	0	1	0	0
T54	3708	0	0	0
T55	2772	0	0	0
T56	2750	0	0	0
T60	197041	0	0	0
T71	0	8	0	0
T72	0	38	0	0
T101	0	5	0	0
T132	0	2	0	0
T227	0	5	0	0
T253	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777565334	1338	0	0
T5	68032	1	0	0
T6	6358	0	0	0
T7	10288	3	0	0
T8	2575	0	0	0
T9	118922	0	0	0
T10	4074	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T25	123140	0	0	0
T36	0	22	0	0
T42	0	4	0	0
T45	0	2	0	0
T54	3708	0	0	0
T55	2772	0	0	0
T56	2750	0	0	0
T60	394082	0	0	0
T61	3613	0	0	0
T71	0	9	0	0
T72	0	26	0	0
T76	0	12	0	0
T101	0	2	0	0
T152	0	1	0	0
T227	0	4	0	0
T253	0	1	0	0
T274	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2086	2086	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777565334	776005622	0	0
T1	1322	1206	0	0
T2	6932	5596	0	0
T3	7308	5928	0	0
T4	276396	276272	0	0
T5	136064	135940	0	0
T6	12716	12414	0	0
T7	10288	10094	0	0
T17	2466	2364	0	0
T18	3138	2590	0	0
T19	4928	4776	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T60

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T60

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T20
1	0	Covered	T10,T11,T20

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T60
1	1	Covered	T10,T11,T20

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T20
1	0	Covered	T1,T4,T17

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T60

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T7,T60
1	Covered	T4,T7,T8

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T60
1	0	Covered	T4,T7,T60
1	1	Covered	T4,T7,T60

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T60

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T60
1	1	Covered	T7,T45,T36

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13
1	Covered	T7,T45,T36

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T60
1	0	Covered	T4,T7,T60
1	1	Covered	T4,T7,T60

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T7,T60
1	Covered	T4,T7,T60

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T60,T36
1	0	Covered	T4,T7,T60
1	1	Covered	T4,T7,T8

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13
1	Covered	T4,T7,T8

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T7,T60
1	Covered	T59,T122,T66

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T60,T8
1	Covered	T4,T7,T60

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T7,T60
1	Covered	T4,T7,T60

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T60
1	1	Covered	T4,T7,T60

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T23
1	0	Covered	T59,T122,T66
1	1	Covered	T59,T122,T66

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T23
1	0	Covered	T59,T122,T66
1	1	Covered	T59,T122,T66

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T7,T60
1	1	0	Covered	T4,T7,T60
1	1	1	Covered	T4,T7,T60

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T60

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T17

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T122,T131,T67
StCalcMask	237	Covered	T122,T131,T67
StCalcPlainEcc	215	Covered	T4,T7,T60
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T7,T60
StPostPack	218	Covered	T4,T7,T8
StPrePack	195	Covered	T7,T45,T36
StReqFlash	237	Covered	T4,T7,T60
StScrambleData	244	Covered	T122,T131,T67
StWaitFlash	270	Covered	T4,T7,T60

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T122,T131,T67
StCalcMask->StScrambleData	244	Covered	T122,T131,T67
StCalcPlainEcc->StCalcMask	237	Covered	T122,T131,T67
StCalcPlainEcc->StReqFlash	237	Covered	T4,T7,T60
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T4,T7,T60
StIdle->StPrePack	195	Covered	T7,T45,T36
StPackData->StCalcPlainEcc	215	Covered	T4,T7,T60
StPackData->StPostPack	218	Covered	T4,T7,T8
StPostPack->StCalcPlainEcc	231	Covered	T4,T7,T8
StPrePack->StPackData	205	Covered	T7,T45,T36
StReqFlash->StIdle	273	Covered	T4,T7,T60
StReqFlash->StWaitFlash	270	Covered	T4,T7,T60
StScrambleData->StCalcEcc	252	Covered	T122,T131,T67
StWaitFlash->StIdle	280	Covered	T4,T7,T60

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T60
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T60
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T60
0	1	Covered	T1,T4,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T7,T60
0	0	1	Covered	T4,T7,T60
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T45,T36
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T60
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T45,T36
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T60
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T7,T60
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T7,T60
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T7,T8
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T59,T122,T66
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T7,T60
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T59,T122,T66
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T59,T122,T66
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T59,T122,T66
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T59,T122,T66
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T59,T122,T66
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T7,T60
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T60,T8
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T7,T60
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T7,T60
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T7,T60
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T7,T60
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T7,T60
0	0	1	-	-	Covered	T59,T122,T66
0	0	0	1	-	Covered	T59,T122,T66
0	0	0	0	1	Covered	T4,T7,T60
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T7,T60
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	388782667	1209689	0	0
PostPackRule_A	388782667	962	0	0
PrePackRule_A	388782667	679	0	0
WidthCheck_A	1043	1043	0	0
u_state_regs_A	388782667	388002811	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	1209689	0	0
T4	138198	4	0	0
T5	68032	0	0	0
T6	6358	0	0	0
T7	5144	1	0	0
T8	0	2	0	0
T17	1233	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T27	0	648	0	0
T36	0	34	0	0
T45	0	1	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T59	0	32768	0	0
T60	0	500	0	0
T66	0	32768	0	0
T122	0	542	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	962	0	0
T4	138198	2	0	0
T5	68032	0	0	0
T6	6358	0	0	0
T7	5144	1	0	0
T8	0	2	0	0
T17	1233	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T36	0	24	0	0
T42	0	3	0	0
T45	0	1	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T71	0	5	0	0
T72	0	15	0	0
T132	0	1	0	0
T227	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	679	0	0
T7	5144	1	0	0
T8	2575	0	0	0
T9	59461	0	0	0
T10	4074	0	0	0
T25	123140	0	0	0
T36	0	12	0	0
T42	0	2	0	0
T45	0	1	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T60	197041	0	0	0
T61	3613	0	0	0
T71	0	5	0	0
T72	0	9	0	0
T76	0	12	0	0
T152	0	1	0	0
T227	0	3	0	0
T274	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T60

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T60

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T191
1	0	Covered	T10,T11,T191

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T60
1	1	Covered	T10,T11,T191

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T191
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T60

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T5,T7,T60
1	Covered	T5,T7,T36

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T60
1	0	Covered	T5,T7,T60
1	1	Covered	T5,T7,T60

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T60

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T60
1	1	Covered	T5,T7,T45

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T13
1	Covered	T5,T7,T45

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T60
1	0	Covered	T5,T7,T60
1	1	Covered	T5,T7,T60

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T5,T7,T60
1	Covered	T5,T7,T60

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T60,T8,T23
1	0	Covered	T5,T7,T60
1	1	Covered	T5,T7,T36

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T13
1	Covered	T5,T7,T36

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T5,T7,T60
1	Covered	T60,T10,T23

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T5,T7,T60
1	Covered	T5,T7,T60

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T5,T7,T60
1	Covered	T5,T7,T60

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T60
1	1	Covered	T5,T7,T60

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T23
1	1	Covered	T60,T10,T23

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T60,T10,T23
1	1	Covered	T60,T10,T23

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T7,T60
1	1	0	Covered	T5,T7,T60
1	1	1	Covered	T5,T7,T60

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T60

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T60,T10,T23
StCalcMask	237	Covered	T60,T10,T23
StCalcPlainEcc	215	Covered	T5,T7,T60
StDisabled	193	Covered	T1,T2,T3
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T5,T7,T60
StPostPack	218	Covered	T5,T7,T36
StPrePack	195	Covered	T5,T7,T45
StReqFlash	237	Covered	T5,T7,T60
StScrambleData	244	Covered	T60,T10,T23
StWaitFlash	270	Covered	T5,T7,T60

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T60,T10,T23
StCalcMask->StScrambleData	244	Covered	T60,T10,T23
StCalcPlainEcc->StCalcMask	237	Covered	T60,T10,T23
StCalcPlainEcc->StReqFlash	237	Covered	T5,T7,T60
StIdle->StDisabled	193	Covered	T1,T2,T3
StIdle->StPackData	197	Covered	T5,T7,T60
StIdle->StPrePack	195	Covered	T5,T7,T45
StPackData->StCalcPlainEcc	215	Covered	T5,T7,T60
StPackData->StPostPack	218	Covered	T5,T7,T36
StPostPack->StCalcPlainEcc	231	Covered	T5,T7,T36
StPrePack->StPackData	205	Covered	T5,T7,T45
StReqFlash->StIdle	273	Covered	T5,T7,T60
StReqFlash->StWaitFlash	270	Covered	T5,T7,T60
StScrambleData->StCalcEcc	252	Covered	T60,T10,T23
StWaitFlash->StIdle	280	Covered	T5,T7,T60

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T60
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T60
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T60
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T7,T60
0	0	1	Covered	T5,T7,T60
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T45
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T60
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T45
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T60
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T7,T36
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T5,T7,T60
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T5,T7,T60
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T7,T36
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T60,T10,T23
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T7,T60
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T60,T10,T23
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T60,T10,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T60,T10,T23
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T60,T10,T23
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T60,T10,T23
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T5,T7,T60
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T5,T7,T60
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T5,T7,T60
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T5,T7,T60
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T7,T60
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T5,T7,T60
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T5,T7,T60
0	0	1	-	-	Covered	T60,T10,T23
0	0	0	1	-	Covered	T60,T10,T23
0	0	0	0	1	Covered	T5,T7,T60
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T5,T7,T60
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	388782667	1238030	0	0
PostPackRule_A	388782667	958	0	0
PrePackRule_A	388782667	659	0	0
WidthCheck_A	1043	1043	0	0
u_state_regs_A	388782667	388002811	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	1238030	0	0
T5	68032	1	0	0
T6	6358	0	0	0
T7	5144	2	0	0
T8	0	1	0	0
T9	59461	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T23	0	1	0	0
T32	0	32	0	0
T36	0	38	0	0
T45	0	1	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T59	0	33152	0	0
T60	197041	714	0	0
T85	0	170	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	958	0	0
T5	68032	1	0	0
T6	6358	0	0	0
T7	5144	2	0	0
T9	59461	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T36	0	24	0	0
T42	0	2	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T60	197041	0	0	0
T71	0	3	0	0
T72	0	23	0	0
T101	0	5	0	0
T132	0	1	0	0
T227	0	3	0	0
T253	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	659	0	0
T5	68032	1	0	0
T6	6358	0	0	0
T7	5144	2	0	0
T9	59461	0	0	0
T18	1569	0	0	0
T19	2464	0	0	0
T36	0	10	0	0
T42	0	2	0	0
T45	0	1	0	0
T54	1854	0	0	0
T55	1386	0	0	0
T56	1375	0	0	0
T60	197041	0	0	0
T71	0	4	0	0
T72	0	17	0	0
T101	0	2	0	0
T227	0	1	0	0
T253	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388782667	388002811	0	0
T1	661	603	0	0
T2	3466	2798	0	0
T3	3654	2964	0	0
T4	138198	138136	0	0
T5	68032	67970	0	0
T6	6358	6207	0	0
T7	5144	5047	0	0
T17	1233	1182	0	0
T18	1569	1295	0	0
T19	2464	2388	0	0