Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_mp
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.46 100.00 97.84 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_mp 99.46 100.00 97.84 100.00 100.00



Module Instance : tb.dut.u_flash_mp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.46 100.00 97.84 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.54 100.00 98.16 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.53 97.12 92.80 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_hw_sel 100.00 100.00 100.00
u_sw_sel 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_mp
Line No.TotalCoveredPercent
TOTAL7676100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
ALWAYS18500
ALWAYS18522100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21511100.00
ALWAYS2401010100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN27011100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN30111100.00
ALWAYS30766100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN37511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1
79 1 1
80 1 1
100 1 1
104 1 1
105 1 1
121 1 1
129 1 1
132 1 1
149 9 9
174 1 1
179 1 1
180 1 1
185 1 1
186 1 1
191 1 1
195 1 1
198 1 1
201 1 1
204 1 1
206 1 1
209 1 1
212 1 1
215 1 1
240 1 1
241 1 1
242 1 1
243 1 1
245 1 1
248 1 1
249 1 1
MISSING_ELSE
MISSING_ELSE
254 1 1
255 1 1
257 1 1
262 1 1
263 1 1
266 1 1
269 1 1
270 1 1
271 1 1
273 1 1
274 1 1
277 1 1
278 1 1
281 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
295 1 1
296 1 1
301 1 1
307 1 1
308 1 1
309 1 1
310 1 1
311 1 1
312 1 1
MISSING_ELSE
316 1 1
317 1 1
318 1 1
319 1 1
324 1 1
325 1 1
326 1 1
375 1 1


Cond Coverage for Module : flash_mp
TotalCoveredPercent
Conditions13913697.84
Logical13913697.84
Non-Logical00
Event00

 LINE       100
 EXPRESSION (if_sel_i == HwSel)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       104
 EXPRESSION (req_part_i == FlashPartData)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       105
 EXPRESSION (req_part_i == FlashPartInfo)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
             --1--   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT6,T60,T9
10CoveredT1,T2,T3
11CoveredT60,T37,T38

 LINE       132
 SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
                 -----------1----------   ------2-----   -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100CoveredT6,T60,T9

 LINE       154
 EXPRESSION (req_i & ((~hw_sel)))
             --1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T4,T17

 LINE       164
 EXPRESSION (req_i & hw_sel)
             --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T17
11CoveredT1,T2,T3

 LINE       174
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       186
 EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
             ---------1---------   --------2-------   -----3-----
-1--2--3-StatusTests
011CoveredT4,T5,T7
101CoveredT1,T2,T3
110CoveredT59,T66,T101
111CoveredT4,T5,T7

 LINE       186
 SUB-EXPRESSION (bank_addr == i[0])
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       204
 EXPRESSION (bk_erase_i & ((|bk_erase_en)))
             -----1----   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT71,T237,T238
11CoveredT4,T5,T36

 LINE       215
 EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T4,T17
111CoveredT60,T36,T122

 LINE       215
 SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT4,T5,T36
0010CoveredT4,T17,T5
0100CoveredT4,T5,T7
1000CoveredT1,T4,T6

 LINE       242
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT1,T4,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       245
 EXPRESSION 
 Number  Term
      1  (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) && 
      2  (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) && 
      3  (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
                -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT13
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
                --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       273
 EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
             ------1------   -----2----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T36
101CoveredT36,T217,T71
110CoveredT71,T237,T238
111CoveredT71,T144,T112

 LINE       281
 EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T4,T17
110CoveredT1,T2,T3
111CoveredT6,T60,T9

 LINE       281
 SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT71,T144,T112
0010CoveredT2,T3,T6
0100CoveredT60,T10,T23
1000CoveredT1,T2,T3

 LINE       289
 EXPRESSION (req_i & (data_rd_en | info_rd_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT6,T9,T23
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       289
 SUB-EXPRESSION (data_rd_en | info_rd_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T4,T6

 LINE       290
 EXPRESSION (req_i & (data_prog_en | info_prog_en))
             --1--   --------------2--------------
-1--2-StatusTests
01CoveredT60,T10,T23
10CoveredT1,T2,T3
11CoveredT4,T5,T7

 LINE       290
 SUB-EXPRESSION (data_prog_en | info_prog_en)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT60,T10,T23
10CoveredT4,T5,T7

 LINE       291
 EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT6,T30,T31
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       291
 SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T6
10CoveredT4,T17,T5

 LINE       292
 EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT4,T5,T36
10CoveredT1,T2,T3
11CoveredT4,T5,T36

 LINE       292
 SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T36

 LINE       293
 EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT6,T60,T9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (data_scramble_en | info_scramble_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T60,T9

 LINE       294
 EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
             --1--   -------------2-------------
-1--2-StatusTests
01CoveredT6,T60,T9
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       294
 SUB-EXPRESSION (data_ecc_en | info_ecc_en)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T6,T60

 LINE       295
 EXPRESSION (req_i & (data_he_en | info_he_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT6,T60,T9
10CoveredT1,T4,T17
11CoveredT1,T2,T3

 LINE       295
 SUB-EXPRESSION (data_he_en | info_he_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT5,T6,T7

 LINE       296
 EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
             --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT4,T5,T36
0010CoveredT2,T3,T4
0100CoveredT4,T5,T7
1000CoveredT1,T2,T3

 LINE       316
 EXPRESSION (rd_done_i | txn_err)
             ----1----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T60
10CoveredT1,T2,T3

 LINE       317
 EXPRESSION (prog_done_i | txn_err)
             -----1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T60
10CoveredT4,T5,T7

 LINE       318
 EXPRESSION (erase_done_i | txn_err)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T60
10CoveredT4,T17,T5

 LINE       324
 EXPRESSION (pg_erase_o | bk_erase_o)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T36
10CoveredT2,T3,T4

 LINE       325
 EXPRESSION (erase_valid & erase_suspend_i)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT144,T161,T162
10CoveredT2,T3,T4
11CoveredT76,T144,T161

 LINE       326
 EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
             ------------------1-----------------   ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT76,T144,T161
10CoveredT144,T161,T162

 LINE       326
 SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
                 -------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT76,T144,T161
11CoveredT144,T161,T162

 LINE       326
 SUB-EXPRESSION (erase_suspend_o & erase_done_o)
                 -------1-------   ------2-----
-1--2-StatusTests
01CoveredT2,T4,T17
10CoveredT76,T144,T161
11CoveredT76,T144,T161

Branch Coverage for Module : flash_mp
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 129 2 2 100.00
TERNARY 174 2 2 100.00
TERNARY 263 2 2 100.00
IF 242 2 2 100.00
IF 307 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 129 (data_part_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 174 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 263 (hw_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 242 if ((hw_sel && req_i))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_ni)) -2-: 309 if (txn_err) -3-: 311 if (no_allowed_txn)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T6,T60
0 0 1 Covered T2,T6,T60
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_mp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BankEraseData_A 388782743 8718240 0 0
BankEraseInfo_A 388782743 11010799 0 0
DataReqToInfo_A 388782743 234494241 0 0
InReqOutReq_A 388782743 261623951 0 0
InfoReqToData_A 388782743 27129710 0 0
NoReqWhenErr_A 383887925 130906 0 0
bkEraseEnOnehot_A 388782743 19729039 0 0
hwInfoRuleOnehot_A 388782743 153982848 0 0
invalidReqOnehot_A 388782743 261493000 0 0
requestTypesOnehot_A 388782743 261493000 0 0


BankEraseData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 8718240 0 0
T4 138198 131080 0 0
T5 68032 65540 0 0
T6 6358 0 0 0
T7 5144 0 0 0
T17 1233 0 0 0
T18 1569 0 0 0
T19 2464 0 0 0
T36 0 393240 0 0
T54 1854 0 0 0
T55 1386 0 0 0
T56 1375 0 0 0
T72 0 524320 0 0
T101 0 65540 0 0
T136 0 65540 0 0
T137 0 65540 0 0
T142 0 196620 0 0
T227 0 65540 0 0
T239 0 131080 0 0

BankEraseInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 11010799 0 0
T11 3926 0 0 0
T65 45412 0 0 0
T71 824080 458780 0 0
T72 597873 0 0 0
T102 1163 0 0 0
T112 0 983100 0 0
T125 0 104864 0 0
T127 0 589860 0 0
T128 0 983100 0 0
T129 0 124526 0 0
T144 0 65619 0 0
T146 0 65540 0 0
T148 0 655400 0 0
T164 3359 0 0 0
T180 3613 0 0 0
T205 162376 0 0 0
T209 1585 0 0 0
T240 0 262160 0 0
T241 2079 0 0 0

DataReqToInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 234494241 0 0
T1 661 31 0 0
T2 3466 0 0 0
T3 3654 0 0 0
T4 138198 133117 0 0
T5 68032 66130 0 0
T6 6358 3352 0 0
T7 5144 2315 0 0
T8 0 713 0 0
T9 0 22515 0 0
T17 1233 260 0 0
T18 1569 0 0 0
T19 2464 0 0 0
T25 0 119415 0 0
T60 0 147843 0 0

InReqOutReq_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 261623951 0 0
T1 661 191 0 0
T2 3466 849 0 0
T3 3654 870 0 0
T4 138198 133277 0 0
T5 68032 66290 0 0
T6 6358 4485 0 0
T7 5144 2475 0 0
T17 1233 420 0 0
T18 1569 330 0 0
T19 2464 160 0 0

InfoReqToData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 27129710 0 0
T1 661 160 0 0
T2 3466 849 0 0
T3 3654 870 0 0
T4 138198 160 0 0
T5 68032 160 0 0
T6 6358 1133 0 0
T7 5144 160 0 0
T17 1233 160 0 0
T18 1569 330 0 0
T19 2464 160 0 0

NoReqWhenErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 383887925 130906 0 0
T6 6358 8 0 0
T7 5144 0 0 0
T9 59461 200 0 0
T19 2464 0 0 0
T25 123140 0 0 0
T30 0 740 0 0
T31 0 740 0 0
T32 0 488 0 0
T36 0 50 0 0
T37 0 50 0 0
T38 0 198 0 0
T54 1854 0 0 0
T55 1386 0 0 0
T56 1375 0 0 0
T60 197041 868 0 0
T61 2589 0 0 0
T242 0 736 0 0

bkEraseEnOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 19729039 0 0
T4 138198 131080 0 0
T5 68032 65540 0 0
T6 6358 0 0 0
T7 5144 0 0 0
T17 1233 0 0 0
T18 1569 0 0 0
T19 2464 0 0 0
T36 0 393240 0 0
T54 1854 0 0 0
T55 1386 0 0 0
T56 1375 0 0 0
T71 0 458780 0 0
T72 0 524320 0 0
T101 0 65540 0 0
T136 0 65540 0 0
T137 0 65540 0 0
T142 0 196620 0 0
T227 0 65540 0 0

hwInfoRuleOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 153982848 0 0
T1 661 160 0 0
T2 3466 849 0 0
T3 3654 870 0 0
T4 138198 160 0 0
T5 68032 160 0 0
T6 6358 320 0 0
T7 5144 160 0 0
T17 1233 160 0 0
T18 1569 330 0 0
T19 2464 160 0 0

invalidReqOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 261493000 0 0
T1 661 191 0 0
T2 3466 849 0 0
T3 3654 870 0 0
T4 138198 133277 0 0
T5 68032 66290 0 0
T6 6358 4477 0 0
T7 5144 2475 0 0
T17 1233 420 0 0
T18 1569 330 0 0
T19 2464 160 0 0

requestTypesOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 388782743 261493000 0 0
T1 661 191 0 0
T2 3466 849 0 0
T3 3654 870 0 0
T4 138198 133277 0 0
T5 68032 66290 0 0
T6 6358 4477 0 0
T7 5144 2475 0 0
T17 1233 420 0 0
T18 1569 330 0 0
T19 2464 160 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%