Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25729881	1		T1	322		T2	1309		T3	58
full_word	7762177	1		T1	106		T2	1871		T20	41

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33491768	1		T1	428		T2	3180		T3	58
auto[TlIntgErrCmd]	89	1		T112	3		T193	3		T246	2
auto[TlIntgErrData]	96	1		T112	3		T193	5		T246	6
auto[TlIntgErrBoth]	105	1		T112	4		T193	2		T246	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29011678	1		T1	350		T2	2680		T3	57
auto[1]	4480380	1		T1	78		T2	500		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24995164	1		T1	303		T2	1094		T3	57
auto[TlIntgErrNone]	partial	auto[1]	734450	1		T1	19		T2	215		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	4016371	1		T1	47		T2	1586		T4	5430
auto[TlIntgErrNone]	full_word	auto[1]	3745783	1		T1	59		T2	285		T20	41
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T112	2		T193	2		T285	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1		T112	1		T193	1		T246	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T362	1		T364	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T246	1		T256	1		T365	2
auto[TlIntgErrData]	partial	auto[0]	51	1		T112	3		T193	1		T246	3
auto[TlIntgErrData]	partial	auto[1]	38	1		T193	3		T246	3		T285	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T193	1		T256	1		T357	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T366	1		T367	1		T368	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1		T112	1		T193	1		T246	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T112	3		T193	1		T285	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T365	1		T367	1		T358	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T285	1		T256	1		T365	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22719	1		T71	293		T111	1103		T112	8
full_word	3818596	1		T1	5		T2	15566		T7	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3841046	1		T1	5		T2	15566		T7	10
auto[TlIntgErrCmd]	66	1		T112	2		T193	3		T246	2
auto[TlIntgErrData]	113	1		T112	6		T193	3		T246	4
auto[TlIntgErrBoth]	90	1		T112	1		T193	4		T246	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3812672	1		T1	5		T2	15566		T7	10
auto[1]	28643	1		T71	381		T111	1415		T112	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1499	1		T71	17		T111	93		T190	17
auto[TlIntgErrNone]	partial	auto[1]	20974	1		T71	276		T111	1010		T190	470
auto[TlIntgErrNone]	full_word	auto[0]	3811065	1		T1	5		T2	15566		T7	10
auto[TlIntgErrNone]	full_word	auto[1]	7508	1		T71	105		T111	405		T190	129
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T193	1		T246	1		T360	2
auto[TlIntgErrCmd]	partial	auto[1]	35	1		T112	1		T193	2		T246	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T368	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T112	1		T360	1		T359	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T112	3		T193	3		T246	3
auto[TlIntgErrData]	partial	auto[1]	57	1		T112	3		T246	1		T285	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T357	1		T364	1		T367	2
auto[TlIntgErrData]	full_word	auto[1]	5	1		T357	1		T367	1		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T193	1		T246	1		T285	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T112	1		T193	3		T246	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T256	1		T363	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T246	1		T285	1		T256	1