SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 80 | 1 | T33 | 3 | T227 | 4 | T373 | 2 | |||
others[1] | 82 | 1 | T227 | 1 | T224 | 1 | T373 | 2 | |||
others[2] | 74 | 1 | T33 | 2 | T171 | 2 | T224 | 3 | |||
others[3] | 145 | 1 | T33 | 1 | T227 | 2 | T171 | 5 | |||
false | 29075 | 1 | T2 | 2 | T3 | 1 | T21 | 1 | |||
true | 24017 | 1 | T1 | 3 | T2 | 1 | T20 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T374 | 1 | T375 | 1 | T376 | 1 | |||
others[1] | 4 | 1 | T104 | 1 | T101 | 1 | T377 | 1 | |||
others[2] | 8 | 1 | T102 | 1 | T186 | 1 | T378 | 1 | |||
others[3] | 1 | 1 | T379 | 1 | - | - | - | - | |||
false | 12587 | 1 | T1 | 2 | T2 | 2 | T3 | 1 | |||
true | 6 | 1 | T100 | 1 | T103 | 1 | T380 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2552 | 1 | T4 | 58 | T6 | 24 | T61 | 69 | |||
others[1] | 2578 | 1 | T4 | 78 | T6 | 24 | T61 | 51 | |||
others[2] | 2539 | 1 | T4 | 60 | T6 | 31 | T61 | 53 | |||
others[3] | 4226 | 1 | T4 | 124 | T6 | 41 | T61 | 93 | |||
false | 7307 | 1 | T1 | 2 | T3 | 1 | T21 | 1 | |||
true | 1483 | 1 | T1 | 1 | T2 | 3 | T20 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2560 | 1 | T4 | 69 | T6 | 23 | T61 | 50 | |||
others[1] | 2516 | 1 | T4 | 63 | T6 | 22 | T61 | 65 | |||
others[2] | 2566 | 1 | T4 | 68 | T6 | 30 | T61 | 67 | |||
others[3] | 4346 | 1 | T4 | 111 | T6 | 44 | T61 | 94 | |||
false | 7276 | 1 | T1 | 2 | T3 | 1 | T21 | 1 | |||
true | 1478 | 1 | T1 | 1 | T2 | 3 | T20 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2479 | 1 | T4 | 60 | T6 | 23 | T61 | 45 | |||
others[1] | 2553 | 1 | T4 | 64 | T6 | 25 | T61 | 47 | |||
others[2] | 2579 | 1 | T4 | 66 | T6 | 23 | T61 | 54 | |||
others[3] | 4158 | 1 | T4 | 117 | T6 | 63 | T61 | 120 | |||
false | 7730 | 1 | T1 | 2 | T2 | 2 | T3 | 1 | |||
true | 41 | 1 | T3 | 1 | T21 | 1 | T51 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 74 | 1 | T33 | 3 | T227 | 3 | T224 | 3 | |||
others[1] | 75 | 1 | T33 | 1 | T227 | 1 | T171 | 5 | |||
others[2] | 100 | 1 | T33 | 1 | T227 | 3 | T171 | 2 | |||
others[3] | 140 | 1 | T33 | 5 | T227 | 2 | T171 | 1 | |||
false | 29125 | 1 | T1 | 2 | T2 | 2 | T3 | 1 | |||
true | 24117 | 1 | T1 | 1 | T2 | 1 | T20 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8271 | 1 | T4 | 198 | T6 | 92 | T61 | 190 | |||
others[1] | 8219 | 1 | T4 | 201 | T6 | 93 | T61 | 199 | |||
others[2] | 8350 | 1 | T4 | 230 | T6 | 87 | T61 | 188 | |||
others[3] | 13746 | 1 | T4 | 378 | T6 | 160 | T61 | 324 | |||
false | 4215 | 1 | T4 | 113 | T6 | 41 | T61 | 108 | |||
true | 20098 | 1 | T1 | 2 | T2 | 2 | T3 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |