Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1575080644	1571649624	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1575080644	407541878	0	0
GntImpliesValid_A	1575080644	407541878	0	0
GrantKnown_A	1575080644	1571649624	0	0
IdxKnown_A	1575080644	1571649624	0	0
IndexIsCorrect_A	1575080644	407541878	0	0
NoReadyValidNoGrant_A	1575080644	178143815	0	0
Priority_A	1575080644	431862007	0	0
ReadyAndValidImplyGrant_A	1575080644	407541878	0	0
ReqAndReadyImplyGrant_A	1575080644	407541878	0	0
ReqImpliesValid_A	1575080644	431862007	0	0
ValidKnown_A	1575080644	1571649624	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	1571649624	0	0
T1	5532	4960	0	0
T2	2237756	2237180	0	0
T3	5448	5148	0	0
T4	1488624	1427740	0	0
T5	603972	603940	0	0
T7	6252	5496	0	0
T20	3576312	3575632	0	0
T21	6664	6436	0	0
T22	4016	3652	0	0
T23	567076	567036	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T7	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	407541878	0	0
T1	5532	348	0	0
T2	2237756	34114	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	212	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	407541878	0	0
T1	5532	348	0	0
T2	2237756	34114	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	212	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	1571649624	0	0
T1	5532	4960	0	0
T2	2237756	2237180	0	0
T3	5448	5148	0	0
T4	1488624	1427740	0	0
T5	603972	603940	0	0
T7	6252	5496	0	0
T20	3576312	3575632	0	0
T21	6664	6436	0	0
T22	4016	3652	0	0
T23	567076	567036	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	1571649624	0	0
T1	5532	4960	0	0
T2	2237756	2237180	0	0
T3	5448	5148	0	0
T4	1488624	1427740	0	0
T5	603972	603940	0	0
T7	6252	5496	0	0
T20	3576312	3575632	0	0
T21	6664	6436	0	0
T22	4016	3652	0	0
T23	567076	567036	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	407541878	0	0
T1	5532	348	0	0
T2	2237756	34114	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	212	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	178143815	0	0
T1	5532	750	0	0
T2	2237756	1219994	0	0
T3	5448	256	0	0
T4	1488624	74248	0	0
T5	603972	17716	0	0
T7	6252	714	0	0
T12	0	1048878	0	0
T20	3576312	678768	0	0
T21	6664	256	0	0
T22	4016	256	0	0
T23	567076	3966	0	0
T24	0	62	0	0
T28	0	50	0	0
T41	0	292	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	431862007	0	0
T1	5532	348	0	0
T2	2237756	486846	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	222	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	407541878	0	0
T1	5532	348	0	0
T2	2237756	34114	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	212	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	407541878	0	0
T1	5532	348	0	0
T2	2237756	34114	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	212	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	431862007	0	0
T1	5532	348	0	0
T2	2237756	486846	0	0
T3	5448	64	0	0
T4	1488624	264858	0	0
T5	603972	2036074	0	0
T7	6252	222	0	0
T20	3576312	512708	0	0
T21	6664	64	0	0
T22	4016	584	0	0
T23	567076	2682702	0	0
T28	0	146	0	0
T41	0	3936	0	0
T42	0	554	0	0
T64	0	270298	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1575080644	1571649624	0	0
T1	5532	4960	0	0
T2	2237756	2237180	0	0
T3	5448	5148	0	0
T4	1488624	1427740	0	0
T5	603972	603940	0	0
T7	6252	5496	0	0
T20	3576312	3575632	0	0
T21	6664	6436	0	0
T22	4016	3652	0	0
T23	567076	567036	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393770161	392912406	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	393770161	110928096	0	0
GntImpliesValid_A	393770161	110928096	0	0
GrantKnown_A	393770161	392912406	0	0
IdxKnown_A	393770161	392912406	0	0
IndexIsCorrect_A	393770161	110928096	0	0
NoReadyValidNoGrant_A	393770161	46945396	0	0
Priority_A	393770161	117081351	0	0
ReadyAndValidImplyGrant_A	393770161	110928096	0	0
ReqAndReadyImplyGrant_A	393770161	110928096	0	0
ReqImpliesValid_A	393770161	117081351	0	0
ValidKnown_A	393770161	392912406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110928096	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110928096	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110928096	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	46945396	0	0
T1	1383	324	0	0
T2	559439	327937	0	0
T3	1362	128	0	0
T4	372156	37124	0	0
T5	150993	1014	0	0
T7	1563	350	0	0
T20	894078	265392	0	0
T21	1666	128	0	0
T22	1004	128	0	0
T23	141769	1820	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	117081351	0	0
T1	1383	156	0	0
T2	559439	127001	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	106	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110928096	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110928096	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	117081351	0	0
T1	1383	156	0	0
T2	559439	127001	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	106	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393770161	392912406	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	393770161	110927941	0	0
GntImpliesValid_A	393770161	110927941	0	0
GrantKnown_A	393770161	392912406	0	0
IdxKnown_A	393770161	392912406	0	0
IndexIsCorrect_A	393770161	110927941	0	0
NoReadyValidNoGrant_A	393770161	46945397	0	0
Priority_A	393770161	117081195	0	0
ReadyAndValidImplyGrant_A	393770161	110927941	0	0
ReqAndReadyImplyGrant_A	393770161	110927941	0	0
ReqImpliesValid_A	393770161	117081195	0	0
ValidKnown_A	393770161	392912406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110927941	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110927941	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110927941	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	46945397	0	0
T1	1383	324	0	0
T2	559439	327937	0	0
T3	1362	128	0	0
T4	372156	37124	0	0
T5	150993	1014	0	0
T7	1563	350	0	0
T20	894078	265392	0	0
T21	1666	128	0	0
T22	1004	128	0	0
T23	141769	1820	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	117081195	0	0
T1	1383	156	0	0
T2	559439	127001	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	106	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110927941	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	110927941	0	0
T1	1383	156	0	0
T2	559439	9323	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	102	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	117081195	0	0
T1	1383	156	0	0
T2	559439	127001	0	0
T3	1362	32	0	0
T4	372156	132429	0	0
T5	150993	331422	0	0
T7	1563	106	0	0
T20	894078	200377	0	0
T21	1666	32	0	0
T22	1004	292	0	0
T23	141769	783571	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T20,T5
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T20,T5
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T20,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393770161	392912406	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	393770161	92842894	0	0
GntImpliesValid_A	393770161	92842894	0	0
GrantKnown_A	393770161	392912406	0	0
IdxKnown_A	393770161	392912406	0	0
IndexIsCorrect_A	393770161	92842894	0	0
NoReadyValidNoGrant_A	393770161	42126516	0	0
Priority_A	393770161	98849699	0	0
ReadyAndValidImplyGrant_A	393770161	92842894	0	0
ReqAndReadyImplyGrant_A	393770161	92842894	0	0
ReqImpliesValid_A	393770161	98849699	0	0
ValidKnown_A	393770161	392912406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842894	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842894	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842894	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	42126516	0	0
T1	1383	51	0	0
T2	559439	282060	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	7844	0	0
T7	1563	7	0	0
T12	0	524439	0	0
T20	894078	73992	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	163	0	0
T24	0	31	0	0
T28	0	25	0	0
T41	0	146	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	98849699	0	0
T1	1383	18	0	0
T2	559439	116422	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	5	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842894	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842894	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	98849699	0	0
T1	1383	18	0	0
T2	559439	116422	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	5	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T20,T5
1	0	Covered	T1,T2,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T20,T5
1	1	Covered	T1,T2,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T20,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	393770161	392912406	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	393770161	92842947	0	0
GntImpliesValid_A	393770161	92842947	0	0
GrantKnown_A	393770161	392912406	0	0
IdxKnown_A	393770161	392912406	0	0
IndexIsCorrect_A	393770161	92842947	0	0
NoReadyValidNoGrant_A	393770161	42126506	0	0
Priority_A	393770161	98849762	0	0
ReadyAndValidImplyGrant_A	393770161	92842947	0	0
ReqAndReadyImplyGrant_A	393770161	92842947	0	0
ReqImpliesValid_A	393770161	98849762	0	0
ValidKnown_A	393770161	392912406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842947	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842947	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842947	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	42126506	0	0
T1	1383	51	0	0
T2	559439	282060	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	7844	0	0
T7	1563	7	0	0
T12	0	524439	0	0
T20	894078	73992	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	163	0	0
T24	0	31	0	0
T28	0	25	0	0
T41	0	146	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	98849762	0	0
T1	1383	18	0	0
T2	559439	116422	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	5	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842947	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	92842947	0	0
T1	1383	18	0	0
T2	559439	7734	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	4	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	98849762	0	0
T1	1383	18	0	0
T2	559439	116422	0	0
T3	1362	0	0	0
T4	372156	0	0	0
T5	150993	686615	0	0
T7	1563	5	0	0
T20	894078	55977	0	0
T21	1666	0	0	0
T22	1004	0	0	0
T23	141769	557780	0	0
T28	0	73	0	0
T41	0	1968	0	0
T42	0	277	0	0
T64	0	135149	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393770161	392912406	0	0
T1	1383	1240	0	0
T2	559439	559295	0	0
T3	1362	1287	0	0
T4	372156	356935	0	0
T5	150993	150985	0	0
T7	1563	1374	0	0
T20	894078	893908	0	0
T21	1666	1609	0	0
T22	1004	913	0	0
T23	141769	141759	0	0