Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.82 100.00 91.27 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.93 100.00 91.70 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.50 100.00 88.24 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.50 100.00 88.24 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 94.12 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 94.12 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORELINE
95.50 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
96.97 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T7
11CoveredT1,T20,T7

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T20,T7
111UnreachableT1,T20,T7

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T20,T7
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T20,T7
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T20,T7
11CoveredT1,T20,T7

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T62
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT7,T8,T62
10CoveredT1,T2,T3
11CoveredT1,T20,T7

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T20,T7

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
95.50 88.24
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
96.97 94.12
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions514996.08
Logical514996.08
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT78
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT78
101CoveredT78
110CoveredT1,T28,T12
111CoveredT1,T28,T12

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T28,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T28,T12
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT78
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT78
10CoveredT1,T2,T3
11CoveredT1,T28,T12

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T28,T12

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T23
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT57,T58,T59
11CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT8,T62,T25

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T8,T62
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T8,T62
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCOREBRANCH
95.50 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
96.97 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 6252 6252 0 0
GntImpliesReady_A 2147483647 70382831 0 0
GntImpliesValid_A 2147483647 70382831 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 70382831 0 0
LockArbDecision_A 2147483647 65537664 0 0
NoReadyValidNoGrant_A 2147483647 2008015658 0 0
ReadyAndValidImplyGrant_A 2147483647 70382831 0 0
ReqAndReadyImplyGrant_A 2147483647 70382831 0 0
ReqImpliesValid_A 2147483647 339564695 0 0
ReqStaysHighUntilGranted0_M 2147483647 65537222 0 0
RoundRobin_A 2147483647 0 0 6222
ValidKnown_A 2147483647 2147483647 0 0
gen_data_port_assertion.DataFlow_A 1575080644 65537966 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8298 7440 0 0
T2 3356634 3355770 0 0
T3 8172 7722 0 0
T4 2232936 2141610 0 0
T5 905958 905910 0 0
T7 9378 8244 0 0
T20 5364468 5363448 0 0
T21 9996 9654 0 0
T22 6024 5478 0 0
T23 850614 850554 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6252 6252 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T5 6 6 0 0
T7 6 6 0 0
T20 6 6 0 0
T21 6 6 0 0
T22 6 6 0 0
T23 6 6 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70382831 0 0
T1 8298 377 0 0
T2 3356634 16700 0 0
T3 8172 128 0 0
T4 2232936 40240 0 0
T5 905958 3007 0 0
T6 0 368 0 0
T7 9378 366 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 5364468 339416 0 0
T21 9996 128 0 0
T22 6024 128 0 0
T23 850614 741 0 0
T24 0 7 0 0
T28 0 47 0 0
T41 0 52 0 0
T61 0 860 0 0
T83 0 87 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70382831 0 0
T1 8298 377 0 0
T2 3356634 16700 0 0
T3 8172 128 0 0
T4 2232936 40240 0 0
T5 905958 3007 0 0
T6 0 368 0 0
T7 9378 366 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 5364468 339416 0 0
T21 9996 128 0 0
T22 6024 128 0 0
T23 850614 741 0 0
T24 0 7 0 0
T28 0 47 0 0
T41 0 52 0 0
T61 0 860 0 0
T83 0 87 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8298 7440 0 0
T2 3356634 3355770 0 0
T3 8172 7722 0 0
T4 2232936 2141610 0 0
T5 905958 905910 0 0
T7 9378 8244 0 0
T20 5364468 5363448 0 0
T21 9996 9654 0 0
T22 6024 5478 0 0
T23 850614 850554 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8298 7440 0 0
T2 3356634 3355770 0 0
T3 8172 7722 0 0
T4 2232936 2141610 0 0
T5 905958 905910 0 0
T7 9378 8244 0 0
T20 5364468 5363448 0 0
T21 9996 9654 0 0
T22 6024 5478 0 0
T23 850614 850554 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70382831 0 0
T1 8298 377 0 0
T2 3356634 16700 0 0
T3 8172 128 0 0
T4 2232936 40240 0 0
T5 905958 3007 0 0
T6 0 368 0 0
T7 9378 366 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 5364468 339416 0 0
T21 9996 128 0 0
T22 6024 128 0 0
T23 850614 741 0 0
T24 0 7 0 0
T28 0 47 0 0
T41 0 52 0 0
T61 0 860 0 0
T83 0 87 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 65537664 0 0
T1 5532 360 0 0
T2 2237756 256 0 0
T3 5448 128 0 0
T4 1488624 39328 0 0
T5 603972 128 0 0
T7 6252 346 0 0
T20 3576312 339416 0 0
T21 6664 128 0 0
T22 4016 128 0 0
T23 567076 128 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2008015658 0 0
T1 8298 5800 0 0
T2 3356634 2245578 0 0
T3 8172 7434 0 0
T4 2232936 1908351 0 0
T5 905958 2426352 0 0
T7 9378 7084 0 0
T20 5364468 4514967 0 0
T21 9996 9366 0 0
T22 6024 5190 0 0
T23 850614 831763 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70382831 0 0
T1 8298 377 0 0
T2 3356634 16700 0 0
T3 8172 128 0 0
T4 2232936 40240 0 0
T5 905958 3007 0 0
T6 0 368 0 0
T7 9378 366 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 5364468 339416 0 0
T21 9996 128 0 0
T22 6024 128 0 0
T23 850614 741 0 0
T24 0 7 0 0
T28 0 47 0 0
T41 0 52 0 0
T61 0 860 0 0
T83 0 87 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 70382831 0 0
T1 8298 377 0 0
T2 3356634 16700 0 0
T3 8172 128 0 0
T4 2232936 40240 0 0
T5 905958 3007 0 0
T6 0 368 0 0
T7 9378 366 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 5364468 339416 0 0
T21 9996 128 0 0
T22 6024 128 0 0
T23 850614 741 0 0
T24 0 7 0 0
T28 0 47 0 0
T41 0 52 0 0
T61 0 860 0 0
T83 0 87 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 339564695 0 0
T1 8298 1568 0 0
T2 3356634 1110120 0 0
T3 8172 256 0 0
T4 2232936 225511 0 0
T5 905958 1197468 0 0
T6 0 23480 0 0
T7 9378 1088 0 0
T8 0 127324 0 0
T12 0 258805 0 0
T20 5364468 678832 0 0
T21 9996 256 0 0
T22 6024 256 0 0
T23 850614 187844 0 0
T24 0 321 0 0
T28 0 2126 0 0
T41 0 14181 0 0
T61 0 55972 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 65537222 0 0
T1 5532 360 0 0
T2 2237756 256 0 0
T3 5448 128 0 0
T4 1488624 39328 0 0
T5 603972 128 0 0
T7 6252 346 0 0
T20 3576312 339416 0 0
T21 6664 128 0 0
T22 4016 128 0 0
T23 567076 128 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 6222

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8298 7440 0 0
T2 3356634 3355770 0 0
T3 8172 7722 0 0
T4 2232936 2141610 0 0
T5 905958 905910 0 0
T7 9378 8244 0 0
T20 5364468 5363448 0 0
T21 9996 9654 0 0
T22 6024 5478 0 0
T23 850614 850554 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1575080644 65537966 0 0
T1 5532 360 0 0
T2 2237756 256 0 0
T3 5448 128 0 0
T4 1488624 39328 0 0
T5 603972 128 0 0
T7 6252 346 0 0
T20 3576312 339416 0 0
T21 6664 128 0 0
T22 4016 128 0 0
T23 567076 128 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T23
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT57,T58,T59
11CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T4
110CoveredT1,T2,T4
111CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT8,T62,T25

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T8,T62
10CoveredT1,T2,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T8,T62
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 2711668 0 0
GntImpliesValid_A 393770161 2711668 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 2711668 0 0
LockArbDecision_A 393770161 0 0 0
NoReadyValidNoGrant_A 393770161 272439080 0 0
ReadyAndValidImplyGrant_A 393770161 2711668 0 0
ReqAndReadyImplyGrant_A 393770161 2711668 0 0
ReqImpliesValid_A 393770161 115213543 0 0
ReqStaysHighUntilGranted0_M 393770161 0 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2711668 0 0
T1 1383 10 0 0
T2 559439 8722 0 0
T3 1362 0 0 0
T4 372156 912 0 0
T5 150993 289 0 0
T6 0 368 0 0
T7 1563 20 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 559 0 0
T28 0 45 0 0
T41 0 25 0 0
T61 0 860 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2711668 0 0
T1 1383 10 0 0
T2 559439 8722 0 0
T3 1362 0 0 0
T4 372156 912 0 0
T5 150993 289 0 0
T6 0 368 0 0
T7 1563 20 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 559 0 0
T28 0 45 0 0
T41 0 25 0 0
T61 0 860 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2711668 0 0
T1 1383 10 0 0
T2 559439 8722 0 0
T3 1362 0 0 0
T4 372156 912 0 0
T5 150993 289 0 0
T6 0 368 0 0
T7 1563 20 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 559 0 0
T28 0 45 0 0
T41 0 25 0 0
T61 0 860 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 272439080 0 0
T1 1383 777 0 0
T2 559439 4425 0 0
T3 1362 1255 0 0
T4 372156 202332 0 0
T5 150993 857110 0 0
T7 1563 1105 0 0
T20 894078 761256 0 0
T21 1666 1577 0 0
T22 1004 881 0 0
T23 141769 136339 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2711668 0 0
T1 1383 10 0 0
T2 559439 8722 0 0
T3 1362 0 0 0
T4 372156 912 0 0
T5 150993 289 0 0
T6 0 368 0 0
T7 1563 20 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 559 0 0
T28 0 45 0 0
T41 0 25 0 0
T61 0 860 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2711668 0 0
T1 1383 10 0 0
T2 559439 8722 0 0
T3 1362 0 0 0
T4 372156 912 0 0
T5 150993 289 0 0
T6 0 368 0 0
T7 1563 20 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 559 0 0
T28 0 45 0 0
T41 0 25 0 0
T61 0 860 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 115213543 0 0
T1 1383 395 0 0
T2 559439 554802 0 0
T3 1362 0 0 0
T4 372156 146855 0 0
T5 150993 652708 0 0
T6 0 23480 0 0
T7 1563 201 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54160 0 0
T28 0 1455 0 0
T41 0 8588 0 0
T61 0 55972 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT8,T83,T140
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT8,T83,T140
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T23,T12
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT57,T58,T59
11CoveredT1,T2,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110CoveredT1,T2,T5
111CoveredT1,T2,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110CoveredT1,T2,T5
111CoveredT1,T2,T5

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110CoveredT1,T2,T5
111CoveredT1,T2,T5

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T20
101CoveredT1,T2,T5
110CoveredT1,T2,T5
111CoveredT1,T2,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT8,T62,T25

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT1,T2,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T62,T25
10CoveredT1,T2,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT8,T62,T63
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 2133197 0 0
GntImpliesValid_A 393770161 2133197 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 2133197 0 0
LockArbDecision_A 393770161 0 0 0
NoReadyValidNoGrant_A 393770161 295003052 0 0
ReadyAndValidImplyGrant_A 393770161 2133197 0 0
ReqAndReadyImplyGrant_A 393770161 2133197 0 0
ReqImpliesValid_A 393770161 93275098 0 0
ReqStaysHighUntilGranted0_M 393770161 0 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2133197 0 0
T1 1383 7 0 0
T2 559439 7722 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 2590 0 0
T7 1563 0 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54 0 0
T24 0 7 0 0
T28 0 2 0 0
T41 0 27 0 0
T83 0 87 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2133197 0 0
T1 1383 7 0 0
T2 559439 7722 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 2590 0 0
T7 1563 0 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54 0 0
T24 0 7 0 0
T28 0 2 0 0
T41 0 27 0 0
T83 0 87 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2133197 0 0
T1 1383 7 0 0
T2 559439 7722 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 2590 0 0
T7 1563 0 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54 0 0
T24 0 7 0 0
T28 0 2 0 0
T41 0 27 0 0
T83 0 87 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 295003052 0 0
T1 1383 783 0 0
T2 559439 4485 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 965326 0 0
T7 1563 1177 0 0
T20 894078 856911 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 128416 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2133197 0 0
T1 1383 7 0 0
T2 559439 7722 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 2590 0 0
T7 1563 0 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54 0 0
T24 0 7 0 0
T28 0 2 0 0
T41 0 27 0 0
T83 0 87 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 2133197 0 0
T1 1383 7 0 0
T2 559439 7722 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 2590 0 0
T7 1563 0 0 0
T8 0 9181 0 0
T12 0 50 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 54 0 0
T24 0 7 0 0
T28 0 2 0 0
T41 0 27 0 0
T83 0 87 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 93275098 0 0
T1 1383 453 0 0
T2 559439 554806 0 0
T3 1362 0 0 0
T4 372156 0 0 0
T5 150993 544504 0 0
T7 1563 193 0 0
T8 0 127324 0 0
T12 0 258805 0 0
T20 894078 0 0 0
T21 1666 0 0 0
T22 1004 0 0 0
T23 141769 133428 0 0
T24 0 321 0 0
T28 0 671 0 0
T41 0 5593 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514588.24
Logical514588.24
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT78
101Not Covered
110CoveredT1,T28,T12
111CoveredT1,T28,T12

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T28,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T28,T12
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T28,T12

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T28,T12

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 15792041 0 0
GntImpliesValid_A 393770161 15792041 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 15792041 0 0
LockArbDecision_A 393763634 15791912 0 0
NoReadyValidNoGrant_A 393770161 361328272 0 0
ReadyAndValidImplyGrant_A 393770161 15792041 0 0
ReqAndReadyImplyGrant_A 393770161 15792041 0 0
ReqImpliesValid_A 393770161 31584090 0 0
ReqStaysHighUntilGranted0_M 393763634 15791912 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0
gen_data_port_assertion.DataFlow_A 393770161 15792041 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393763634 15791912 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 361328272 0 0
T1 1383 1060 0 0
T2 559439 559167 0 0
T3 1362 1223 0 0
T4 372156 337271 0 0
T5 150993 150979 0 0
T7 1563 1211 0 0
T20 894078 893804 0 0
T21 1666 1545 0 0
T22 1004 849 0 0
T23 141769 141752 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 31584090 0 0
T1 1383 180 0 0
T2 559439 128 0 0
T3 1362 64 0 0
T4 372156 19664 0 0
T5 150993 64 0 0
T7 1563 163 0 0
T20 894078 104 0 0
T21 1666 64 0 0
T22 1004 64 0 0
T23 141769 64 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393763634 15791912 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792041 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514894.12
Logical514894.12
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT78
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT78
110CoveredT1,T28,T12
111CoveredT1,T28,T12

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T28,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T28,T12
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T28,T12
11CoveredT1,T28,T12

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT78
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT78
10CoveredT1,T2,T3
11CoveredT1,T28,T12

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T28,T12
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T28,T12

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 15792085 0 0
GntImpliesValid_A 393770161 15792085 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 15792085 0 0
LockArbDecision_A 393763634 15791912 0 0
NoReadyValidNoGrant_A 393770161 361328228 0 0
ReadyAndValidImplyGrant_A 393770161 15792085 0 0
ReqAndReadyImplyGrant_A 393770161 15792085 0 0
ReqImpliesValid_A 393770161 31584178 0 0
ReqStaysHighUntilGranted0_M 393763634 15791912 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0
gen_data_port_assertion.DataFlow_A 393770161 15792085 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393763634 15791912 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 361328228 0 0
T1 1383 1060 0 0
T2 559439 559167 0 0
T3 1362 1223 0 0
T4 372156 337271 0 0
T5 150993 150979 0 0
T7 1563 1211 0 0
T20 894078 893804 0 0
T21 1666 1545 0 0
T22 1004 849 0 0
T23 141769 141752 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 31584178 0 0
T1 1383 180 0 0
T2 559439 128 0 0
T3 1362 64 0 0
T4 372156 19664 0 0
T5 150993 64 0 0
T7 1563 163 0 0
T20 894078 104 0 0
T21 1666 64 0 0
T22 1004 64 0 0
T23 141769 64 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393763634 15791912 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 15792085 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 81 0 0
T20 894078 52 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T7
11CoveredT1,T20,T7

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T20,T7
111UnreachableT1,T20,T7

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T20,T7
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T20,T7
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T20,T7
11CoveredT1,T20,T7

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T62
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT7,T8,T62
10CoveredT1,T2,T3
11CoveredT1,T20,T7

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T20,T7

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 16976920 0 0
GntImpliesValid_A 393770161 16976920 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 16976920 0 0
LockArbDecision_A 393770076 16976920 0 0
NoReadyValidNoGrant_A 393770161 358958471 0 0
ReadyAndValidImplyGrant_A 393770161 16976920 0 0
ReqAndReadyImplyGrant_A 393770161 16976920 0 0
ReqImpliesValid_A 393770161 33953935 0 0
ReqStaysHighUntilGranted0_M 393757293 16976699 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0
gen_data_port_assertion.DataFlow_A 393770161 16976920 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770076 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 358958471 0 0
T1 1383 1060 0 0
T2 559439 559167 0 0
T3 1362 1223 0 0
T4 372156 337271 0 0
T5 150993 150979 0 0
T7 1563 1190 0 0
T20 894078 554596 0 0
T21 1666 1545 0 0
T22 1004 849 0 0
T23 141769 141752 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 33953935 0 0
T1 1383 180 0 0
T2 559439 128 0 0
T3 1362 64 0 0
T4 372156 19664 0 0
T5 150993 64 0 0
T7 1563 184 0 0
T20 894078 339312 0 0
T21 1666 64 0 0
T22 1004 64 0 0
T23 141769 64 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393757293 16976699 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T7
11CoveredT1,T20,T7

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT7,T8,T62
110CoveredT1,T20,T7
111UnreachableT1,T20,T7

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T20,T7
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T20,T7
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT1,T20,T7
11CoveredT1,T20,T7

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T62
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT7,T8,T62
10CoveredT1,T2,T3
11CoveredT1,T20,T7

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T20,T7
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T20,T7

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 393770161 392912406 0 0
CheckNGreaterZero_A 1042 1042 0 0
GntImpliesReady_A 393770161 16976920 0 0
GntImpliesValid_A 393770161 16976920 0 0
GrantKnown_A 393770161 392912406 0 0
IdxKnown_A 393770161 392912406 0 0
IndexIsCorrect_A 393770161 16976920 0 0
LockArbDecision_A 393770076 16976920 0 0
NoReadyValidNoGrant_A 393770161 358958555 0 0
ReadyAndValidImplyGrant_A 393770161 16976920 0 0
ReqAndReadyImplyGrant_A 393770161 16976920 0 0
ReqImpliesValid_A 393770161 33953851 0 0
ReqStaysHighUntilGranted0_M 393757293 16976699 0 0
RoundRobin_A 393770161 0 0 1037
ValidKnown_A 393770161 392912406 0 0
gen_data_port_assertion.DataFlow_A 393770161 16976920 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0
T23 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770076 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 358958555 0 0
T1 1383 1060 0 0
T2 559439 559167 0 0
T3 1362 1223 0 0
T4 372156 337271 0 0
T5 150993 150979 0 0
T7 1563 1190 0 0
T20 894078 554596 0 0
T21 1666 1545 0 0
T22 1004 849 0 0
T23 141769 141752 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 33953851 0 0
T1 1383 180 0 0
T2 559439 128 0 0
T3 1362 64 0 0
T4 372156 19664 0 0
T5 150993 64 0 0
T7 1563 184 0 0
T20 894078 339312 0 0
T21 1666 64 0 0
T22 1004 64 0 0
T23 141769 64 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 393757293 16976699 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 0 0 1037

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 392912406 0 0
T1 1383 1240 0 0
T2 559439 559295 0 0
T3 1362 1287 0 0
T4 372156 356935 0 0
T5 150993 150985 0 0
T7 1563 1374 0 0
T20 894078 893908 0 0
T21 1666 1609 0 0
T22 1004 913 0 0
T23 141769 141759 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 393770161 16976920 0 0
T1 1383 90 0 0
T2 559439 64 0 0
T3 1362 32 0 0
T4 372156 9832 0 0
T5 150993 32 0 0
T7 1563 92 0 0
T20 894078 169656 0 0
T21 1666 32 0 0
T22 1004 32 0 0
T23 141769 32 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%