Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26653822	1		T1	5424		T2	70		T3	3235
full_word	7696525	1		T1	10067		T2	43		T3	900

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34350017	1		T1	15491		T2	113		T3	4135
auto[TlIntgErrCmd]	107	1		T66	4		T116	4		T210	6
auto[TlIntgErrData]	109	1		T66	3		T116	7		T210	6
auto[TlIntgErrBoth]	114	1		T66	3		T116	9		T210	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29834899	1		T1	9949		T2	58		T3	3432
auto[1]	4515448	1		T1	5542		T2	55		T3	703

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25937791	1		T1	5183		T2	58		T3	3166
auto[TlIntgErrNone]	partial	auto[1]	715723	1		T1	241		T2	12		T3	69
auto[TlIntgErrNone]	full_word	auto[0]	3896955	1		T1	4766		T3	266		T4	2621
auto[TlIntgErrNone]	full_word	auto[1]	3799548	1		T1	5301		T2	43		T3	634
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T66	3		T116	2		T210	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T66	1		T116	2		T210	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T239	1		T272	1		T362	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T238	1		T271	1		T272	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T66	2		T116	4		T210	3
auto[TlIntgErrData]	partial	auto[1]	53	1		T66	1		T116	2		T210	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T116	1		T210	1		T363	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T360	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T116	2		T210	1		T238	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T66	2		T116	7		T210	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T360	1		T364	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T66	1		T210	3		T242	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20712	1		T66	8		T116	19		T118	904
full_word	4107624	1		T5	11280		T6	217		T7	220

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4128027	1		T5	11280		T6	217		T7	220
auto[TlIntgErrCmd]	99	1		T66	1		T116	9		T210	4
auto[TlIntgErrData]	113	1		T66	3		T116	7		T210	9
auto[TlIntgErrBoth]	97	1		T66	5		T116	4		T210	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4102220	1		T5	11280		T6	217		T7	220
auto[1]	26116	1		T66	7		T116	12		T118	1250

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1386	1		T118	37		T117	3		T209	30
auto[TlIntgErrNone]	partial	auto[1]	19044	1		T118	867		T117	150		T209	595
auto[TlIntgErrNone]	full_word	auto[0]	4100699	1		T5	11280		T6	217		T7	220
auto[TlIntgErrNone]	full_word	auto[1]	6898	1		T118	383		T117	53		T209	115
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T116	4		T238	2		T239	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T116	5		T210	4		T239	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T242	1		T272	2		T365	1
auto[TlIntgErrCmd]	full_word	auto[1]	11	1		T66	1		T240	1		T366	3
auto[TlIntgErrData]	partial	auto[0]	57	1		T66	1		T116	2		T210	5
auto[TlIntgErrData]	partial	auto[1]	49	1		T66	2		T116	4		T210	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T116	1		T365	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T210	1		T242	1		T367	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T66	1		T116	1		T210	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T66	4		T116	3		T210	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T272	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T240	1		T272	1		T365	1