Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1526238184	1523023856	0	0
CheckNGreaterZero_A	4208	4208	0	0
GntImpliesReady_A	1526238184	408393641	0	0
GntImpliesValid_A	1526238184	408393641	0	0
GrantKnown_A	1526238184	1523023856	0	0
IdxKnown_A	1526238184	1523023856	0	0
IndexIsCorrect_A	1526238184	408393641	0	0
NoReadyValidNoGrant_A	1526238184	171324306	0	0
Priority_A	1526238184	432629939	0	0
ReadyAndValidImplyGrant_A	1526238184	408393641	0	0
ReqAndReadyImplyGrant_A	1526238184	408393641	0	0
ReqImpliesValid_A	1526238184	432629939	0	0
ValidKnown_A	1526238184	1523023856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	1523023856	0	0
T1	444436	444212	0	0
T2	6992	6628	0	0
T3	40416	40128	0	0
T4	387028	386744	0	0
T5	290588	290308	0	0
T6	27644	27296	0	0
T19	14140	13880	0	0
T20	9332	9048	0	0
T21	4360	4108	0	0
T22	7488	7144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4208	4208	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	408393641	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	41292	0	0
T6	27644	5582	0	0
T7	18742	776	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	16470	0	0
T29	0	45028	0	0
T34	0	203382	0	0
T54	0	165330	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	408393641	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	41292	0	0
T6	27644	5582	0	0
T7	18742	776	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	16470	0	0
T29	0	45028	0	0
T34	0	203382	0	0
T54	0	165330	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	1523023856	0	0
T1	444436	444212	0	0
T2	6992	6628	0	0
T3	40416	40128	0	0
T4	387028	386744	0	0
T5	290588	290308	0	0
T6	27644	27296	0	0
T19	14140	13880	0	0
T20	9332	9048	0	0
T21	4360	4108	0	0
T22	7488	7144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	1523023856	0	0
T1	444436	444212	0	0
T2	6992	6628	0	0
T3	40416	40128	0	0
T4	387028	386744	0	0
T5	290588	290308	0	0
T6	27644	27296	0	0
T19	14140	13880	0	0
T20	9332	9048	0	0
T21	4360	4108	0	0
T22	7488	7144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	408393641	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	41292	0	0
T6	27644	5582	0	0
T7	18742	776	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	16470	0	0
T29	0	45028	0	0
T34	0	203382	0	0
T54	0	165330	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	171324306	0	0
T1	222218	128	0	0
T2	3496	256	0	0
T3	40416	994	0	0
T4	387028	7372	0	0
T5	290588	116280	0	0
T6	27644	1252	0	0
T7	18742	1150	0	0
T11	1254	0	0	0
T19	14140	256	0	0
T20	9332	256	0	0
T21	4360	256	0	0
T22	7488	256	0	0
T23	0	1530	0	0
T26	0	601888	0	0
T29	0	88944	0	0
T34	0	5060	0	0
T54	0	156260	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	432629939	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	43054	0	0
T6	27644	5708	0	0
T7	18742	778	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	245966	0	0
T29	0	48828	0	0
T34	0	203382	0	0
T54	0	203800	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	408393641	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	41292	0	0
T6	27644	5582	0	0
T7	18742	776	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	16470	0	0
T29	0	45028	0	0
T34	0	203382	0	0
T54	0	165330	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	408393641	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	41292	0	0
T6	27644	5582	0	0
T7	18742	776	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	16470	0	0
T29	0	45028	0	0
T34	0	203382	0	0
T54	0	165330	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	432629939	0	0
T1	222218	1104	0	0
T2	3496	64	0	0
T3	40416	15050	0	0
T4	387028	121852	0	0
T5	290588	43054	0	0
T6	27644	5708	0	0
T7	18742	778	0	0
T11	1254	0	0	0
T19	14140	64	0	0
T20	9332	64	0	0
T21	4360	64	0	0
T22	7488	64	0	0
T23	0	286000	0	0
T26	0	245966	0	0
T29	0	48828	0	0
T34	0	203382	0	0
T54	0	203800	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526238184	1523023856	0	0
T1	444436	444212	0	0
T2	6992	6628	0	0
T3	40416	40128	0	0
T4	387028	386744	0	0
T5	290588	290308	0	0
T6	27644	27296	0	0
T19	14140	13880	0	0
T20	9332	9048	0	0
T21	4360	4108	0	0
T22	7488	7144	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T26
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381559546	380755964	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	381559546	106499678	0	0
GntImpliesValid_A	381559546	106499678	0	0
GrantKnown_A	381559546	380755964	0	0
IdxKnown_A	381559546	380755964	0	0
IndexIsCorrect_A	381559546	106499678	0	0
NoReadyValidNoGrant_A	381559546	44188141	0	0
Priority_A	381559546	112723957	0	0
ReadyAndValidImplyGrant_A	381559546	106499678	0	0
ReqAndReadyImplyGrant_A	381559546	106499678	0	0
ReqImpliesValid_A	381559546	112723957	0	0
ValidKnown_A	381559546	380755964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499678	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499678	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499678	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	44188141	0	0
T1	111109	64	0	0
T2	1748	128	0	0
T3	10104	265	0	0
T4	96757	2090	0	0
T5	72647	29370	0	0
T6	6911	315	0	0
T19	3535	128	0	0
T20	2333	128	0	0
T21	1090	128	0	0
T22	1872	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	112723957	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	11013	0	0
T6	6911	1610	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499678	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499678	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	112723957	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	11013	0	0
T6	6911	1610	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T26
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381559546	380755964	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	381559546	106499520	0	0
GntImpliesValid_A	381559546	106499520	0	0
GrantKnown_A	381559546	380755964	0	0
IdxKnown_A	381559546	380755964	0	0
IndexIsCorrect_A	381559546	106499520	0	0
NoReadyValidNoGrant_A	381559546	44188144	0	0
Priority_A	381559546	112723796	0	0
ReadyAndValidImplyGrant_A	381559546	106499520	0	0
ReqAndReadyImplyGrant_A	381559546	106499520	0	0
ReqImpliesValid_A	381559546	112723796	0	0
ValidKnown_A	381559546	380755964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499520	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499520	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499520	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	44188144	0	0
T1	111109	64	0	0
T2	1748	128	0	0
T3	10104	265	0	0
T4	96757	2090	0	0
T5	72647	29370	0	0
T6	6911	315	0	0
T19	3535	128	0	0
T20	2333	128	0	0
T21	1090	128	0	0
T22	1872	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	112723796	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	11013	0	0
T6	6911	1610	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499520	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	106499520	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	10391	0	0
T6	6911	1591	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	112723796	0	0
T1	111109	552	0	0
T2	1748	32	0	0
T3	10104	4662	0	0
T4	96757	33838	0	0
T5	72647	11013	0	0
T6	6911	1610	0	0
T19	3535	32	0	0
T20	2333	32	0	0
T21	1090	32	0	0
T22	1872	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381559546	380755964	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	381559546	97697189	0	0
GntImpliesValid_A	381559546	97697189	0	0
GrantKnown_A	381559546	380755964	0	0
IdxKnown_A	381559546	380755964	0	0
IndexIsCorrect_A	381559546	97697189	0	0
NoReadyValidNoGrant_A	381559546	41474021	0	0
Priority_A	381559546	103591050	0	0
ReadyAndValidImplyGrant_A	381559546	97697189	0	0
ReqAndReadyImplyGrant_A	381559546	97697189	0	0
ReqImpliesValid_A	381559546	103591050	0	0
ValidKnown_A	381559546	380755964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697189	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697189	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697189	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	41474021	0	0
T3	10104	232	0	0
T4	96757	1596	0	0
T5	72647	28770	0	0
T6	6911	311	0	0
T7	9371	575	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	765	0	0
T26	0	300944	0	0
T29	0	44472	0	0
T34	0	2530	0	0
T54	0	78130	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	103591050	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10514	0	0
T6	6911	1244	0	0
T7	9371	389	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	122983	0	0
T29	0	24414	0	0
T34	0	101691	0	0
T54	0	101900	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697189	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697189	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	103591050	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10514	0	0
T6	6911	1244	0	0
T7	9371	389	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	122983	0	0
T29	0	24414	0	0
T34	0	101691	0	0
T54	0	101900	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T4,T5
1	1	Covered	T5,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T3,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381559546	380755964	0	0
CheckNGreaterZero_A	1052	1052	0	0
GntImpliesReady_A	381559546	97697254	0	0
GntImpliesValid_A	381559546	97697254	0	0
GrantKnown_A	381559546	380755964	0	0
IdxKnown_A	381559546	380755964	0	0
IndexIsCorrect_A	381559546	97697254	0	0
NoReadyValidNoGrant_A	381559546	41474000	0	0
Priority_A	381559546	103591136	0	0
ReadyAndValidImplyGrant_A	381559546	97697254	0	0
ReqAndReadyImplyGrant_A	381559546	97697254	0	0
ReqImpliesValid_A	381559546	103591136	0	0
ValidKnown_A	381559546	380755964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1052	1052	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697254	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697254	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697254	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	41474000	0	0
T3	10104	232	0	0
T4	96757	1596	0	0
T5	72647	28770	0	0
T6	6911	311	0	0
T7	9371	575	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	765	0	0
T26	0	300944	0	0
T29	0	44472	0	0
T34	0	2530	0	0
T54	0	78130	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	103591136	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10514	0	0
T6	6911	1244	0	0
T7	9371	389	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	122983	0	0
T29	0	24414	0	0
T34	0	101691	0	0
T54	0	101900	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697254	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	97697254	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10255	0	0
T6	6911	1200	0	0
T7	9371	388	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	8235	0	0
T29	0	22514	0	0
T34	0	101691	0	0
T54	0	82665	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	103591136	0	0
T3	10104	2863	0	0
T4	96757	27088	0	0
T5	72647	10514	0	0
T6	6911	1244	0	0
T7	9371	389	0	0
T11	627	0	0	0
T19	3535	0	0	0
T20	2333	0	0	0
T21	1090	0	0	0
T22	1872	0	0	0
T23	0	143000	0	0
T26	0	122983	0	0
T29	0	24414	0	0
T34	0	101691	0	0
T54	0	101900	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381559546	380755964	0	0
T1	111109	111053	0	0
T2	1748	1657	0	0
T3	10104	10032	0	0
T4	96757	96686	0	0
T5	72647	72577	0	0
T6	6911	6824	0	0
T19	3535	3470	0	0
T20	2333	2262	0	0
T21	1090	1027	0	0
T22	1872	1786	0	0