| T1080 |
/workspace/coverage/default/35.flash_ctrl_disable.2383505858 |
|
|
Jul 06 05:54:40 PM PDT 24 |
Jul 06 05:55:02 PM PDT 24 |
13910000 ps |
| T1081 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.2619231832 |
|
|
Jul 06 05:51:16 PM PDT 24 |
Jul 06 05:55:51 PM PDT 24 |
293340900 ps |
| T1082 |
/workspace/coverage/default/36.flash_ctrl_otp_reset.1197272393 |
|
|
Jul 06 05:54:41 PM PDT 24 |
Jul 06 05:56:32 PM PDT 24 |
38488100 ps |
| T1083 |
/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.6768087 |
|
|
Jul 06 05:54:24 PM PDT 24 |
Jul 06 05:55:25 PM PDT 24 |
6786080100 ps |
| T1084 |
/workspace/coverage/default/29.flash_ctrl_prog_reset.2626688680 |
|
|
Jul 06 05:54:11 PM PDT 24 |
Jul 06 05:54:25 PM PDT 24 |
38897500 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.940893026 |
|
|
Jul 06 05:50:01 PM PDT 24 |
Jul 06 05:50:14 PM PDT 24 |
15966200 ps |
| T374 |
/workspace/coverage/default/46.flash_ctrl_disable.841862118 |
|
|
Jul 06 05:55:20 PM PDT 24 |
Jul 06 05:55:42 PM PDT 24 |
14890500 ps |
| T14 |
/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2257220645 |
|
|
Jul 06 05:50:00 PM PDT 24 |
Jul 06 05:50:14 PM PDT 24 |
14951400 ps |
| T1086 |
/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2818259627 |
|
|
Jul 06 05:49:09 PM PDT 24 |
Jul 06 05:49:41 PM PDT 24 |
136630200 ps |
| T1087 |
/workspace/coverage/default/17.flash_ctrl_phy_arb.3070188323 |
|
|
Jul 06 05:52:44 PM PDT 24 |
Jul 06 05:57:46 PM PDT 24 |
720241500 ps |
| T201 |
/workspace/coverage/default/2.flash_ctrl_rma_err.1263436871 |
|
|
Jul 06 05:49:15 PM PDT 24 |
Jul 06 06:04:39 PM PDT 24 |
163790537000 ps |
| T1088 |
/workspace/coverage/default/72.flash_ctrl_connect.4005826718 |
|
|
Jul 06 05:55:50 PM PDT 24 |
Jul 06 05:56:06 PM PDT 24 |
27826200 ps |
| T1089 |
/workspace/coverage/default/17.flash_ctrl_sec_info_access.2901575777 |
|
|
Jul 06 05:52:53 PM PDT 24 |
Jul 06 05:54:10 PM PDT 24 |
4102733600 ps |
| T1090 |
/workspace/coverage/default/43.flash_ctrl_alert_test.4243035179 |
|
|
Jul 06 05:55:14 PM PDT 24 |
Jul 06 05:55:28 PM PDT 24 |
116392200 ps |
| T1091 |
/workspace/coverage/default/1.flash_ctrl_smoke.3090928197 |
|
|
Jul 06 05:48:55 PM PDT 24 |
Jul 06 05:52:35 PM PDT 24 |
709347600 ps |
| T1092 |
/workspace/coverage/default/40.flash_ctrl_connect.3244886294 |
|
|
Jul 06 05:55:08 PM PDT 24 |
Jul 06 05:55:24 PM PDT 24 |
45019100 ps |
| T1093 |
/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.730254016 |
|
|
Jul 06 05:53:52 PM PDT 24 |
Jul 06 05:56:28 PM PDT 24 |
23097052200 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3851957117 |
|
|
Jul 06 05:48:49 PM PDT 24 |
Jul 06 05:50:43 PM PDT 24 |
737220300 ps |
| T1095 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3442548351 |
|
|
Jul 06 05:49:58 PM PDT 24 |
Jul 06 05:50:21 PM PDT 24 |
19517200 ps |
| T1096 |
/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.1744420300 |
|
|
Jul 06 05:49:19 PM PDT 24 |
Jul 06 05:49:42 PM PDT 24 |
42204600 ps |
| T1097 |
/workspace/coverage/default/36.flash_ctrl_sec_info_access.2659024475 |
|
|
Jul 06 05:54:41 PM PDT 24 |
Jul 06 05:55:52 PM PDT 24 |
672492400 ps |
| T1098 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.698001250 |
|
|
Jul 06 05:53:56 PM PDT 24 |
Jul 06 05:56:43 PM PDT 24 |
17563338500 ps |
| T1099 |
/workspace/coverage/default/27.flash_ctrl_otp_reset.506965068 |
|
|
Jul 06 05:53:59 PM PDT 24 |
Jul 06 05:56:12 PM PDT 24 |
241663500 ps |
| T1100 |
/workspace/coverage/default/28.flash_ctrl_rw_evict.2444037414 |
|
|
Jul 06 05:54:05 PM PDT 24 |
Jul 06 05:54:36 PM PDT 24 |
29095200 ps |
| T1101 |
/workspace/coverage/default/40.flash_ctrl_smoke.1184122966 |
|
|
Jul 06 05:55:09 PM PDT 24 |
Jul 06 05:55:59 PM PDT 24 |
44629900 ps |
| T1102 |
/workspace/coverage/default/20.flash_ctrl_prog_reset.155529724 |
|
|
Jul 06 05:53:14 PM PDT 24 |
Jul 06 05:53:28 PM PDT 24 |
38134600 ps |
| T1103 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.3023319235 |
|
|
Jul 06 05:49:16 PM PDT 24 |
Jul 06 06:58:15 PM PDT 24 |
306186734400 ps |
| T1104 |
/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1551229473 |
|
|
Jul 06 05:55:13 PM PDT 24 |
Jul 06 05:57:24 PM PDT 24 |
8605494500 ps |
| T1105 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.915607332 |
|
|
Jul 06 05:52:53 PM PDT 24 |
Jul 06 05:54:55 PM PDT 24 |
8537299600 ps |
| T1106 |
/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.205479887 |
|
|
Jul 06 05:52:53 PM PDT 24 |
Jul 06 05:54:41 PM PDT 24 |
10032116900 ps |
| T1107 |
/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2578569904 |
|
|
Jul 06 05:49:07 PM PDT 24 |
Jul 06 05:49:59 PM PDT 24 |
1241055400 ps |
| T1108 |
/workspace/coverage/default/9.flash_ctrl_ro_serr.3721807712 |
|
|
Jul 06 05:51:05 PM PDT 24 |
Jul 06 05:53:48 PM PDT 24 |
2755414500 ps |
| T1109 |
/workspace/coverage/default/48.flash_ctrl_otp_reset.973246620 |
|
|
Jul 06 05:55:28 PM PDT 24 |
Jul 06 05:57:19 PM PDT 24 |
78281400 ps |
| T1110 |
/workspace/coverage/default/19.flash_ctrl_disable.3079691695 |
|
|
Jul 06 05:53:10 PM PDT 24 |
Jul 06 05:53:30 PM PDT 24 |
14954600 ps |
| T1111 |
/workspace/coverage/default/3.flash_ctrl_intr_wr.1149951857 |
|
|
Jul 06 05:49:18 PM PDT 24 |
Jul 06 05:50:32 PM PDT 24 |
2625693500 ps |
| T394 |
/workspace/coverage/default/41.flash_ctrl_sec_info_access.2504440606 |
|
|
Jul 06 05:55:08 PM PDT 24 |
Jul 06 05:56:24 PM PDT 24 |
5980475100 ps |
| T1112 |
/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2223529346 |
|
|
Jul 06 05:52:55 PM PDT 24 |
Jul 06 05:53:49 PM PDT 24 |
2798140900 ps |
| T1113 |
/workspace/coverage/default/2.flash_ctrl_rand_ops.1711525279 |
|
|
Jul 06 05:49:13 PM PDT 24 |
Jul 06 06:03:46 PM PDT 24 |
201018300 ps |
| T1114 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3547386147 |
|
|
Jul 06 05:51:42 PM PDT 24 |
Jul 06 05:51:56 PM PDT 24 |
46851600 ps |
| T401 |
/workspace/coverage/default/5.flash_ctrl_sec_info_access.1036587849 |
|
|
Jul 06 05:50:10 PM PDT 24 |
Jul 06 05:51:14 PM PDT 24 |
2391859900 ps |
| T1115 |
/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2572755221 |
|
|
Jul 06 05:54:00 PM PDT 24 |
Jul 06 05:55:20 PM PDT 24 |
3082821200 ps |
| T1116 |
/workspace/coverage/default/34.flash_ctrl_intr_rd.1213243504 |
|
|
Jul 06 05:54:34 PM PDT 24 |
Jul 06 05:58:20 PM PDT 24 |
3089030600 ps |
| T1117 |
/workspace/coverage/default/15.flash_ctrl_re_evict.3437481749 |
|
|
Jul 06 05:52:26 PM PDT 24 |
Jul 06 05:53:01 PM PDT 24 |
745171500 ps |
| T1118 |
/workspace/coverage/default/20.flash_ctrl_connect.2312080785 |
|
|
Jul 06 05:53:16 PM PDT 24 |
Jul 06 05:53:32 PM PDT 24 |
17112900 ps |
| T1119 |
/workspace/coverage/default/16.flash_ctrl_mp_regions.3887609065 |
|
|
Jul 06 05:52:39 PM PDT 24 |
Jul 06 05:56:40 PM PDT 24 |
8345035100 ps |
| T342 |
/workspace/coverage/default/34.flash_ctrl_rw_evict.1158719026 |
|
|
Jul 06 05:54:39 PM PDT 24 |
Jul 06 05:55:09 PM PDT 24 |
54274200 ps |
| T1120 |
/workspace/coverage/default/3.flash_ctrl_serr_counter.2087580337 |
|
|
Jul 06 05:49:18 PM PDT 24 |
Jul 06 05:50:20 PM PDT 24 |
1088436400 ps |
| T1121 |
/workspace/coverage/default/53.flash_ctrl_connect.4200680585 |
|
|
Jul 06 05:55:36 PM PDT 24 |
Jul 06 05:55:52 PM PDT 24 |
31115900 ps |
| T1122 |
/workspace/coverage/default/74.flash_ctrl_connect.2735638671 |
|
|
Jul 06 05:55:50 PM PDT 24 |
Jul 06 05:56:06 PM PDT 24 |
28239400 ps |
| T1123 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3679087943 |
|
|
Jul 06 05:49:19 PM PDT 24 |
Jul 06 05:52:07 PM PDT 24 |
5869729800 ps |
| T1124 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2450161977 |
|
|
Jul 06 05:51:16 PM PDT 24 |
Jul 06 05:51:29 PM PDT 24 |
85111800 ps |
| T100 |
/workspace/coverage/default/0.flash_ctrl_wr_intg.289728399 |
|
|
Jul 06 05:48:56 PM PDT 24 |
Jul 06 05:49:12 PM PDT 24 |
200658500 ps |
| T249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3874051621 |
|
|
Jul 06 05:36:19 PM PDT 24 |
Jul 06 05:36:33 PM PDT 24 |
26609700 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3780525515 |
|
|
Jul 06 05:37:19 PM PDT 24 |
Jul 06 05:37:34 PM PDT 24 |
169704200 ps |
| T263 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1444457128 |
|
|
Jul 06 05:37:13 PM PDT 24 |
Jul 06 05:37:27 PM PDT 24 |
24982300 ps |
| T264 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3841468960 |
|
|
Jul 06 05:37:36 PM PDT 24 |
Jul 06 05:37:51 PM PDT 24 |
15701800 ps |
| T265 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2839354749 |
|
|
Jul 06 05:36:41 PM PDT 24 |
Jul 06 05:36:55 PM PDT 24 |
37577800 ps |
| T318 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1089727371 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:04 PM PDT 24 |
17784300 ps |
| T66 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3536337556 |
|
|
Jul 06 05:37:27 PM PDT 24 |
Jul 06 05:45:13 PM PDT 24 |
489184500 ps |
| T250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.363123318 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:36:42 PM PDT 24 |
22116800 ps |
| T67 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3660315543 |
|
|
Jul 06 05:37:02 PM PDT 24 |
Jul 06 05:37:19 PM PDT 24 |
134381500 ps |
| T260 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1982661622 |
|
|
Jul 06 05:36:39 PM PDT 24 |
Jul 06 05:36:58 PM PDT 24 |
110357100 ps |
| T316 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3705379088 |
|
|
Jul 06 05:37:33 PM PDT 24 |
Jul 06 05:37:46 PM PDT 24 |
44636200 ps |
| T317 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2263361779 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:05 PM PDT 24 |
39524600 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.329083886 |
|
|
Jul 06 05:36:37 PM PDT 24 |
Jul 06 05:49:10 PM PDT 24 |
340432500 ps |
| T1125 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2545973313 |
|
|
Jul 06 05:36:22 PM PDT 24 |
Jul 06 05:36:35 PM PDT 24 |
130423800 ps |
| T118 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3184858178 |
|
|
Jul 06 05:37:14 PM PDT 24 |
Jul 06 05:37:35 PM PDT 24 |
64777200 ps |
| T117 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1219382921 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:50 PM PDT 24 |
25295100 ps |
| T261 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1641686026 |
|
|
Jul 06 05:36:51 PM PDT 24 |
Jul 06 05:37:09 PM PDT 24 |
73509900 ps |
| T319 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2415827550 |
|
|
Jul 06 05:36:13 PM PDT 24 |
Jul 06 05:36:27 PM PDT 24 |
17556100 ps |
| T210 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2909124433 |
|
|
Jul 06 05:36:08 PM PDT 24 |
Jul 06 05:51:07 PM PDT 24 |
1578419300 ps |
| T293 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1969277136 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:50 PM PDT 24 |
144554500 ps |
| T315 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2005876661 |
|
|
Jul 06 05:36:13 PM PDT 24 |
Jul 06 05:37:36 PM PDT 24 |
9101111800 ps |
| T238 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3957759167 |
|
|
Jul 06 05:37:14 PM PDT 24 |
Jul 06 05:44:52 PM PDT 24 |
685307800 ps |
| T415 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2308696994 |
|
|
Jul 06 05:36:19 PM PDT 24 |
Jul 06 05:37:40 PM PDT 24 |
2196402600 ps |
| T1126 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1198714652 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:04 PM PDT 24 |
50677600 ps |
| T294 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2092157917 |
|
|
Jul 06 05:36:55 PM PDT 24 |
Jul 06 05:37:14 PM PDT 24 |
100664100 ps |
| T295 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.566325593 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:36:46 PM PDT 24 |
212481400 ps |
| T1127 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2462623544 |
|
|
Jul 06 05:36:31 PM PDT 24 |
Jul 06 05:36:47 PM PDT 24 |
13613100 ps |
| T239 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2461930392 |
|
|
Jul 06 05:36:55 PM PDT 24 |
Jul 06 05:51:54 PM PDT 24 |
835045500 ps |
| T1128 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3376028179 |
|
|
Jul 06 05:37:10 PM PDT 24 |
Jul 06 05:37:26 PM PDT 24 |
41588300 ps |
| T320 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1693223040 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:04 PM PDT 24 |
17124200 ps |
| T296 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3118471880 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:54 PM PDT 24 |
95993800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.234779626 |
|
|
Jul 06 05:36:42 PM PDT 24 |
Jul 06 05:36:59 PM PDT 24 |
11957800 ps |
| T1130 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3070975501 |
|
|
Jul 06 05:37:39 PM PDT 24 |
Jul 06 05:37:55 PM PDT 24 |
14082700 ps |
| T209 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.256321503 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:16 PM PDT 24 |
35996200 ps |
| T240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1912888456 |
|
|
Jul 06 05:36:23 PM PDT 24 |
Jul 06 05:51:14 PM PDT 24 |
673249000 ps |
| T297 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3710880600 |
|
|
Jul 06 05:37:01 PM PDT 24 |
Jul 06 05:37:37 PM PDT 24 |
3577989700 ps |
| T241 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2006984485 |
|
|
Jul 06 05:37:25 PM PDT 24 |
Jul 06 05:37:43 PM PDT 24 |
82688000 ps |
| T1131 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2281440992 |
|
|
Jul 06 05:38:06 PM PDT 24 |
Jul 06 05:38:22 PM PDT 24 |
26703000 ps |
| T1132 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2973204844 |
|
|
Jul 06 05:37:27 PM PDT 24 |
Jul 06 05:37:43 PM PDT 24 |
12173500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3589597981 |
|
|
Jul 06 05:36:12 PM PDT 24 |
Jul 06 05:36:26 PM PDT 24 |
29126200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2234904247 |
|
|
Jul 06 05:37:08 PM PDT 24 |
Jul 06 05:37:22 PM PDT 24 |
55147700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3581291196 |
|
|
Jul 06 05:37:29 PM PDT 24 |
Jul 06 05:37:44 PM PDT 24 |
34666100 ps |
| T1136 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2946342281 |
|
|
Jul 06 05:37:32 PM PDT 24 |
Jul 06 05:37:46 PM PDT 24 |
60971700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2673718251 |
|
|
Jul 06 05:37:39 PM PDT 24 |
Jul 06 05:37:56 PM PDT 24 |
19316800 ps |
| T242 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1342058073 |
|
|
Jul 06 05:37:02 PM PDT 24 |
Jul 06 05:52:15 PM PDT 24 |
1316769800 ps |
| T243 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3394145100 |
|
|
Jul 06 05:37:09 PM PDT 24 |
Jul 06 05:37:26 PM PDT 24 |
31239900 ps |
| T244 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2894070710 |
|
|
Jul 06 05:36:32 PM PDT 24 |
Jul 06 05:36:51 PM PDT 24 |
127757300 ps |
| T245 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1399393282 |
|
|
Jul 06 05:37:12 PM PDT 24 |
Jul 06 05:37:31 PM PDT 24 |
57037200 ps |
| T1138 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.304979417 |
|
|
Jul 06 05:37:48 PM PDT 24 |
Jul 06 05:38:02 PM PDT 24 |
30680500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3569368719 |
|
|
Jul 06 05:36:28 PM PDT 24 |
Jul 06 05:36:41 PM PDT 24 |
43539800 ps |
| T1140 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1030102181 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:50 PM PDT 24 |
31864200 ps |
| T321 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2699006408 |
|
|
Jul 06 05:37:44 PM PDT 24 |
Jul 06 05:37:58 PM PDT 24 |
45062200 ps |
| T1141 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1962195593 |
|
|
Jul 06 05:37:09 PM PDT 24 |
Jul 06 05:37:23 PM PDT 24 |
51240300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.472027642 |
|
|
Jul 06 05:36:32 PM PDT 24 |
Jul 06 05:37:03 PM PDT 24 |
155560000 ps |
| T298 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.849989757 |
|
|
Jul 06 05:36:44 PM PDT 24 |
Jul 06 05:37:00 PM PDT 24 |
72928000 ps |
| T299 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.191997392 |
|
|
Jul 06 05:36:42 PM PDT 24 |
Jul 06 05:38:19 PM PDT 24 |
6318881500 ps |
| T246 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.870279422 |
|
|
Jul 06 05:37:18 PM PDT 24 |
Jul 06 05:37:36 PM PDT 24 |
36980400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1671358257 |
|
|
Jul 06 05:37:42 PM PDT 24 |
Jul 06 05:37:56 PM PDT 24 |
32152300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3356209324 |
|
|
Jul 06 05:37:47 PM PDT 24 |
Jul 06 05:38:01 PM PDT 24 |
53512900 ps |
| T247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.210978201 |
|
|
Jul 06 05:37:38 PM PDT 24 |
Jul 06 05:37:58 PM PDT 24 |
32442700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2563933375 |
|
|
Jul 06 05:37:09 PM PDT 24 |
Jul 06 05:37:26 PM PDT 24 |
37335900 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1597824958 |
|
|
Jul 06 05:36:18 PM PDT 24 |
Jul 06 05:36:50 PM PDT 24 |
97026000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4220135879 |
|
|
Jul 06 05:36:33 PM PDT 24 |
Jul 06 05:36:47 PM PDT 24 |
45499000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.616122761 |
|
|
Jul 06 05:37:17 PM PDT 24 |
Jul 06 05:37:30 PM PDT 24 |
77962200 ps |
| T300 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3724953093 |
|
|
Jul 06 05:37:27 PM PDT 24 |
Jul 06 05:37:43 PM PDT 24 |
55521800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1985842327 |
|
|
Jul 06 05:37:43 PM PDT 24 |
Jul 06 05:37:56 PM PDT 24 |
41066300 ps |
| T271 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3673142162 |
|
|
Jul 06 05:37:24 PM PDT 24 |
Jul 06 05:43:55 PM PDT 24 |
798725300 ps |
| T1150 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3583906083 |
|
|
Jul 06 05:37:48 PM PDT 24 |
Jul 06 05:38:03 PM PDT 24 |
223292500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3750290026 |
|
|
Jul 06 05:36:45 PM PDT 24 |
Jul 06 05:37:01 PM PDT 24 |
44185700 ps |
| T272 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2602591019 |
|
|
Jul 06 05:37:16 PM PDT 24 |
Jul 06 05:52:13 PM PDT 24 |
5563088300 ps |
| T1152 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2467906290 |
|
|
Jul 06 05:36:57 PM PDT 24 |
Jul 06 05:37:11 PM PDT 24 |
17446100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1028095752 |
|
|
Jul 06 05:36:28 PM PDT 24 |
Jul 06 05:37:24 PM PDT 24 |
1706561200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.873637501 |
|
|
Jul 06 05:36:25 PM PDT 24 |
Jul 06 05:36:41 PM PDT 24 |
11949700 ps |
| T301 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4087398819 |
|
|
Jul 06 05:37:23 PM PDT 24 |
Jul 06 05:37:41 PM PDT 24 |
114582300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1694713045 |
|
|
Jul 06 05:37:37 PM PDT 24 |
Jul 06 05:37:51 PM PDT 24 |
24988700 ps |
| T1156 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2823048686 |
|
|
Jul 06 05:37:12 PM PDT 24 |
Jul 06 05:37:30 PM PDT 24 |
135472100 ps |
| T302 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2601569016 |
|
|
Jul 06 05:37:21 PM PDT 24 |
Jul 06 05:37:40 PM PDT 24 |
115516500 ps |
| T1157 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3756789921 |
|
|
Jul 06 05:37:43 PM PDT 24 |
Jul 06 05:37:57 PM PDT 24 |
33521000 ps |
| T266 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.501741913 |
|
|
Jul 06 05:37:00 PM PDT 24 |
Jul 06 05:37:20 PM PDT 24 |
116059900 ps |
| T1158 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1374483458 |
|
|
Jul 06 05:37:47 PM PDT 24 |
Jul 06 05:38:01 PM PDT 24 |
17872500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.435868518 |
|
|
Jul 06 05:37:00 PM PDT 24 |
Jul 06 05:37:14 PM PDT 24 |
16058300 ps |
| T268 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2380468954 |
|
|
Jul 06 05:37:33 PM PDT 24 |
Jul 06 05:37:52 PM PDT 24 |
50529800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2825061203 |
|
|
Jul 06 05:36:47 PM PDT 24 |
Jul 06 05:37:05 PM PDT 24 |
74053000 ps |
| T278 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1729969330 |
|
|
Jul 06 05:37:11 PM PDT 24 |
Jul 06 05:37:28 PM PDT 24 |
138242400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3625663522 |
|
|
Jul 06 05:36:20 PM PDT 24 |
Jul 06 05:36:34 PM PDT 24 |
72592700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3393495307 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:06 PM PDT 24 |
18710300 ps |
| T1163 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4174719019 |
|
|
Jul 06 05:37:24 PM PDT 24 |
Jul 06 05:37:40 PM PDT 24 |
250839900 ps |
| T262 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1180991860 |
|
|
Jul 06 05:36:11 PM PDT 24 |
Jul 06 05:36:27 PM PDT 24 |
39179300 ps |
| T1164 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2207968431 |
|
|
Jul 06 05:36:59 PM PDT 24 |
Jul 06 05:37:17 PM PDT 24 |
75054000 ps |
| T274 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.927298106 |
|
|
Jul 06 05:36:40 PM PDT 24 |
Jul 06 05:36:57 PM PDT 24 |
202083300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1241948418 |
|
|
Jul 06 05:37:11 PM PDT 24 |
Jul 06 05:37:24 PM PDT 24 |
12007500 ps |
| T1166 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.475971769 |
|
|
Jul 06 05:37:02 PM PDT 24 |
Jul 06 05:37:18 PM PDT 24 |
19567700 ps |
| T303 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2795265671 |
|
|
Jul 06 05:37:18 PM PDT 24 |
Jul 06 05:37:37 PM PDT 24 |
222907000 ps |
| T269 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2459677383 |
|
|
Jul 06 05:37:28 PM PDT 24 |
Jul 06 05:37:49 PM PDT 24 |
81686800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1375097484 |
|
|
Jul 06 05:36:16 PM PDT 24 |
Jul 06 05:36:32 PM PDT 24 |
19303300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3564556722 |
|
|
Jul 06 05:37:25 PM PDT 24 |
Jul 06 05:37:38 PM PDT 24 |
21122800 ps |
| T304 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2030724584 |
|
|
Jul 06 05:37:12 PM PDT 24 |
Jul 06 05:37:28 PM PDT 24 |
271520900 ps |
| T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.316361188 |
|
|
Jul 06 05:36:39 PM PDT 24 |
Jul 06 05:36:55 PM PDT 24 |
18953100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3144426947 |
|
|
Jul 06 05:37:08 PM PDT 24 |
Jul 06 05:37:27 PM PDT 24 |
71155400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1325285104 |
|
|
Jul 06 05:37:15 PM PDT 24 |
Jul 06 05:37:31 PM PDT 24 |
14743100 ps |
| T305 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3917859371 |
|
|
Jul 06 05:36:18 PM PDT 24 |
Jul 06 05:37:28 PM PDT 24 |
8397618000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1842051908 |
|
|
Jul 06 05:36:15 PM PDT 24 |
Jul 06 05:36:33 PM PDT 24 |
49812600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.833522260 |
|
|
Jul 06 05:36:22 PM PDT 24 |
Jul 06 05:36:39 PM PDT 24 |
38279300 ps |
| T276 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2325563778 |
|
|
Jul 06 05:37:13 PM PDT 24 |
Jul 06 05:37:32 PM PDT 24 |
86880100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1453414191 |
|
|
Jul 06 05:37:32 PM PDT 24 |
Jul 06 05:37:52 PM PDT 24 |
110339700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.369712846 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:48 PM PDT 24 |
12344200 ps |
| T251 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2893023789 |
|
|
Jul 06 05:36:42 PM PDT 24 |
Jul 06 05:36:56 PM PDT 24 |
24406000 ps |
| T1176 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.223606106 |
|
|
Jul 06 05:36:52 PM PDT 24 |
Jul 06 05:37:06 PM PDT 24 |
98053800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1640806328 |
|
|
Jul 06 05:36:57 PM PDT 24 |
Jul 06 05:37:14 PM PDT 24 |
11661200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2687115656 |
|
|
Jul 06 05:37:03 PM PDT 24 |
Jul 06 05:37:32 PM PDT 24 |
843149300 ps |
| T1179 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4087528243 |
|
|
Jul 06 05:37:33 PM PDT 24 |
Jul 06 05:37:52 PM PDT 24 |
208245500 ps |
| T267 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1639909163 |
|
|
Jul 06 05:37:09 PM PDT 24 |
Jul 06 05:37:29 PM PDT 24 |
215169900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4055024402 |
|
|
Jul 06 05:37:09 PM PDT 24 |
Jul 06 05:37:25 PM PDT 24 |
34246900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2239526575 |
|
|
Jul 06 05:37:18 PM PDT 24 |
Jul 06 05:37:34 PM PDT 24 |
30266700 ps |
| T1182 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1259420865 |
|
|
Jul 06 05:36:32 PM PDT 24 |
Jul 06 05:36:50 PM PDT 24 |
105998300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2388826927 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:16 PM PDT 24 |
234810700 ps |
| T366 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.922703465 |
|
|
Jul 06 05:37:39 PM PDT 24 |
Jul 06 05:52:42 PM PDT 24 |
2867193000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1598457636 |
|
|
Jul 06 05:37:15 PM PDT 24 |
Jul 06 05:37:31 PM PDT 24 |
41649500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1939985012 |
|
|
Jul 06 05:37:43 PM PDT 24 |
Jul 06 05:37:57 PM PDT 24 |
30141000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2367635761 |
|
|
Jul 06 05:37:29 PM PDT 24 |
Jul 06 05:37:42 PM PDT 24 |
29425500 ps |
| T367 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.805632414 |
|
|
Jul 06 05:37:12 PM PDT 24 |
Jul 06 05:44:44 PM PDT 24 |
178722400 ps |
| T1187 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1952106822 |
|
|
Jul 06 05:36:34 PM PDT 24 |
Jul 06 05:36:48 PM PDT 24 |
67985800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3373995576 |
|
|
Jul 06 05:36:12 PM PDT 24 |
Jul 06 05:36:26 PM PDT 24 |
19774000 ps |
| T273 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3155381016 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:36:47 PM PDT 24 |
60678600 ps |
| T362 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3898857234 |
|
|
Jul 06 05:37:08 PM PDT 24 |
Jul 06 05:51:52 PM PDT 24 |
889137600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.43804704 |
|
|
Jul 06 05:36:17 PM PDT 24 |
Jul 06 05:36:49 PM PDT 24 |
226116200 ps |
| T1190 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.799314718 |
|
|
Jul 06 05:37:42 PM PDT 24 |
Jul 06 05:37:56 PM PDT 24 |
20863900 ps |
| T365 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3629383417 |
|
|
Jul 06 05:37:08 PM PDT 24 |
Jul 06 05:52:26 PM PDT 24 |
2772846500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2937817117 |
|
|
Jul 06 05:37:01 PM PDT 24 |
Jul 06 05:37:20 PM PDT 24 |
249922600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3487099758 |
|
|
Jul 06 05:36:36 PM PDT 24 |
Jul 06 05:36:54 PM PDT 24 |
43010700 ps |
| T1193 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.421132977 |
|
|
Jul 06 05:36:56 PM PDT 24 |
Jul 06 05:37:12 PM PDT 24 |
35640700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2222120528 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:38:23 PM PDT 24 |
15604389300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3287891996 |
|
|
Jul 06 05:37:29 PM PDT 24 |
Jul 06 05:37:45 PM PDT 24 |
17436300 ps |
| T1196 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3747345190 |
|
|
Jul 06 05:37:14 PM PDT 24 |
Jul 06 05:37:28 PM PDT 24 |
16476100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.506489818 |
|
|
Jul 06 05:37:24 PM PDT 24 |
Jul 06 05:37:38 PM PDT 24 |
17568100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.689310720 |
|
|
Jul 06 05:37:11 PM PDT 24 |
Jul 06 05:37:25 PM PDT 24 |
29415200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1939374425 |
|
|
Jul 06 05:37:39 PM PDT 24 |
Jul 06 05:37:53 PM PDT 24 |
32524800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2762837694 |
|
|
Jul 06 05:37:40 PM PDT 24 |
Jul 06 05:37:58 PM PDT 24 |
114944100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3660423641 |
|
|
Jul 06 05:36:17 PM PDT 24 |
Jul 06 05:36:32 PM PDT 24 |
24416200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2524762226 |
|
|
Jul 06 05:37:10 PM PDT 24 |
Jul 06 05:37:29 PM PDT 24 |
319442500 ps |
| T1203 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2027542625 |
|
|
Jul 06 05:36:26 PM PDT 24 |
Jul 06 05:37:13 PM PDT 24 |
52311800 ps |
| T1204 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2785990400 |
|
|
Jul 06 05:37:32 PM PDT 24 |
Jul 06 05:37:49 PM PDT 24 |
29624700 ps |
| T270 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.714074262 |
|
|
Jul 06 05:37:13 PM PDT 24 |
Jul 06 05:37:32 PM PDT 24 |
52365500 ps |
| T1205 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2111822217 |
|
|
Jul 06 05:36:51 PM PDT 24 |
Jul 06 05:37:07 PM PDT 24 |
25890300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.463453146 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:06 PM PDT 24 |
15186100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4058864430 |
|
|
Jul 06 05:36:10 PM PDT 24 |
Jul 06 05:36:56 PM PDT 24 |
43795200 ps |
| T1208 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1472186253 |
|
|
Jul 06 05:37:12 PM PDT 24 |
Jul 06 05:37:27 PM PDT 24 |
273057200 ps |
| T275 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1910682177 |
|
|
Jul 06 05:37:24 PM PDT 24 |
Jul 06 05:37:45 PM PDT 24 |
65474000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3177034232 |
|
|
Jul 06 05:36:17 PM PDT 24 |
Jul 06 05:36:33 PM PDT 24 |
38235800 ps |
| T1210 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.4176988162 |
|
|
Jul 06 05:36:51 PM PDT 24 |
Jul 06 05:37:11 PM PDT 24 |
50922300 ps |
| T1211 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4088153596 |
|
|
Jul 06 05:37:22 PM PDT 24 |
Jul 06 05:37:37 PM PDT 24 |
37873100 ps |
| T1212 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3314575283 |
|
|
Jul 06 05:37:28 PM PDT 24 |
Jul 06 05:37:45 PM PDT 24 |
124821100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.155845887 |
|
|
Jul 06 05:36:47 PM PDT 24 |
Jul 06 05:37:04 PM PDT 24 |
110178400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3328062321 |
|
|
Jul 06 05:37:17 PM PDT 24 |
Jul 06 05:37:35 PM PDT 24 |
188698600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2833931641 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:11 PM PDT 24 |
37264500 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.85766156 |
|
|
Jul 06 05:37:38 PM PDT 24 |
Jul 06 05:38:01 PM PDT 24 |
444226500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1871552587 |
|
|
Jul 06 05:37:47 PM PDT 24 |
Jul 06 05:38:01 PM PDT 24 |
14478400 ps |
| T360 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3042461879 |
|
|
Jul 06 05:36:57 PM PDT 24 |
Jul 06 05:52:01 PM PDT 24 |
1616432500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1343354139 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:14 PM PDT 24 |
11951000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2631944687 |
|
|
Jul 06 05:37:13 PM PDT 24 |
Jul 06 05:37:32 PM PDT 24 |
192245500 ps |
| T364 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.41487771 |
|
|
Jul 06 05:37:13 PM PDT 24 |
Jul 06 05:49:55 PM PDT 24 |
2336669000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.339594595 |
|
|
Jul 06 05:37:46 PM PDT 24 |
Jul 06 05:38:00 PM PDT 24 |
30594100 ps |
| T1221 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2259436749 |
|
|
Jul 06 05:36:48 PM PDT 24 |
Jul 06 05:37:03 PM PDT 24 |
36092500 ps |
| T1222 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.892465610 |
|
|
Jul 06 05:36:26 PM PDT 24 |
Jul 06 05:36:41 PM PDT 24 |
103282900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2716144074 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:36:45 PM PDT 24 |
153395400 ps |
| T1224 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.599155932 |
|
|
Jul 06 05:36:12 PM PDT 24 |
Jul 06 05:36:28 PM PDT 24 |
22494800 ps |
| T1225 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.18411515 |
|
|
Jul 06 05:36:27 PM PDT 24 |
Jul 06 05:36:41 PM PDT 24 |
18053300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1635842219 |
|
|
Jul 06 05:37:33 PM PDT 24 |
Jul 06 05:37:49 PM PDT 24 |
44841000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1270852466 |
|
|
Jul 06 05:37:46 PM PDT 24 |
Jul 06 05:38:00 PM PDT 24 |
158061600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3292005580 |
|
|
Jul 06 05:37:41 PM PDT 24 |
Jul 06 05:37:54 PM PDT 24 |
16676500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2783337959 |
|
|
Jul 06 05:37:47 PM PDT 24 |
Jul 06 05:38:01 PM PDT 24 |
27716600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3086063186 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:37:52 PM PDT 24 |
201403500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1798455879 |
|
|
Jul 06 05:37:08 PM PDT 24 |
Jul 06 05:37:24 PM PDT 24 |
35088200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2969991008 |
|
|
Jul 06 05:36:56 PM PDT 24 |
Jul 06 05:37:10 PM PDT 24 |
32364900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4208562342 |
|
|
Jul 06 05:36:37 PM PDT 24 |
Jul 06 05:36:54 PM PDT 24 |
73335700 ps |
| T1234 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2941238336 |
|
|
Jul 06 05:37:46 PM PDT 24 |
Jul 06 05:38:00 PM PDT 24 |
24322000 ps |
| T361 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2004391210 |
|
|
Jul 06 05:37:34 PM PDT 24 |
Jul 06 05:50:16 PM PDT 24 |
693908800 ps |
| T359 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3237179278 |
|
|
Jul 06 05:36:38 PM PDT 24 |
Jul 06 05:43:04 PM PDT 24 |
1557841500 ps |
| T1235 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1005458796 |
|
|
Jul 06 05:36:56 PM PDT 24 |
Jul 06 05:44:27 PM PDT 24 |
377673700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.285313298 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:13 PM PDT 24 |
17112500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2832925644 |
|
|
Jul 06 05:37:00 PM PDT 24 |
Jul 06 05:37:16 PM PDT 24 |
53737400 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.793718003 |
|
|
Jul 06 05:36:46 PM PDT 24 |
Jul 06 05:36:59 PM PDT 24 |
12541900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.336822299 |
|
|
Jul 06 05:37:43 PM PDT 24 |
Jul 06 05:37:57 PM PDT 24 |
28257700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.420534670 |
|
|
Jul 06 05:37:11 PM PDT 24 |
Jul 06 05:37:27 PM PDT 24 |
252448200 ps |
| T1241 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1623277460 |
|
|
Jul 06 05:36:58 PM PDT 24 |
Jul 06 05:37:16 PM PDT 24 |
203148000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2751276079 |
|
|
Jul 06 05:37:33 PM PDT 24 |
Jul 06 05:37:49 PM PDT 24 |
38441700 ps |
| T1243 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4089486161 |
|
|
Jul 06 05:37:51 PM PDT 24 |
Jul 06 05:38:05 PM PDT 24 |
74650700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3846998686 |
|
|
Jul 06 05:36:18 PM PDT 24 |
Jul 06 05:36:35 PM PDT 24 |
86822100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2080153249 |
|
|
Jul 06 05:36:37 PM PDT 24 |
Jul 06 05:37:13 PM PDT 24 |
918644700 ps |
| T277 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.740194037 |
|
|
Jul 06 05:36:47 PM PDT 24 |
Jul 06 05:44:31 PM PDT 24 |
408695000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3832817386 |
|
|
Jul 06 05:36:42 PM PDT 24 |
Jul 06 05:37:13 PM PDT 24 |
251938700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3028878613 |
|
|
Jul 06 05:36:13 PM PDT 24 |
Jul 06 05:36:29 PM PDT 24 |
38366400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4053430632 |
|
|
Jul 06 05:37:43 PM PDT 24 |
Jul 06 05:37:57 PM PDT 24 |
55022800 ps |
| T1249 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2727848009 |
|
|
Jul 06 05:37:10 PM PDT 24 |
Jul 06 05:37:24 PM PDT 24 |
113733400 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.320883339 |
|
|
Jul 06 05:36:38 PM PDT 24 |
Jul 06 05:36:52 PM PDT 24 |
17494700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2304535348 |
|
|
Jul 06 05:37:38 PM PDT 24 |
Jul 06 05:37:51 PM PDT 24 |
69469200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2140854493 |
|
|
Jul 06 05:37:48 PM PDT 24 |
Jul 06 05:38:03 PM PDT 24 |
57072900 ps |
| T1252 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3831134347 |
|
|
Jul 06 05:36:51 PM PDT 24 |
Jul 06 05:37:11 PM PDT 24 |
51510900 ps |