Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.67	93.95	98.31	92.52	98.19	96.89	98.18

Total test records in report: 1267

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1253	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2593986118			Jul 06 05:37:17 PM PDT 24	Jul 06 05:37:33 PM PDT 24	12541300 ps
T1254	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1221095629			Jul 06 05:36:14 PM PDT 24	Jul 06 05:36:32 PM PDT 24	114795200 ps
T1255	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2512099139			Jul 06 05:36:42 PM PDT 24	Jul 06 05:36:56 PM PDT 24	42437600 ps
T1256	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1209511682			Jul 06 05:37:14 PM PDT 24	Jul 06 05:37:27 PM PDT 24	53647500 ps
T1257	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.802627153			Jul 06 05:36:56 PM PDT 24	Jul 06 05:37:14 PM PDT 24	123867200 ps
T363	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.850289386			Jul 06 05:36:14 PM PDT 24	Jul 06 05:51:14 PM PDT 24	520535600 ps
T1258	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.641385872			Jul 06 05:37:46 PM PDT 24	Jul 06 05:38:00 PM PDT 24	30386500 ps
T1259	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3017245917			Jul 06 05:36:36 PM PDT 24	Jul 06 05:37:16 PM PDT 24	1277922300 ps
T1260	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4116526008			Jul 06 05:36:51 PM PDT 24	Jul 06 05:37:56 PM PDT 24	3825466800 ps
T253	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2548818586			Jul 06 05:36:08 PM PDT 24	Jul 06 05:36:21 PM PDT 24	16823600 ps
T1261	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4232718807			Jul 06 05:36:37 PM PDT 24	Jul 06 05:36:54 PM PDT 24	52821100 ps
T1262	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.760305938			Jul 06 05:36:52 PM PDT 24	Jul 06 05:37:28 PM PDT 24	329498700 ps
T1263	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3312429453			Jul 06 05:37:09 PM PDT 24	Jul 06 05:37:27 PM PDT 24	66166000 ps
T1264	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1883666486			Jul 06 05:36:46 PM PDT 24	Jul 06 05:37:10 PM PDT 24	3411293500 ps
T1265	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1921318008			Jul 06 05:36:13 PM PDT 24	Jul 06 05:36:58 PM PDT 24	9387276800 ps
T1266	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2167391460			Jul 06 05:36:52 PM PDT 24	Jul 06 05:37:09 PM PDT 24	333749900 ps
T1267	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2938610286			Jul 06 05:36:56 PM PDT 24	Jul 06 05:37:11 PM PDT 24	54302400 ps

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.3663002080
Short name	T6
Test name
Test status
Simulation time	70517200 ps
CPU time	369.46 seconds
Started	Jul 06 05:49:58 PM PDT 24
Finished	Jul 06 05:56:08 PM PDT 24
Peak memory	262996 kb
Host	smart-f8273be8-73c7-4dd5-97d9-328520554b87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3663002080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3663002080
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2909124433
Short name	T210
Test name
Test status
Simulation time	1578419300 ps
CPU time	898.7 seconds
Started	Jul 06 05:36:08 PM PDT 24
Finished	Jul 06 05:51:07 PM PDT 24
Peak memory	263628 kb
Host	smart-b45b6a90-b52a-40a6-af1f-0f3de342d649
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909124433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.2909124433
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.4012993857
Short name	T13
Test name
Test status
Simulation time	160170061900 ps
CPU time	878.1 seconds
Started	Jul 06 05:52:42 PM PDT 24
Finished	Jul 06 06:07:21 PM PDT 24
Peak memory	264112 kb
Host	smart-752e4880-4ffd-4cab-a3fc-4aec5829146a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012993857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.4012993857
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.4054318551
Short name	T34
Test name
Test status
Simulation time	9492382900 ps
CPU time	290.66 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	274336 kb
Host	smart-2a92ae0c-3662-4414-ab0d-5712ff7f06a8
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054318551 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.4054318551
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.117983582
Short name	T29
Test name
Test status
Simulation time	3158821100 ps
CPU time	198.45 seconds
Started	Jul 06 05:53:38 PM PDT 24
Finished	Jul 06 05:56:57 PM PDT 24
Peak memory	284948 kb
Host	smart-8867a4cc-ac21-4938-8703-05b3a0eada1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117983582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas h_ctrl_intr_rd.117983582
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.693681437
Short name	T18
Test name
Test status
Simulation time	1950118400 ps
CPU time	4624.77 seconds
Started	Jul 06 05:48:53 PM PDT 24
Finished	Jul 06 07:05:59 PM PDT 24
Peak memory	287500 kb
Host	smart-4222ab55-716a-41fd-bc39-64e3a1c94d6d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693681437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.693681437
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.1349426112
Short name	T54
Test name
Test status
Simulation time	8048473900 ps
CPU time	654.09 seconds
Started	Jul 06 05:51:06 PM PDT 24
Finished	Jul 06 06:02:00 PM PDT 24
Peak memory	337392 kb
Host	smart-e6c08dcb-f7f7-4f72-b8ee-ac76230e79bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349426112 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_rw_derr.1349426112
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.49593173
Short name	T61
Test name
Test status
Simulation time	2207441600 ps
CPU time	52.64 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:55:13 PM PDT 24
Peak memory	262784 kb
Host	smart-971c998d-75bd-4acd-8346-abaad96a40b6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49593173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw _sec_otp.49593173
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.3368007757
Short name	T167
Test name
Test status
Simulation time	8330420100 ps
CPU time	602.42 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:59:09 PM PDT 24
Peak memory	263436 kb
Host	smart-dbb42efb-f633-484a-8805-7995ec12d232
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3368007757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3368007757
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.545231299
Short name	T72
Test name
Test status
Simulation time	142420700 ps
CPU time	132.92 seconds
Started	Jul 06 05:53:25 PM PDT 24
Finished	Jul 06 05:55:38 PM PDT 24
Peak memory	260048 kb
Host	smart-46a5d06b-2560-46c0-b347-b71b05ddb5eb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545231299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot p_reset.545231299
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.329083886
Short name	T116
Test name
Test status
Simulation time	340432500 ps
CPU time	753.33 seconds
Started	Jul 06 05:36:37 PM PDT 24
Finished	Jul 06 05:49:10 PM PDT 24
Peak memory	263716 kb
Host	smart-be27154d-ac8d-4338-b2c3-b05f107ab1c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329083886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ tl_intg_err.329083886
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.375577850
Short name	T97
Test name
Test status
Simulation time	1645128300 ps
CPU time	70.54 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:49:59 PM PDT 24
Peak memory	260708 kb
Host	smart-a72cb86a-7d19-473d-9153-9f94ec073cc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375577850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.375577850
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.1632854870
Short name	T191
Test name
Test status
Simulation time	61327500 ps
CPU time	133.09 seconds
Started	Jul 06 05:55:43 PM PDT 24
Finished	Jul 06 05:57:57 PM PDT 24
Peak memory	261152 kb
Host	smart-ee680c0b-ba14-406c-be89-1e5f0abc2f36
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632854870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.1632854870
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.842569532
Short name	T26
Test name
Test status
Simulation time	81635161300 ps
CPU time	170.66 seconds
Started	Jul 06 05:52:48 PM PDT 24
Finished	Jul 06 05:55:39 PM PDT 24
Peak memory	293048 kb
Host	smart-b3caffff-d1ec-41d1-9fe1-fa159697a6f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842569532 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.842569532
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2894070710
Short name	T244
Test name
Test status
Simulation time	127757300 ps
CPU time	18.73 seconds
Started	Jul 06 05:36:32 PM PDT 24
Finished	Jul 06 05:36:51 PM PDT 24
Peak memory	263676 kb
Host	smart-d9187354-6aec-4f50-ab4b-41a999207421
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894070710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2 894070710
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2257220645
Short name	T14
Test name
Test status
Simulation time	14951400 ps
CPU time	13.92 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 05:50:14 PM PDT 24
Peak memory	265504 kb
Host	smart-6577324d-ef8b-42db-80f7-79236179df57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257220645 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2257220645
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.357820572
Short name	T91
Test name
Test status
Simulation time	10037538000 ps
CPU time	98.97 seconds
Started	Jul 06 05:51:49 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	272376 kb
Host	smart-8de40e5d-eba6-46c8-ae22-964ec10aa192
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357820572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.357820572
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2415827550
Short name	T319
Test name
Test status
Simulation time	17556100 ps
CPU time	13.76 seconds
Started	Jul 06 05:36:13 PM PDT 24
Finished	Jul 06 05:36:27 PM PDT 24
Peak memory	261116 kb
Host	smart-d0451ee3-d294-49fe-a122-a4c219514e92
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415827550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2 415827550
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.1658765331
Short name	T2
Test name
Test status
Simulation time	40597500 ps
CPU time	13.41 seconds
Started	Jul 06 05:52:36 PM PDT 24
Finished	Jul 06 05:52:49 PM PDT 24
Peak memory	258392 kb
Host	smart-8f50edd9-52e6-4e41-b868-26f36d84640a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658765331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 1658765331
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.3581571211
Short name	T71
Test name
Test status
Simulation time	38431800 ps
CPU time	112 seconds
Started	Jul 06 05:55:11 PM PDT 24
Finished	Jul 06 05:57:04 PM PDT 24
Peak memory	264900 kb
Host	smart-9f5b0a60-7a42-4dc1-b6fd-ae81746c446c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581571211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.3581571211
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2444168983
Short name	T86
Test name
Test status
Simulation time	518200656400 ps
CPU time	1813.61 seconds
Started	Jul 06 05:49:05 PM PDT 24
Finished	Jul 06 06:19:19 PM PDT 24
Peak memory	264352 kb
Host	smart-f964c9ef-5a5f-40bb-940e-16c7894e4956
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444168983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.2444168983
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.1579900606
Short name	T9
Test name
Test status
Simulation time	49233400 ps
CPU time	15.12 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 05:49:20 PM PDT 24
Peak memory	261036 kb
Host	smart-97afa949-a532-4b6b-a08c-11024cd0cecb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579900606 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1579900606
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.489203157
Short name	T50
Test name
Test status
Simulation time	16161078200 ps
CPU time	64.66 seconds
Started	Jul 06 05:54:49 PM PDT 24
Finished	Jul 06 05:55:54 PM PDT 24
Peak memory	263680 kb
Host	smart-b3edfae8-7e1c-4128-af79-f85e2d086e91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489203157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.489203157
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.1933006951
Short name	T184
Test name
Test status
Simulation time	72997700 ps
CPU time	136.54 seconds
Started	Jul 06 05:55:39 PM PDT 24
Finished	Jul 06 05:57:56 PM PDT 24
Peak memory	260152 kb
Host	smart-a6bbe873-bea9-4fee-b4a4-bbb8b66dc2fe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933006951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.1933006951
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.574721850
Short name	T55
Test name
Test status
Simulation time	1249081300 ps
CPU time	22.48 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 05:49:27 PM PDT 24
Peak memory	262528 kb
Host	smart-aedc8a66-2f8e-48d1-9cc9-43f101ee6e5e
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574721850 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.574721850
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.383557579
Short name	T69
Test name
Test status
Simulation time	5989360500 ps
CPU time	420.46 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:55:58 PM PDT 24
Peak memory	274256 kb
Host	smart-f39c4139-8c8c-4c83-b1c6-a65097c50462
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383557579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.383557579
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.1854096446
Short name	T190
Test name
Test status
Simulation time	80591621500 ps
CPU time	921.45 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 06:04:19 PM PDT 24
Peak memory	263756 kb
Host	smart-c02cc31c-6c13-4975-a2ec-23acc38bb715
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854096446 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1854096446
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.4101671799
Short name	T174
Test name
Test status
Simulation time	42599400 ps
CPU time	13.75 seconds
Started	Jul 06 05:49:21 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	262524 kb
Host	smart-2f30a76e-68a9-4c07-83b8-d846df8894e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101671799 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.4101671799
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.2094242684
Short name	T98
Test name
Test status
Simulation time	4857815300 ps
CPU time	75.63 seconds
Started	Jul 06 05:49:17 PM PDT 24
Finished	Jul 06 05:50:33 PM PDT 24
Peak memory	260576 kb
Host	smart-0e47b412-fec4-4780-81c2-b13f41ed07ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094242684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2094242684
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.3966529262
Short name	T58
Test name
Test status
Simulation time	10456802400 ps
CPU time	549.24 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:58:11 PM PDT 24
Peak memory	314496 kb
Host	smart-1d23bf50-bff5-4f1a-9938-4b7a2a9c2731
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966529262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.flash_ctrl_rw.3966529262
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.2718256596
Short name	T28
Test name
Test status
Simulation time	29695100 ps
CPU time	30.78 seconds
Started	Jul 06 05:53:34 PM PDT 24
Finished	Jul 06 05:54:05 PM PDT 24
Peak memory	268512 kb
Host	smart-f1d3b2a9-7f3c-4734-8c34-9713ab04060c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718256596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.2718256596
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.501741913
Short name	T266
Test name
Test status
Simulation time	116059900 ps
CPU time	19.39 seconds
Started	Jul 06 05:37:00 PM PDT 24
Finished	Jul 06 05:37:20 PM PDT 24
Peak memory	263712 kb
Host	smart-d13cb4e5-01c7-49fa-8d4d-23e5cc2a5059
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501741913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.501741913
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.1220225583
Short name	T4
Test name
Test status
Simulation time	4025168300 ps
CPU time	73.76 seconds
Started	Jul 06 05:52:11 PM PDT 24
Finished	Jul 06 05:53:25 PM PDT 24
Peak memory	260816 kb
Host	smart-413062c7-96c7-45b9-804e-71521ddf052e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220225583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1 220225583
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.2085093031
Short name	T16
Test name
Test status
Simulation time	3798878200 ps
CPU time	4747.25 seconds
Started	Jul 06 05:49:21 PM PDT 24
Finished	Jul 06 07:08:29 PM PDT 24
Peak memory	287792 kb
Host	smart-08227a51-33f0-49de-b2f6-58ba7b3a618b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085093031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2085093031
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.1101680683
Short name	T322
Test name
Test status
Simulation time	804347900 ps
CPU time	175.69 seconds
Started	Jul 06 05:54:59 PM PDT 24
Finished	Jul 06 05:57:55 PM PDT 24
Peak memory	293384 kb
Host	smart-a06f65f5-f62d-4bf7-946b-bf581621e424
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101680683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.1101680683
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.4144511331
Short name	T179
Test name
Test status
Simulation time	67018400 ps
CPU time	13.56 seconds
Started	Jul 06 05:51:25 PM PDT 24
Finished	Jul 06 05:51:39 PM PDT 24
Peak memory	259988 kb
Host	smart-bd11d108-0b76-40dd-8605-918469a40c9b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144511331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.4144511331
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.1004979565
Short name	T337
Test name
Test status
Simulation time	67967500 ps
CPU time	34.08 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:49:54 PM PDT 24
Peak memory	270024 kb
Host	smart-3c8412ea-a89e-4d3f-a942-6c10c75c98a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004979565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.1004979565
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2548818586
Short name	T253
Test name
Test status
Simulation time	16823600 ps
CPU time	13.61 seconds
Started	Jul 06 05:36:08 PM PDT 24
Finished	Jul 06 05:36:21 PM PDT 24
Peak memory	262992 kb
Host	smart-57e9eeed-53c5-41f6-b593-62cc8fdeca6a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548818586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.2548818586
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.2206110017
Short name	T101
Test name
Test status
Simulation time	2447457300 ps
CPU time	143.56 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:51:14 PM PDT 24
Peak memory	281764 kb
Host	smart-dade9ef5-ccb9-45a7-a4f6-2ca0ea1dcf9b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206110017 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2206110017
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3716326186
Short name	T204
Test name
Test status
Simulation time	10012480000 ps
CPU time	143.88 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:51:34 PM PDT 24
Peak memory	385640 kb
Host	smart-4ce87a12-12bb-4b5a-b96b-3e633d2a79a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716326186 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3716326186
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2602591019
Short name	T272
Test name
Test status
Simulation time	5563088300 ps
CPU time	897.29 seconds
Started	Jul 06 05:37:16 PM PDT 24
Finished	Jul 06 05:52:13 PM PDT 24
Peak memory	263764 kb
Host	smart-205e4dc6-1ee3-448f-b41a-98625fc27bfb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602591019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr l_tl_intg_err.2602591019
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3841468960
Short name	T264
Test name
Test status
Simulation time	15701800 ps
CPU time	14.44 seconds
Started	Jul 06 05:37:36 PM PDT 24
Finished	Jul 06 05:37:51 PM PDT 24
Peak memory	261096 kb
Host	smart-c1f83695-b898-475a-a3de-9c78c0587874
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841468960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 3841468960
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.2817907962
Short name	T137
Test name
Test status
Simulation time	4289747400 ps
CPU time	708.94 seconds
Started	Jul 06 05:49:00 PM PDT 24
Finished	Jul 06 06:00:49 PM PDT 24
Peak memory	326248 kb
Host	smart-024e09ea-7543-459f-9021-af56ca29d808
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817907962 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_integrity.2817907962
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1113551997
Short name	T715
Test name
Test status
Simulation time	44992700 ps
CPU time	13.23 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:52:28 PM PDT 24
Peak memory	259936 kb
Host	smart-eb375762-5633-46fb-86c4-0673b3591336
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113551997 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1113551997
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.3205365280
Short name	T387
Test name
Test status
Simulation time	503453400 ps
CPU time	59.17 seconds
Started	Jul 06 05:54:01 PM PDT 24
Finished	Jul 06 05:55:01 PM PDT 24
Peak memory	263752 kb
Host	smart-f25c4ca6-f353-4fbe-94fa-e51d23dece0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205365280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3205365280
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.4236224281
Short name	T229
Test name
Test status
Simulation time	92688000 ps
CPU time	13.77 seconds
Started	Jul 06 05:49:21 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	261804 kb
Host	smart-3defd3ef-180e-4cfd-b229-d5d0513f0e5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4236224281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.4236224281
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.4087398819
Short name	T301
Test name
Test status
Simulation time	114582300 ps
CPU time	17.74 seconds
Started	Jul 06 05:37:23 PM PDT 24
Finished	Jul 06 05:37:41 PM PDT 24
Peak memory	270356 kb
Host	smart-86f93001-674d-496e-ba3c-cc6516af6c0b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087398819 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.4087398819
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.99812396
Short name	T80
Test name
Test status
Simulation time	765024000 ps
CPU time	26.43 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	263084 kb
Host	smart-0866520b-7f28-49f8-8979-dcc1d984768e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99812396 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.99812396
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.985778044
Short name	T113
Test name
Test status
Simulation time	25885200 ps
CPU time	16.07 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:55:53 PM PDT 24
Peak memory	274868 kb
Host	smart-6e3bd089-4774-4523-b1ae-a1a924b7099d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985778044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.985778044
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.555455534
Short name	T332
Test name
Test status
Simulation time	17892766700 ps
CPU time	236.02 seconds
Started	Jul 06 05:51:34 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	292900 kb
Host	smart-070ed02b-3e93-4399-956e-31450a725973
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555455534 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.555455534
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.1680355128
Short name	T49
Test name
Test status
Simulation time	618004400 ps
CPU time	1380.99 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 06:11:59 PM PDT 24
Peak memory	288120 kb
Host	smart-7258ae05-5e5e-4f7f-8a7e-a09ba419fd08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680355128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1680355128
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.3757414437
Short name	T371
Test name
Test status
Simulation time	33026800 ps
CPU time	21.87 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:52:38 PM PDT 24
Peak memory	273612 kb
Host	smart-8bc8c135-3ba3-4577-a68d-f659ce3679ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757414437 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.3757414437
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.3482748636
Short name	T122
Test name
Test status
Simulation time	334248351400 ps
CPU time	2032.02 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 06:22:50 PM PDT 24
Peak memory	260832 kb
Host	smart-385076b3-2f3f-4c20-a082-e1b904755bf5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482748636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.3482748636
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3957759167
Short name	T238
Test name
Test status
Simulation time	685307800 ps
CPU time	457.07 seconds
Started	Jul 06 05:37:14 PM PDT 24
Finished	Jul 06 05:44:52 PM PDT 24
Peak memory	263760 kb
Host	smart-498bf61d-2349-48ec-b82b-11162705f079
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957759167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.3957759167
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3042461879
Short name	T360
Test name
Test status
Simulation time	1616432500 ps
CPU time	903.26 seconds
Started	Jul 06 05:36:57 PM PDT 24
Finished	Jul 06 05:52:01 PM PDT 24
Peak memory	263740 kb
Host	smart-a378b518-21f8-459c-8940-761618a5f5d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042461879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.3042461879
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1524510236
Short name	T635
Test name
Test status
Simulation time	34407400 ps
CPU time	13.4 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:49:11 PM PDT 24
Peak memory	265340 kb
Host	smart-f04604c4-1ef6-46ce-a456-2e58451f3c80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524510236 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1524510236
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.4026361490
Short name	T338
Test name
Test status
Simulation time	108065700 ps
CPU time	33.58 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	270332 kb
Host	smart-19e05bba-4287-45e4-a996-ab96fd536c66
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026361490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.4026361490
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.1103447383
Short name	T863
Test name
Test status
Simulation time	15323488700 ps
CPU time	659.75 seconds
Started	Jul 06 05:50:03 PM PDT 24
Finished	Jul 06 06:01:03 PM PDT 24
Peak memory	314304 kb
Host	smart-e68f52b0-6dea-4c2e-8e10-8f0f358eef73
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103447383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.1103447383
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3960963383
Short name	T215
Test name
Test status
Simulation time	17874600 ps
CPU time	13.9 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:23 PM PDT 24
Peak memory	262532 kb
Host	smart-8f3f323b-ba02-4793-9c37-69b3824bea3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960963383 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3960963383
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.2301404420
Short name	T1035
Test name
Test status
Simulation time	1304537600 ps
CPU time	2451.17 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 06:29:38 PM PDT 24
Peak memory	264644 kb
Host	smart-a2c8e9ba-93f1-4477-9814-a29f4d35c30e
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301404420 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2301404420
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.1745200943
Short name	T292
Test name
Test status
Simulation time	447142700 ps
CPU time	1050.24 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 06:06:33 PM PDT 24
Peak memory	273420 kb
Host	smart-59224816-a970-4516-bb99-a5ac17252b05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745200943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1745200943
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3536337556
Short name	T66
Test name
Test status
Simulation time	489184500 ps
CPU time	465.88 seconds
Started	Jul 06 05:37:27 PM PDT 24
Finished	Jul 06 05:45:13 PM PDT 24
Peak memory	263748 kb
Host	smart-5b06e597-6ab9-4513-9efe-25d7dc4003e0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536337556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.3536337556
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2026922357
Short name	T282
Test name
Test status
Simulation time	32432500 ps
CPU time	31.03 seconds
Started	Jul 06 05:51:20 PM PDT 24
Finished	Jul 06 05:51:51 PM PDT 24
Peak memory	268500 kb
Host	smart-cc06c735-dcec-4e30-b92a-5744e529c830
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026922357 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2026922357
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.4188585244
Short name	T211
Test name
Test status
Simulation time	1445273800 ps
CPU time	136.43 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 05:52:45 PM PDT 24
Peak memory	281880 kb
Host	smart-925b6f7e-6104-41cb-9e99-935d08fdb1bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4188585244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.4188585244
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1200925496
Short name	T289
Test name
Test status
Simulation time	10126788200 ps
CPU time	32.04 seconds
Started	Jul 06 05:51:29 PM PDT 24
Finished	Jul 06 05:52:02 PM PDT 24
Peak memory	263580 kb
Host	smart-eb1512b6-0240-40a9-8b26-3a26c21fa9c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200925496 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1200925496
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2185070997
Short name	T285
Test name
Test status
Simulation time	15413100 ps
CPU time	13.38 seconds
Started	Jul 06 05:51:46 PM PDT 24
Finished	Jul 06 05:52:00 PM PDT 24
Peak memory	258660 kb
Host	smart-2300379c-f911-4e2d-96f3-27f083bbc023
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185070997 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2185070997
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.3571086069
Short name	T393
Test name
Test status
Simulation time	3304861100 ps
CPU time	76.04 seconds
Started	Jul 06 05:51:50 PM PDT 24
Finished	Jul 06 05:53:06 PM PDT 24
Peak memory	263708 kb
Host	smart-363b9987-32cf-4be2-8565-346723bb4dc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3571086069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3571086069
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.3922773431
Short name	T334
Test name
Test status
Simulation time	50266800 ps
CPU time	28.79 seconds
Started	Jul 06 05:52:59 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	268488 kb
Host	smart-9e3b9579-00d2-46fa-abb3-6f436564635c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922773431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.3922773431
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.2195989751
Short name	T406
Test name
Test status
Simulation time	447847100 ps
CPU time	49.26 seconds
Started	Jul 06 05:55:08 PM PDT 24
Finished	Jul 06 05:55:57 PM PDT 24
Peak memory	263780 kb
Host	smart-a676ff0d-d6b5-45b1-90a3-870c19445169
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195989751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2195989751
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.947006892
Short name	T404
Test name
Test status
Simulation time	2751297400 ps
CPU time	72.56 seconds
Started	Jul 06 05:50:42 PM PDT 24
Finished	Jul 06 05:51:55 PM PDT 24
Peak memory	263748 kb
Host	smart-89be4573-1fe8-4b47-85b1-0f0854507a23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947006892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.947006892
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.2602560932
Short name	T25
Test name
Test status
Simulation time	27224300 ps
CPU time	14.23 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:49:05 PM PDT 24
Peak memory	261356 kb
Host	smart-14d1e86e-1ab4-4f76-b701-87072b27d2d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602560932 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2602560932
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.1845059569
Short name	T372
Test name
Test status
Simulation time	23513400 ps
CPU time	22.17 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 05:53:01 PM PDT 24
Peak memory	273584 kb
Host	smart-e8b7eb25-3058-42f4-8d38-3a7d7ccf561e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845059569 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.1845059569
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.3099507332
Short name	T864
Test name
Test status
Simulation time	104266200 ps
CPU time	13.61 seconds
Started	Jul 06 05:49:11 PM PDT 24
Finished	Jul 06 05:49:25 PM PDT 24
Peak memory	265056 kb
Host	smart-787e4b6a-2e7f-425b-b5eb-2de642805fe7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099507332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.3099507332
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.1805706100
Short name	T333
Test name
Test status
Simulation time	77648500 ps
CPU time	28.34 seconds
Started	Jul 06 05:54:42 PM PDT 24
Finished	Jul 06 05:55:11 PM PDT 24
Peak memory	268468 kb
Host	smart-d443baf1-e74e-44c9-9c5f-484a67b0a524
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805706100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl ash_ctrl_rw_evict.1805706100
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1180991860
Short name	T262
Test name
Test status
Simulation time	39179300 ps
CPU time	16.38 seconds
Started	Jul 06 05:36:11 PM PDT 24
Finished	Jul 06 05:36:27 PM PDT 24
Peak memory	263716 kb
Host	smart-fe4e6520-f000-4525-82fd-8cd7382c675b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180991860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1 180991860
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2112450041
Short name	T76
Test name
Test status
Simulation time	883168700 ps
CPU time	16.38 seconds
Started	Jul 06 05:48:51 PM PDT 24
Finished	Jul 06 05:49:08 PM PDT 24
Peak memory	263224 kb
Host	smart-3ddf9abd-ae2d-47f2-92e3-48a76aa595ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112450041 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2112450041
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.509896093
Short name	T78
Test name
Test status
Simulation time	864573200 ps
CPU time	19.17 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	264396 kb
Host	smart-74f4549b-d263-443a-b0ba-fc78c60e0a80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509896093 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.509896093
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.510184974
Short name	T31
Test name
Test status
Simulation time	150140725500 ps
CPU time	302.8 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:55:54 PM PDT 24
Peak memory	265328 kb
Host	smart-a800e670-a80f-451d-8f47-ae234a19a2e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510 184974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.510184974
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.616122761
Short name	T1148
Test name
Test status
Simulation time	77962200 ps
CPU time	13.58 seconds
Started	Jul 06 05:37:17 PM PDT 24
Finished	Jul 06 05:37:30 PM PDT 24
Peak memory	261212 kb
Host	smart-a2da2c77-1084-4df6-88f9-07fb5f2566a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616122761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.616122761
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.4114492026
Short name	T917
Test name
Test status
Simulation time	12969500 ps
CPU time	20.89 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:49:11 PM PDT 24
Peak memory	273616 kb
Host	smart-40829361-e802-421d-9356-8b6ec2cd8cf0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114492026 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.4114492026
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.1688545471
Short name	T162
Test name
Test status
Simulation time	6439123000 ps
CPU time	68.39 seconds
Started	Jul 06 05:49:03 PM PDT 24
Finished	Jul 06 05:50:11 PM PDT 24
Peak memory	260504 kb
Host	smart-707c83e0-d091-4812-ba80-91cab1540150
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688545471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1688545471
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.3267319061
Short name	T930
Test name
Test status
Simulation time	12406600 ps
CPU time	21.01 seconds
Started	Jul 06 05:51:39 PM PDT 24
Finished	Jul 06 05:52:00 PM PDT 24
Peak memory	265480 kb
Host	smart-0261ff38-390e-45bd-be03-23bfbb695236
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267319061 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.3267319061
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2559384336
Short name	T354
Test name
Test status
Simulation time	82091200 ps
CPU time	32.03 seconds
Started	Jul 06 05:51:42 PM PDT 24
Finished	Jul 06 05:52:15 PM PDT 24
Peak memory	275688 kb
Host	smart-16b8f340-8b66-4772-84fc-ccfab33bd748
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559384336 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2559384336
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.2734451318
Short name	T879
Test name
Test status
Simulation time	17765800 ps
CPU time	21.82 seconds
Started	Jul 06 05:52:07 PM PDT 24
Finished	Jul 06 05:52:29 PM PDT 24
Peak memory	273560 kb
Host	smart-4057d7bc-0528-4793-8385-d7bae0a28846
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734451318 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.2734451318
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.178568637
Short name	T351
Test name
Test status
Simulation time	44648700 ps
CPU time	31.79 seconds
Started	Jul 06 05:52:16 PM PDT 24
Finished	Jul 06 05:52:48 PM PDT 24
Peak memory	268432 kb
Host	smart-b17cf1f9-81e8-4ebd-853a-573345a85d19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178568637 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.178568637
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.3079691695
Short name	T1110
Test name
Test status
Simulation time	14954600 ps
CPU time	20.47 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:53:30 PM PDT 24
Peak memory	273552 kb
Host	smart-77152444-fcfd-4572-b722-63ff31ee0aca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079691695 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.3079691695
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.3226954041
Short name	T869
Test name
Test status
Simulation time	1957575000 ps
CPU time	72.76 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:54:45 PM PDT 24
Peak memory	264724 kb
Host	smart-f2b0c31d-72f3-44ac-8f81-9e9c3969ad08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226954041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3226954041
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.2397372023
Short name	T110
Test name
Test status
Simulation time	15192600 ps
CPU time	20.7 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:54:08 PM PDT 24
Peak memory	273592 kb
Host	smart-27297386-774e-4959-a7ce-0b3fbd0de992
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397372023 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.2397372023
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.1158719026
Short name	T342
Test name
Test status
Simulation time	54274200 ps
CPU time	29.94 seconds
Started	Jul 06 05:54:39 PM PDT 24
Finished	Jul 06 05:55:09 PM PDT 24
Peak memory	275596 kb
Host	smart-c463dd8f-0fa6-4c0c-9aca-35c714d8893b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158719026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.1158719026
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.4012737579
Short name	T108
Test name
Test status
Simulation time	10174000 ps
CPU time	20.68 seconds
Started	Jul 06 05:55:19 PM PDT 24
Finished	Jul 06 05:55:40 PM PDT 24
Peak memory	273528 kb
Host	smart-e581874e-fa6a-4bce-85b3-de434f6a1ee2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012737579 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.4012737579
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.1036587849
Short name	T401
Test name
Test status
Simulation time	2391859900 ps
CPU time	64.02 seconds
Started	Jul 06 05:50:10 PM PDT 24
Finished	Jul 06 05:51:14 PM PDT 24
Peak memory	263708 kb
Host	smart-578f231a-55c7-4c1a-be1b-3e9a04715465
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1036587849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1036587849
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.439172460
Short name	T189
Test name
Test status
Simulation time	160173398100 ps
CPU time	866.32 seconds
Started	Jul 06 05:51:45 PM PDT 24
Finished	Jul 06 06:06:12 PM PDT 24
Peak memory	264276 kb
Host	smart-e14c9e6a-1e92-4fde-8eb1-d8a646653d15
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439172460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.flash_ctrl_hw_rma_reset.439172460
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.2818613226
Short name	T136
Test name
Test status
Simulation time	9400643900 ps
CPU time	685.24 seconds
Started	Jul 06 05:49:11 PM PDT 24
Finished	Jul 06 06:00:37 PM PDT 24
Peak memory	333588 kb
Host	smart-9f8068d6-4c59-48be-a45b-c65e35ff1120
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818613226 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_rw_derr.2818613226
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_derr.1432376036
Short name	T147
Test name
Test status
Simulation time	4904426700 ps
CPU time	548.25 seconds
Started	Jul 06 05:49:55 PM PDT 24
Finished	Jul 06 05:59:03 PM PDT 24
Peak memory	315612 kb
Host	smart-67f320b2-26fc-4cfd-a05d-fa851ab26979
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432376036 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_rw_derr.1432376036
Directory	/workspace/4.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.2917962364
Short name	T227
Test name
Test status
Simulation time	60241800 ps
CPU time	97.37 seconds
Started	Jul 06 05:48:45 PM PDT 24
Finished	Jul 06 05:50:22 PM PDT 24
Peak memory	262644 kb
Host	smart-65475dc8-f7da-4e7e-a061-cd17faf34a82
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2917962364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2917962364
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.136666345
Short name	T882
Test name
Test status
Simulation time	7384437800 ps
CPU time	583.73 seconds
Started	Jul 06 05:51:50 PM PDT 24
Finished	Jul 06 06:01:34 PM PDT 24
Peak memory	309548 kb
Host	smart-36819d34-7bcb-4d34-9571-88b6a84465bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136666345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.136666345
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.4067336058
Short name	T96
Test name
Test status
Simulation time	25278680100 ps
CPU time	451.41 seconds
Started	Jul 06 05:54:14 PM PDT 24
Finished	Jul 06 06:01:46 PM PDT 24
Peak memory	293984 kb
Host	smart-89e8b7fc-7c5c-4273-b481-763ba2321f6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067336058 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.4067336058
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.740194037
Short name	T277
Test name
Test status
Simulation time	408695000 ps
CPU time	463.61 seconds
Started	Jul 06 05:36:47 PM PDT 24
Finished	Jul 06 05:44:31 PM PDT 24
Peak memory	263760 kb
Host	smart-72942c2d-fa3b-4a83-aac9-85f38e8b627c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740194037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ tl_intg_err.740194037
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.2402936556
Short name	T23
Test name
Test status
Simulation time	3435233700 ps
CPU time	2146.05 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 06:24:35 PM PDT 24
Peak memory	262788 kb
Host	smart-c94bbd4a-23bc-4a3d-bf4a-2397a7322f3d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2402936556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.2402936556
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.3192409877
Short name	T978
Test name
Test status
Simulation time	91550362200 ps
CPU time	2427.22 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 06:29:18 PM PDT 24
Peak memory	265336 kb
Host	smart-40e6dd90-865e-4fa9-8578-289d241f3986
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192409877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.3192409877
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.289728399
Short name	T100
Test name
Test status
Simulation time	200658500 ps
CPU time	15.25 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:49:12 PM PDT 24
Peak memory	265104 kb
Host	smart-1eb0dfc3-fb9b-4f16-abeb-871860dfb769
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289728399 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.289728399
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3068513419
Short name	T214
Test name
Test status
Simulation time	298236680400 ps
CPU time	3029.76 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 06:39:49 PM PDT 24
Peak memory	264988 kb
Host	smart-70f09b9e-caff-4273-947e-d2e33a859d4d
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068513419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.3068513419
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.2660224823
Short name	T213
Test name
Test status
Simulation time	508236822300 ps
CPU time	1861.85 seconds
Started	Jul 06 05:49:33 PM PDT 24
Finished	Jul 06 06:20:36 PM PDT 24
Peak memory	265340 kb
Host	smart-83f6185c-1fd3-4315-be5e-08107a2c04c3
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660224823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.2660224823
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1921318008
Short name	T1265
Test name
Test status
Simulation time	9387276800 ps
CPU time	44.51 seconds
Started	Jul 06 05:36:13 PM PDT 24
Finished	Jul 06 05:36:58 PM PDT 24
Peak memory	261364 kb
Host	smart-12d36bbf-113d-4141-932a-6503e59c2b59
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921318008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.1921318008
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2005876661
Short name	T315
Test name
Test status
Simulation time	9101111800 ps
CPU time	83.02 seconds
Started	Jul 06 05:36:13 PM PDT 24
Finished	Jul 06 05:37:36 PM PDT 24
Peak memory	261232 kb
Host	smart-688fbbe0-fef9-48cc-b2a0-b2947b95fb5c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005876661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.2005876661
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4058864430
Short name	T1207
Test name
Test status
Simulation time	43795200 ps
CPU time	46.04 seconds
Started	Jul 06 05:36:10 PM PDT 24
Finished	Jul 06 05:36:56 PM PDT 24
Peak memory	263380 kb
Host	smart-775f1f48-aec1-420f-8e31-bb00ec51e163
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058864430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.4058864430
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1842051908
Short name	T1172
Test name
Test status
Simulation time	49812600 ps
CPU time	17.41 seconds
Started	Jul 06 05:36:15 PM PDT 24
Finished	Jul 06 05:36:33 PM PDT 24
Peak memory	270528 kb
Host	smart-3379b093-cc20-42ca-993f-be1930651854
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842051908 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1842051908
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1221095629
Short name	T1254
Test name
Test status
Simulation time	114795200 ps
CPU time	17.53 seconds
Started	Jul 06 05:36:14 PM PDT 24
Finished	Jul 06 05:36:32 PM PDT 24
Peak memory	261260 kb
Host	smart-496d2cbc-c241-43e5-a742-622aac93deab
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221095629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1221095629
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3589597981
Short name	T1133
Test name
Test status
Simulation time	29126200 ps
CPU time	13.8 seconds
Started	Jul 06 05:36:12 PM PDT 24
Finished	Jul 06 05:36:26 PM PDT 24
Peak memory	261196 kb
Host	smart-56097554-cbc2-4eda-84ac-aa830e40f297
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589597981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.3589597981
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.43804704
Short name	T1189
Test name
Test status
Simulation time	226116200 ps
CPU time	31.48 seconds
Started	Jul 06 05:36:17 PM PDT 24
Finished	Jul 06 05:36:49 PM PDT 24
Peak memory	262432 kb
Host	smart-c7013568-85bc-4d2f-b74f-56ca8dc8746a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43804704 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.43804704
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3373995576
Short name	T1188
Test name
Test status
Simulation time	19774000 ps
CPU time	13.33 seconds
Started	Jul 06 05:36:12 PM PDT 24
Finished	Jul 06 05:36:26 PM PDT 24
Peak memory	252960 kb
Host	smart-6c683d2f-10e7-480b-93c8-9b18e363840a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373995576 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3373995576
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.599155932
Short name	T1224
Test name
Test status
Simulation time	22494800 ps
CPU time	15.82 seconds
Started	Jul 06 05:36:12 PM PDT 24
Finished	Jul 06 05:36:28 PM PDT 24
Peak memory	253092 kb
Host	smart-537542fc-2d15-4b19-a881-9ff3a74f02df
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599155932 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.599155932
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3917859371
Short name	T305
Test name
Test status
Simulation time	8397618000 ps
CPU time	69.22 seconds
Started	Jul 06 05:36:18 PM PDT 24
Finished	Jul 06 05:37:28 PM PDT 24
Peak memory	261292 kb
Host	smart-c93dedd5-6d3d-4418-aa3f-6aae18b23b2b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917859371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.3917859371
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2308696994
Short name	T415
Test name
Test status
Simulation time	2196402600 ps
CPU time	81.05 seconds
Started	Jul 06 05:36:19 PM PDT 24
Finished	Jul 06 05:37:40 PM PDT 24
Peak memory	261264 kb
Host	smart-f120bb78-97d6-4221-9a0e-6c84f4ad9c8a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308696994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.2308696994
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1597824958
Short name	T1146
Test name
Test status
Simulation time	97026000 ps
CPU time	31.97 seconds
Started	Jul 06 05:36:18 PM PDT 24
Finished	Jul 06 05:36:50 PM PDT 24
Peak memory	261212 kb
Host	smart-7998ff94-1547-4f20-a4af-d2346b105115
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597824958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.1597824958
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.833522260
Short name	T1173
Test name
Test status
Simulation time	38279300 ps
CPU time	17.68 seconds
Started	Jul 06 05:36:22 PM PDT 24
Finished	Jul 06 05:36:39 PM PDT 24
Peak memory	272020 kb
Host	smart-3ba747d1-98c4-466e-962a-75bbdc8800b4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833522260 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.833522260
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3846998686
Short name	T1244
Test name
Test status
Simulation time	86822100 ps
CPU time	17.05 seconds
Started	Jul 06 05:36:18 PM PDT 24
Finished	Jul 06 05:36:35 PM PDT 24
Peak memory	261332 kb
Host	smart-a660014d-b9f7-43d8-b465-dd4ceb63c93a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846998686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.3846998686
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3625663522
Short name	T1161
Test name
Test status
Simulation time	72592700 ps
CPU time	13.41 seconds
Started	Jul 06 05:36:20 PM PDT 24
Finished	Jul 06 05:36:34 PM PDT 24
Peak memory	261048 kb
Host	smart-076efc4c-381a-4c75-8b4c-b575d860d2f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625663522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3 625663522
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3874051621
Short name	T249
Test name
Test status
Simulation time	26609700 ps
CPU time	13.55 seconds
Started	Jul 06 05:36:19 PM PDT 24
Finished	Jul 06 05:36:33 PM PDT 24
Peak memory	262092 kb
Host	smart-74024036-d032-4112-a40c-faaab5d126eb
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874051621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.3874051621
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3660423641
Short name	T1201
Test name
Test status
Simulation time	24416200 ps
CPU time	13.95 seconds
Started	Jul 06 05:36:17 PM PDT 24
Finished	Jul 06 05:36:32 PM PDT 24
Peak memory	261092 kb
Host	smart-13bd1003-a7e3-4537-9884-fd529208f481
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660423641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.3660423641
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2716144074
Short name	T1223
Test name
Test status
Simulation time	153395400 ps
CPU time	17.64 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:36:45 PM PDT 24
Peak memory	261148 kb
Host	smart-fcf95191-1698-4b1d-80bf-8879c11c811e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716144074 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2716144074
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3177034232
Short name	T1209
Test name
Test status
Simulation time	38235800 ps
CPU time	15.97 seconds
Started	Jul 06 05:36:17 PM PDT 24
Finished	Jul 06 05:36:33 PM PDT 24
Peak memory	253056 kb
Host	smart-cf8cdc5f-236e-4d62-bdd1-16d6515fd148
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177034232 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3177034232
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1375097484
Short name	T1167
Test name
Test status
Simulation time	19303300 ps
CPU time	15.79 seconds
Started	Jul 06 05:36:16 PM PDT 24
Finished	Jul 06 05:36:32 PM PDT 24
Peak memory	252892 kb
Host	smart-4f1840e0-22ca-45d4-acd7-926cdac1075e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375097484 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1375097484
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3028878613
Short name	T1247
Test name
Test status
Simulation time	38366400 ps
CPU time	15.85 seconds
Started	Jul 06 05:36:13 PM PDT 24
Finished	Jul 06 05:36:29 PM PDT 24
Peak memory	262764 kb
Host	smart-6ddf8669-b121-4d54-82fb-0d166c368fad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028878613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3 028878613
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.850289386
Short name	T363
Test name
Test status
Simulation time	520535600 ps
CPU time	900.14 seconds
Started	Jul 06 05:36:14 PM PDT 24
Finished	Jul 06 05:51:14 PM PDT 24
Peak memory	263764 kb
Host	smart-009fa2c2-79da-425b-b6f2-94206e554d33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850289386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ tl_intg_err.850289386
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2006984485
Short name	T241
Test name
Test status
Simulation time	82688000 ps
CPU time	17.41 seconds
Started	Jul 06 05:37:25 PM PDT 24
Finished	Jul 06 05:37:43 PM PDT 24
Peak memory	263704 kb
Host	smart-3afbdc08-3a9b-4d71-b5fb-780a32c68cd7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006984485 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2006984485
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2563933375
Short name	T1145
Test name
Test status
Simulation time	37335900 ps
CPU time	17.05 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:26 PM PDT 24
Peak memory	263704 kb
Host	smart-83f7a3dd-a812-4d0b-bb8c-b7f4e0143149
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563933375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.2563933375
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1962195593
Short name	T1141
Test name
Test status
Simulation time	51240300 ps
CPU time	13.49 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:23 PM PDT 24
Peak memory	261240 kb
Host	smart-b993e733-af94-4104-bc37-b046b23c06e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962195593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 1962195593
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3144426947
Short name	T1170
Test name
Test status
Simulation time	71155400 ps
CPU time	17.91 seconds
Started	Jul 06 05:37:08 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	263084 kb
Host	smart-fa5aabd7-f973-4d73-8a8a-eec3167a863c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144426947 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3144426947
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4055024402
Short name	T1180
Test name
Test status
Simulation time	34246900 ps
CPU time	15.71 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:25 PM PDT 24
Peak memory	252896 kb
Host	smart-e23a8428-b8ff-409b-b955-34f606f5daf1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055024402 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.4055024402
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3376028179
Short name	T1128
Test name
Test status
Simulation time	41588300 ps
CPU time	15.73 seconds
Started	Jul 06 05:37:10 PM PDT 24
Finished	Jul 06 05:37:26 PM PDT 24
Peak memory	253012 kb
Host	smart-7f34861f-1c29-4721-9d8d-f33f5eaa31b2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376028179 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3376028179
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3312429453
Short name	T1263
Test name
Test status
Simulation time	66166000 ps
CPU time	17.19 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	263720 kb
Host	smart-30fe54c1-1d15-4b12-b3f5-e8f934fb6e28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312429453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 3312429453
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3898857234
Short name	T362
Test name
Test status
Simulation time	889137600 ps
CPU time	883.66 seconds
Started	Jul 06 05:37:08 PM PDT 24
Finished	Jul 06 05:51:52 PM PDT 24
Peak memory	263724 kb
Host	smart-7932c097-8c7b-4afb-9d6a-273c5f2fb45a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898857234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.3898857234
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2524762226
Short name	T1202
Test name
Test status
Simulation time	319442500 ps
CPU time	19.3 seconds
Started	Jul 06 05:37:10 PM PDT 24
Finished	Jul 06 05:37:29 PM PDT 24
Peak memory	270464 kb
Host	smart-384415ec-6119-4066-8bfe-3414777bd45f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524762226 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2524762226
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2727848009
Short name	T1249
Test name
Test status
Simulation time	113733400 ps
CPU time	14.14 seconds
Started	Jul 06 05:37:10 PM PDT 24
Finished	Jul 06 05:37:24 PM PDT 24
Peak memory	261260 kb
Host	smart-75fc82c4-551e-404e-9901-a3a3f4dd9350
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727848009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.2727848009
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.689310720
Short name	T1198
Test name
Test status
Simulation time	29415200 ps
CPU time	13.75 seconds
Started	Jul 06 05:37:11 PM PDT 24
Finished	Jul 06 05:37:25 PM PDT 24
Peak memory	261100 kb
Host	smart-dd1abc18-742c-4e7e-a54d-8709772f561c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689310720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.689310720
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.420534670
Short name	T1240
Test name
Test status
Simulation time	252448200 ps
CPU time	15.47 seconds
Started	Jul 06 05:37:11 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	263448 kb
Host	smart-9024e4ac-b408-42ac-be43-acfb3f69bcd4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420534670 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.420534670
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1798455879
Short name	T1231
Test name
Test status
Simulation time	35088200 ps
CPU time	16.23 seconds
Started	Jul 06 05:37:08 PM PDT 24
Finished	Jul 06 05:37:24 PM PDT 24
Peak memory	253020 kb
Host	smart-a6780437-bb0c-4004-92a9-ed963e05ff9f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798455879 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1798455879
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2234904247
Short name	T1134
Test name
Test status
Simulation time	55147700 ps
CPU time	13.2 seconds
Started	Jul 06 05:37:08 PM PDT 24
Finished	Jul 06 05:37:22 PM PDT 24
Peak memory	252944 kb
Host	smart-0ed1dc28-c067-47f8-8453-6f968f60fd4a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234904247 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2234904247
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1399393282
Short name	T245
Test name
Test status
Simulation time	57037200 ps
CPU time	19.08 seconds
Started	Jul 06 05:37:12 PM PDT 24
Finished	Jul 06 05:37:31 PM PDT 24
Peak memory	263192 kb
Host	smart-c0a59979-9134-4cb0-b874-cb3d5ebfec71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399393282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 1399393282
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3629383417
Short name	T365
Test name
Test status
Simulation time	2772846500 ps
CPU time	917.69 seconds
Started	Jul 06 05:37:08 PM PDT 24
Finished	Jul 06 05:52:26 PM PDT 24
Peak memory	263696 kb
Host	smart-2fe1b66e-b4d9-4570-86eb-52c0eb798eda
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629383417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.3629383417
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2325563778
Short name	T276
Test name
Test status
Simulation time	86880100 ps
CPU time	18.68 seconds
Started	Jul 06 05:37:13 PM PDT 24
Finished	Jul 06 05:37:32 PM PDT 24
Peak memory	272160 kb
Host	smart-f7af714c-24c0-4df8-b113-1a371a08aeac
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325563778 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2325563778
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2823048686
Short name	T1156
Test name
Test status
Simulation time	135472100 ps
CPU time	17.65 seconds
Started	Jul 06 05:37:12 PM PDT 24
Finished	Jul 06 05:37:30 PM PDT 24
Peak memory	263752 kb
Host	smart-c2fa3d10-1dcc-4e58-a153-88b8f50c47b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823048686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.2823048686
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1444457128
Short name	T263
Test name
Test status
Simulation time	24982300 ps
CPU time	14.08 seconds
Started	Jul 06 05:37:13 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	261108 kb
Host	smart-0acc2ef7-3d57-4b21-b576-934c24dbdce9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444457128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 1444457128
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2631944687
Short name	T1219
Test name
Test status
Simulation time	192245500 ps
CPU time	18.21 seconds
Started	Jul 06 05:37:13 PM PDT 24
Finished	Jul 06 05:37:32 PM PDT 24
Peak memory	262476 kb
Host	smart-e138c3a3-20ca-4831-839a-7582d0ec1bdb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631944687 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2631944687
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1325285104
Short name	T1171
Test name
Test status
Simulation time	14743100 ps
CPU time	15.93 seconds
Started	Jul 06 05:37:15 PM PDT 24
Finished	Jul 06 05:37:31 PM PDT 24
Peak memory	253056 kb
Host	smart-18db1c05-6f0b-470f-baf1-64c212483a5c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325285104 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1325285104
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1241948418
Short name	T1165
Test name
Test status
Simulation time	12007500 ps
CPU time	12.99 seconds
Started	Jul 06 05:37:11 PM PDT 24
Finished	Jul 06 05:37:24 PM PDT 24
Peak memory	252968 kb
Host	smart-61fa2fa0-64b9-4b36-8623-e17dd187daa7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241948418 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1241948418
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1639909163
Short name	T267
Test name
Test status
Simulation time	215169900 ps
CPU time	19.87 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:29 PM PDT 24
Peak memory	263704 kb
Host	smart-a2f18f75-e123-44b2-ba26-ee6e413a4e2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639909163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 1639909163
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1729969330
Short name	T278
Test name
Test status
Simulation time	138242400 ps
CPU time	16.93 seconds
Started	Jul 06 05:37:11 PM PDT 24
Finished	Jul 06 05:37:28 PM PDT 24
Peak memory	278284 kb
Host	smart-189b86c8-5e1f-41f1-a1a8-a67d215c74f6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729969330 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1729969330
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1472186253
Short name	T1208
Test name
Test status
Simulation time	273057200 ps
CPU time	15.24 seconds
Started	Jul 06 05:37:12 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	261348 kb
Host	smart-26641f51-9cb8-4cf7-a2ba-13761b5d38fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472186253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.1472186253
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3747345190
Short name	T1196
Test name
Test status
Simulation time	16476100 ps
CPU time	13.71 seconds
Started	Jul 06 05:37:14 PM PDT 24
Finished	Jul 06 05:37:28 PM PDT 24
Peak memory	261232 kb
Host	smart-9a10d6a9-5c1a-43bd-81be-58e0c9bbc459
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747345190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 3747345190
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2030724584
Short name	T304
Test name
Test status
Simulation time	271520900 ps
CPU time	15.92 seconds
Started	Jul 06 05:37:12 PM PDT 24
Finished	Jul 06 05:37:28 PM PDT 24
Peak memory	261280 kb
Host	smart-ebeaf663-eba4-4213-9eef-617a71d67f88
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030724584 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.2030724584
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1209511682
Short name	T1256
Test name
Test status
Simulation time	53647500 ps
CPU time	13.33 seconds
Started	Jul 06 05:37:14 PM PDT 24
Finished	Jul 06 05:37:27 PM PDT 24
Peak memory	252832 kb
Host	smart-db70bc90-eab4-4a0c-a0e6-5189826c5d4a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209511682 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.1209511682
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1598457636
Short name	T1184
Test name
Test status
Simulation time	41649500 ps
CPU time	15.98 seconds
Started	Jul 06 05:37:15 PM PDT 24
Finished	Jul 06 05:37:31 PM PDT 24
Peak memory	252792 kb
Host	smart-fa123889-8ed7-453d-95d9-2e7389ba10b3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598457636 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1598457636
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.714074262
Short name	T270
Test name
Test status
Simulation time	52365500 ps
CPU time	19.5 seconds
Started	Jul 06 05:37:13 PM PDT 24
Finished	Jul 06 05:37:32 PM PDT 24
Peak memory	263712 kb
Host	smart-291c79f1-beea-496d-9870-5d0e0011ba21
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714074262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.714074262
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.805632414
Short name	T367
Test name
Test status
Simulation time	178722400 ps
CPU time	452.04 seconds
Started	Jul 06 05:37:12 PM PDT 24
Finished	Jul 06 05:44:44 PM PDT 24
Peak memory	263728 kb
Host	smart-bda4d5f0-ea8b-4fdd-ada6-95c43e6dce0a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805632414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _tl_intg_err.805632414
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3328062321
Short name	T1214
Test name
Test status
Simulation time	188698600 ps
CPU time	17.99 seconds
Started	Jul 06 05:37:17 PM PDT 24
Finished	Jul 06 05:37:35 PM PDT 24
Peak memory	270588 kb
Host	smart-f5aa8e44-ecc3-49a3-adbd-d7331822461c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328062321 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3328062321
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3780525515
Short name	T65
Test name
Test status
Simulation time	169704200 ps
CPU time	14.36 seconds
Started	Jul 06 05:37:19 PM PDT 24
Finished	Jul 06 05:37:34 PM PDT 24
Peak memory	263768 kb
Host	smart-3a50c77d-f346-4f35-8703-daf97cfef85f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780525515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.3780525515
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2795265671
Short name	T303
Test name
Test status
Simulation time	222907000 ps
CPU time	19.45 seconds
Started	Jul 06 05:37:18 PM PDT 24
Finished	Jul 06 05:37:37 PM PDT 24
Peak memory	262564 kb
Host	smart-3c94ec57-024e-481e-a19f-d1ecd92eb32b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795265671 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2795265671
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2239526575
Short name	T1181
Test name
Test status
Simulation time	30266700 ps
CPU time	15.55 seconds
Started	Jul 06 05:37:18 PM PDT 24
Finished	Jul 06 05:37:34 PM PDT 24
Peak memory	253040 kb
Host	smart-7cf4f8fa-ee5d-4d2b-86a2-c2db58b99a40
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239526575 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2239526575
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2593986118
Short name	T1253
Test name
Test status
Simulation time	12541300 ps
CPU time	15.91 seconds
Started	Jul 06 05:37:17 PM PDT 24
Finished	Jul 06 05:37:33 PM PDT 24
Peak memory	252928 kb
Host	smart-447d40e7-5c6f-45f7-acef-66b8a5eb5330
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593986118 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2593986118
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3184858178
Short name	T118
Test name
Test status
Simulation time	64777200 ps
CPU time	20.8 seconds
Started	Jul 06 05:37:14 PM PDT 24
Finished	Jul 06 05:37:35 PM PDT 24
Peak memory	263684 kb
Host	smart-c5447484-444a-4f0a-ad0f-f6001da8980e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184858178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 3184858178
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.41487771
Short name	T364
Test name
Test status
Simulation time	2336669000 ps
CPU time	762.13 seconds
Started	Jul 06 05:37:13 PM PDT 24
Finished	Jul 06 05:49:55 PM PDT 24
Peak memory	263720 kb
Host	smart-99e657f3-a5ec-4a0b-abe6-b78e94aca8ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ tl_intg_err.41487771
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4174719019
Short name	T1163
Test name
Test status
Simulation time	250839900 ps
CPU time	15.52 seconds
Started	Jul 06 05:37:24 PM PDT 24
Finished	Jul 06 05:37:40 PM PDT 24
Peak memory	263716 kb
Host	smart-f14bf637-ef48-49e5-bd0f-62f7342a0b81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174719019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.4174719019
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.506489818
Short name	T1197
Test name
Test status
Simulation time	17568100 ps
CPU time	13.7 seconds
Started	Jul 06 05:37:24 PM PDT 24
Finished	Jul 06 05:37:38 PM PDT 24
Peak memory	261076 kb
Host	smart-13eeff10-4f9c-4477-a2be-8c24807d3ddb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506489818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.506489818
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2601569016
Short name	T302
Test name
Test status
Simulation time	115516500 ps
CPU time	18.8 seconds
Started	Jul 06 05:37:21 PM PDT 24
Finished	Jul 06 05:37:40 PM PDT 24
Peak memory	262824 kb
Host	smart-572a1144-eb9e-4b33-b122-3d9b379f2ea3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601569016 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2601569016
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.4088153596
Short name	T1211
Test name
Test status
Simulation time	37873100 ps
CPU time	15.6 seconds
Started	Jul 06 05:37:22 PM PDT 24
Finished	Jul 06 05:37:37 PM PDT 24
Peak memory	253020 kb
Host	smart-c0075313-3383-475a-b8f5-8dd4884a78c1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088153596 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.4088153596
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3564556722
Short name	T1168
Test name
Test status
Simulation time	21122800 ps
CPU time	13.42 seconds
Started	Jul 06 05:37:25 PM PDT 24
Finished	Jul 06 05:37:38 PM PDT 24
Peak memory	252948 kb
Host	smart-9ededc18-9129-47e8-8640-dffd5c3a1e7e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564556722 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3564556722
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.870279422
Short name	T246
Test name
Test status
Simulation time	36980400 ps
CPU time	16.98 seconds
Started	Jul 06 05:37:18 PM PDT 24
Finished	Jul 06 05:37:36 PM PDT 24
Peak memory	263704 kb
Host	smart-672a5455-44b4-42c5-8b71-7385509416e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870279422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.870279422
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3724953093
Short name	T300
Test name
Test status
Simulation time	55521800 ps
CPU time	15.15 seconds
Started	Jul 06 05:37:27 PM PDT 24
Finished	Jul 06 05:37:43 PM PDT 24
Peak memory	271996 kb
Host	smart-ba726c02-fd2f-4be7-8b21-0878e34ceb03
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724953093 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3724953093
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3314575283
Short name	T1212
Test name
Test status
Simulation time	124821100 ps
CPU time	16.53 seconds
Started	Jul 06 05:37:28 PM PDT 24
Finished	Jul 06 05:37:45 PM PDT 24
Peak memory	261264 kb
Host	smart-bc5014fb-773c-457a-8958-71c3bb5ded59
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314575283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.3314575283
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2367635761
Short name	T1186
Test name
Test status
Simulation time	29425500 ps
CPU time	13.77 seconds
Started	Jul 06 05:37:29 PM PDT 24
Finished	Jul 06 05:37:42 PM PDT 24
Peak memory	261228 kb
Host	smart-72aa8dbc-a549-43a3-9366-007d5bf60889
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367635761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 2367635761
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3581291196
Short name	T1135
Test name
Test status
Simulation time	34666100 ps
CPU time	15.42 seconds
Started	Jul 06 05:37:29 PM PDT 24
Finished	Jul 06 05:37:44 PM PDT 24
Peak memory	261300 kb
Host	smart-accb7a76-6b61-4fe5-b8ac-26127206567d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581291196 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3581291196
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3287891996
Short name	T1195
Test name
Test status
Simulation time	17436300 ps
CPU time	15.96 seconds
Started	Jul 06 05:37:29 PM PDT 24
Finished	Jul 06 05:37:45 PM PDT 24
Peak memory	252956 kb
Host	smart-5ed88a42-d10f-42dc-b574-ff7bd3c5d3e0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287891996 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3287891996
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2973204844
Short name	T1132
Test name
Test status
Simulation time	12173500 ps
CPU time	16.6 seconds
Started	Jul 06 05:37:27 PM PDT 24
Finished	Jul 06 05:37:43 PM PDT 24
Peak memory	252920 kb
Host	smart-92f0ea54-dabf-4fee-88e3-308c2dbfc6fb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973204844 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2973204844
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1910682177
Short name	T275
Test name
Test status
Simulation time	65474000 ps
CPU time	20.47 seconds
Started	Jul 06 05:37:24 PM PDT 24
Finished	Jul 06 05:37:45 PM PDT 24
Peak memory	263676 kb
Host	smart-e3f7c87d-27f5-4797-9eec-9e14034b1c05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910682177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 1910682177
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3673142162
Short name	T271
Test name
Test status
Simulation time	798725300 ps
CPU time	391.01 seconds
Started	Jul 06 05:37:24 PM PDT 24
Finished	Jul 06 05:43:55 PM PDT 24
Peak memory	263724 kb
Host	smart-8399e8d9-fe09-400d-bc9f-16c530489b42
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673142162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.3673142162
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1219382921
Short name	T117
Test name
Test status
Simulation time	25295100 ps
CPU time	15.27 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:50 PM PDT 24
Peak memory	271408 kb
Host	smart-374c2e7e-c0f6-4238-b4e1-94c4cabd5457
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219382921 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1219382921
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1969277136
Short name	T293
Test name
Test status
Simulation time	144554500 ps
CPU time	16.36 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:50 PM PDT 24
Peak memory	263716 kb
Host	smart-4ef46887-dfeb-4eb0-9807-4660a243391c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969277136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.1969277136
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3705379088
Short name	T316
Test name
Test status
Simulation time	44636200 ps
CPU time	13.39 seconds
Started	Jul 06 05:37:33 PM PDT 24
Finished	Jul 06 05:37:46 PM PDT 24
Peak memory	261108 kb
Host	smart-faf73cbd-6745-405b-975e-371dc833d6c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705379088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test. 3705379088
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4087528243
Short name	T1179
Test name
Test status
Simulation time	208245500 ps
CPU time	18.47 seconds
Started	Jul 06 05:37:33 PM PDT 24
Finished	Jul 06 05:37:52 PM PDT 24
Peak memory	262528 kb
Host	smart-8c992544-8ebc-415f-9d6f-587e9cb109d9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087528243 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.4087528243
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.369712846
Short name	T1175
Test name
Test status
Simulation time	12344200 ps
CPU time	13.25 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:48 PM PDT 24
Peak memory	252952 kb
Host	smart-e3273a4e-b943-450d-86aa-818c61275213
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369712846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.369712846
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2751276079
Short name	T1242
Test name
Test status
Simulation time	38441700 ps
CPU time	15.93 seconds
Started	Jul 06 05:37:33 PM PDT 24
Finished	Jul 06 05:37:49 PM PDT 24
Peak memory	253008 kb
Host	smart-45bdba3f-b4d4-440a-9ad1-c78d830e9a1a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751276079 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2751276079
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2459677383
Short name	T269
Test name
Test status
Simulation time	81686800 ps
CPU time	20.67 seconds
Started	Jul 06 05:37:28 PM PDT 24
Finished	Jul 06 05:37:49 PM PDT 24
Peak memory	263700 kb
Host	smart-29b0c08b-95c1-4eb5-832c-5b308df8e811
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459677383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 2459677383
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1453414191
Short name	T1174
Test name
Test status
Simulation time	110339700 ps
CPU time	19.02 seconds
Started	Jul 06 05:37:32 PM PDT 24
Finished	Jul 06 05:37:52 PM PDT 24
Peak memory	278752 kb
Host	smart-240d1181-923e-4379-8d87-c6ba493ea89f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453414191 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1453414191
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2785990400
Short name	T1204
Test name
Test status
Simulation time	29624700 ps
CPU time	17.48 seconds
Started	Jul 06 05:37:32 PM PDT 24
Finished	Jul 06 05:37:49 PM PDT 24
Peak memory	263672 kb
Host	smart-f80a0e46-363d-4a1d-81af-cdf5d033bbfd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785990400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.2785990400
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2946342281
Short name	T1136
Test name
Test status
Simulation time	60971700 ps
CPU time	13.57 seconds
Started	Jul 06 05:37:32 PM PDT 24
Finished	Jul 06 05:37:46 PM PDT 24
Peak memory	261232 kb
Host	smart-837bda47-628c-4bdd-94ed-53d211b901cb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946342281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 2946342281
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3118471880
Short name	T296
Test name
Test status
Simulation time	95993800 ps
CPU time	19.1 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:54 PM PDT 24
Peak memory	261080 kb
Host	smart-2654a0c8-7ee7-4968-ab98-8bd737fb66b4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118471880 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3118471880
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1030102181
Short name	T1140
Test name
Test status
Simulation time	31864200 ps
CPU time	15.83 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:50 PM PDT 24
Peak memory	252956 kb
Host	smart-46b58a93-c5b3-49e1-ac91-777603d295f4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030102181 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1030102181
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1635842219
Short name	T1226
Test name
Test status
Simulation time	44841000 ps
CPU time	16.1 seconds
Started	Jul 06 05:37:33 PM PDT 24
Finished	Jul 06 05:37:49 PM PDT 24
Peak memory	252944 kb
Host	smart-d46732dd-e51d-4e48-ad91-a8eb27fa5215
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635842219 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1635842219
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3086063186
Short name	T1230
Test name
Test status
Simulation time	201403500 ps
CPU time	17.4 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:37:52 PM PDT 24
Peak memory	263688 kb
Host	smart-6f527dac-aaf8-4272-b7b7-bd08b66de147
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086063186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 3086063186
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2004391210
Short name	T361
Test name
Test status
Simulation time	693908800 ps
CPU time	760.87 seconds
Started	Jul 06 05:37:34 PM PDT 24
Finished	Jul 06 05:50:16 PM PDT 24
Peak memory	263756 kb
Host	smart-7177838a-3aa4-455b-a462-e37927ee57c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004391210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.2004391210
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.210978201
Short name	T247
Test name
Test status
Simulation time	32442700 ps
CPU time	19.24 seconds
Started	Jul 06 05:37:38 PM PDT 24
Finished	Jul 06 05:37:58 PM PDT 24
Peak memory	278316 kb
Host	smart-fe2df86e-76ad-45fb-bbf4-c9cf2f57d9e0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210978201 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.210978201
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2762837694
Short name	T1200
Test name
Test status
Simulation time	114944100 ps
CPU time	17.67 seconds
Started	Jul 06 05:37:40 PM PDT 24
Finished	Jul 06 05:37:58 PM PDT 24
Peak memory	263740 kb
Host	smart-d23342d2-63de-48cc-bbf3-975fb054c026
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762837694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.2762837694
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2304535348
Short name	T1250
Test name
Test status
Simulation time	69469200 ps
CPU time	13.44 seconds
Started	Jul 06 05:37:38 PM PDT 24
Finished	Jul 06 05:37:51 PM PDT 24
Peak memory	261160 kb
Host	smart-c9afd4b6-6925-4d82-9979-4b5e05d46d6e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304535348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 2304535348
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.85766156
Short name	T1216
Test name
Test status
Simulation time	444226500 ps
CPU time	22.09 seconds
Started	Jul 06 05:37:38 PM PDT 24
Finished	Jul 06 05:38:01 PM PDT 24
Peak memory	262780 kb
Host	smart-d33290d4-4849-48ce-bc8f-abf714f162a1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85766156 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.85766156
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3070975501
Short name	T1130
Test name
Test status
Simulation time	14082700 ps
CPU time	15.82 seconds
Started	Jul 06 05:37:39 PM PDT 24
Finished	Jul 06 05:37:55 PM PDT 24
Peak memory	253084 kb
Host	smart-47e556e7-9bf3-4b84-9308-5d40f4fbbfaa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070975501 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3070975501
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2673718251
Short name	T1137
Test name
Test status
Simulation time	19316800 ps
CPU time	16.59 seconds
Started	Jul 06 05:37:39 PM PDT 24
Finished	Jul 06 05:37:56 PM PDT 24
Peak memory	252928 kb
Host	smart-87a7d467-c720-4fe7-8a5d-56562a713475
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673718251 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2673718251
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2380468954
Short name	T268
Test name
Test status
Simulation time	50529800 ps
CPU time	19.07 seconds
Started	Jul 06 05:37:33 PM PDT 24
Finished	Jul 06 05:37:52 PM PDT 24
Peak memory	263036 kb
Host	smart-3d355308-24b9-4d08-8c43-63ef02eaeb9d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380468954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 2380468954
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.922703465
Short name	T366
Test name
Test status
Simulation time	2867193000 ps
CPU time	902.56 seconds
Started	Jul 06 05:37:39 PM PDT 24
Finished	Jul 06 05:52:42 PM PDT 24
Peak memory	263768 kb
Host	smart-1eee8725-6cd5-4807-8ec0-4ec6400d0602
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922703465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl _tl_intg_err.922703465
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1028095752
Short name	T1153
Test name
Test status
Simulation time	1706561200 ps
CPU time	55.18 seconds
Started	Jul 06 05:36:28 PM PDT 24
Finished	Jul 06 05:37:24 PM PDT 24
Peak memory	261324 kb
Host	smart-92eb2fa0-4420-41c4-8f24-c9c0e054eab7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028095752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_aliasing.1028095752
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2222120528
Short name	T1194
Test name
Test status
Simulation time	15604389300 ps
CPU time	115.81 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:38:23 PM PDT 24
Peak memory	261280 kb
Host	smart-31080994-452b-4cef-aeb4-af629c3c723d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222120528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.2222120528
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2027542625
Short name	T1203
Test name
Test status
Simulation time	52311800 ps
CPU time	46.89 seconds
Started	Jul 06 05:36:26 PM PDT 24
Finished	Jul 06 05:37:13 PM PDT 24
Peak memory	261188 kb
Host	smart-b6179175-7f05-4f88-8e06-9387c3aa3d47
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027542625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.2027542625
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1259420865
Short name	T1182
Test name
Test status
Simulation time	105998300 ps
CPU time	17.72 seconds
Started	Jul 06 05:36:32 PM PDT 24
Finished	Jul 06 05:36:50 PM PDT 24
Peak memory	271756 kb
Host	smart-3dae233e-9f08-4fd3-af8a-5613e1cd97f8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259420865 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1259420865
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.892465610
Short name	T1222
Test name
Test status
Simulation time	103282900 ps
CPU time	14.93 seconds
Started	Jul 06 05:36:26 PM PDT 24
Finished	Jul 06 05:36:41 PM PDT 24
Peak memory	263756 kb
Host	smart-8c5e842c-d65b-43db-b94b-2b884997f7da
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892465610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_csr_rw.892465610
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3569368719
Short name	T1139
Test name
Test status
Simulation time	43539800 ps
CPU time	13.14 seconds
Started	Jul 06 05:36:28 PM PDT 24
Finished	Jul 06 05:36:41 PM PDT 24
Peak memory	261152 kb
Host	smart-b044b304-9ff4-4af9-af5d-6792c919b46c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569368719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3 569368719
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.363123318
Short name	T250
Test name
Test status
Simulation time	22116800 ps
CPU time	14.72 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:36:42 PM PDT 24
Peak memory	262832 kb
Host	smart-a908ca70-3e8e-4226-9597-11c783c28cf5
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363123318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_mem_partial_access.363123318
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.18411515
Short name	T1225
Test name
Test status
Simulation time	18053300 ps
CPU time	13.31 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:36:41 PM PDT 24
Peak memory	261016 kb
Host	smart-0e46db9c-5471-4a54-886b-6b009bf4c932
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18411515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_ walk.18411515
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.566325593
Short name	T295
Test name
Test status
Simulation time	212481400 ps
CPU time	18.92 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:36:46 PM PDT 24
Peak memory	263736 kb
Host	smart-6342710e-045b-41e1-86d2-803f51367911
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566325593 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.566325593
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.873637501
Short name	T1154
Test name
Test status
Simulation time	11949700 ps
CPU time	15.76 seconds
Started	Jul 06 05:36:25 PM PDT 24
Finished	Jul 06 05:36:41 PM PDT 24
Peak memory	252948 kb
Host	smart-6f785ccc-8d15-49bf-880e-777ea5b9d1ff
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873637501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.873637501
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2545973313
Short name	T1125
Test name
Test status
Simulation time	130423800 ps
CPU time	13.15 seconds
Started	Jul 06 05:36:22 PM PDT 24
Finished	Jul 06 05:36:35 PM PDT 24
Peak memory	252920 kb
Host	smart-48200ed9-468c-4d99-8826-de572496a691
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545973313 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2545973313
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3155381016
Short name	T273
Test name
Test status
Simulation time	60678600 ps
CPU time	19.84 seconds
Started	Jul 06 05:36:27 PM PDT 24
Finished	Jul 06 05:36:47 PM PDT 24
Peak memory	263704 kb
Host	smart-4d2658b7-275f-49c7-bdb5-60447ce1d0c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155381016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3 155381016
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1912888456
Short name	T240
Test name
Test status
Simulation time	673249000 ps
CPU time	890.31 seconds
Started	Jul 06 05:36:23 PM PDT 24
Finished	Jul 06 05:51:14 PM PDT 24
Peak memory	263760 kb
Host	smart-ff52c097-e177-4b14-a5b4-6187b2c0548c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912888456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.1912888456
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1694713045
Short name	T1155
Test name
Test status
Simulation time	24988700 ps
CPU time	13.54 seconds
Started	Jul 06 05:37:37 PM PDT 24
Finished	Jul 06 05:37:51 PM PDT 24
Peak memory	261068 kb
Host	smart-8da31fc6-deed-4ad4-837f-240b90066eaf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694713045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test. 1694713045
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1939374425
Short name	T1199
Test name
Test status
Simulation time	32524800 ps
CPU time	13.69 seconds
Started	Jul 06 05:37:39 PM PDT 24
Finished	Jul 06 05:37:53 PM PDT 24
Peak memory	261216 kb
Host	smart-de471a2a-6f06-4386-96aa-b4329b1d485c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939374425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 1939374425
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.641385872
Short name	T1258
Test name
Test status
Simulation time	30386500 ps
CPU time	13.64 seconds
Started	Jul 06 05:37:46 PM PDT 24
Finished	Jul 06 05:38:00 PM PDT 24
Peak memory	261040 kb
Host	smart-0da7a1ca-0e19-45b0-af29-a0d4d7d035d8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641385872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.641385872
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1985842327
Short name	T1149
Test name
Test status
Simulation time	41066300 ps
CPU time	13.4 seconds
Started	Jul 06 05:37:43 PM PDT 24
Finished	Jul 06 05:37:56 PM PDT 24
Peak memory	261008 kb
Host	smart-b97da847-b96f-4ac9-84c3-04c0164dcd25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985842327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test. 1985842327
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.336822299
Short name	T1239
Test name
Test status
Simulation time	28257700 ps
CPU time	13.63 seconds
Started	Jul 06 05:37:43 PM PDT 24
Finished	Jul 06 05:37:57 PM PDT 24
Peak memory	261084 kb
Host	smart-9bcda8bd-84cd-45b7-9364-db88b22fad32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336822299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.336822299
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4053430632
Short name	T1248
Test name
Test status
Simulation time	55022800 ps
CPU time	13.49 seconds
Started	Jul 06 05:37:43 PM PDT 24
Finished	Jul 06 05:37:57 PM PDT 24
Peak memory	261240 kb
Host	smart-52f84fd5-e6f2-47cf-8b0c-3e17201dbfdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053430632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 4053430632
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3756789921
Short name	T1157
Test name
Test status
Simulation time	33521000 ps
CPU time	13.77 seconds
Started	Jul 06 05:37:43 PM PDT 24
Finished	Jul 06 05:37:57 PM PDT 24
Peak memory	261112 kb
Host	smart-46ffcd01-a4f0-4335-b502-60ab182946fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756789921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 3756789921
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1270852466
Short name	T1227
Test name
Test status
Simulation time	158061600 ps
CPU time	13.57 seconds
Started	Jul 06 05:37:46 PM PDT 24
Finished	Jul 06 05:38:00 PM PDT 24
Peak memory	261100 kb
Host	smart-1e502150-b6be-444d-8c90-9b0fa0eed266
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270852466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 1270852466
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1671358257
Short name	T1143
Test name
Test status
Simulation time	32152300 ps
CPU time	13.74 seconds
Started	Jul 06 05:37:42 PM PDT 24
Finished	Jul 06 05:37:56 PM PDT 24
Peak memory	261232 kb
Host	smart-2b1b4150-df47-435f-b880-cd7d8369dd51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671358257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test. 1671358257
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2080153249
Short name	T1245
Test name
Test status
Simulation time	918644700 ps
CPU time	35.19 seconds
Started	Jul 06 05:36:37 PM PDT 24
Finished	Jul 06 05:37:13 PM PDT 24
Peak memory	261272 kb
Host	smart-bdf3f96d-a876-4f71-8122-34c933f55201
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080153249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.2080153249
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3017245917
Short name	T1259
Test name
Test status
Simulation time	1277922300 ps
CPU time	40.25 seconds
Started	Jul 06 05:36:36 PM PDT 24
Finished	Jul 06 05:37:16 PM PDT 24
Peak memory	261292 kb
Host	smart-b1cfd9fc-3c78-4790-87b4-0225761d8fd0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017245917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.3017245917
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.472027642
Short name	T1142
Test name
Test status
Simulation time	155560000 ps
CPU time	30.67 seconds
Started	Jul 06 05:36:32 PM PDT 24
Finished	Jul 06 05:37:03 PM PDT 24
Peak memory	263012 kb
Host	smart-4150ca01-0a3c-46de-a934-45c8a689ab28
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472027642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.flash_ctrl_csr_hw_reset.472027642
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.927298106
Short name	T274
Test name
Test status
Simulation time	202083300 ps
CPU time	17.56 seconds
Started	Jul 06 05:36:40 PM PDT 24
Finished	Jul 06 05:36:57 PM PDT 24
Peak memory	272000 kb
Host	smart-bc17e036-70f9-4437-9a72-c7d25c6eb4dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927298106 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.927298106
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.4208562342
Short name	T1233
Test name
Test status
Simulation time	73335700 ps
CPU time	16.86 seconds
Started	Jul 06 05:36:37 PM PDT 24
Finished	Jul 06 05:36:54 PM PDT 24
Peak memory	261212 kb
Host	smart-4a61fcf7-bf70-40a2-aa3f-998551c90417
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208562342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.4208562342
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1952106822
Short name	T1187
Test name
Test status
Simulation time	67985800 ps
CPU time	13.98 seconds
Started	Jul 06 05:36:34 PM PDT 24
Finished	Jul 06 05:36:48 PM PDT 24
Peak memory	261232 kb
Host	smart-304879c1-4bad-433f-8fdd-4e8f4cc542f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952106822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1 952106822
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.320883339
Short name	T252
Test name
Test status
Simulation time	17494700 ps
CPU time	13.66 seconds
Started	Jul 06 05:36:38 PM PDT 24
Finished	Jul 06 05:36:52 PM PDT 24
Peak memory	262096 kb
Host	smart-72c7e16b-91d6-4c22-9b88-24c3e4f722c0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320883339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_mem_partial_access.320883339
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4220135879
Short name	T1147
Test name
Test status
Simulation time	45499000 ps
CPU time	13.43 seconds
Started	Jul 06 05:36:33 PM PDT 24
Finished	Jul 06 05:36:47 PM PDT 24
Peak memory	261040 kb
Host	smart-c3a6e368-6f4e-4cc5-b6a2-9605ee99d2a4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220135879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.4220135879
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1982661622
Short name	T260
Test name
Test status
Simulation time	110357100 ps
CPU time	18.35 seconds
Started	Jul 06 05:36:39 PM PDT 24
Finished	Jul 06 05:36:58 PM PDT 24
Peak memory	263780 kb
Host	smart-411beee6-a4df-440a-bd2c-8a35db3a03db
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982661622 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1982661622
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.316361188
Short name	T1169
Test name
Test status
Simulation time	18953100 ps
CPU time	15.82 seconds
Started	Jul 06 05:36:39 PM PDT 24
Finished	Jul 06 05:36:55 PM PDT 24
Peak memory	252948 kb
Host	smart-9e7ac7e8-c27e-48f6-b4aa-9edb999399de
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316361188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.316361188
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2462623544
Short name	T1127
Test name
Test status
Simulation time	13613100 ps
CPU time	16.4 seconds
Started	Jul 06 05:36:31 PM PDT 24
Finished	Jul 06 05:36:47 PM PDT 24
Peak memory	252944 kb
Host	smart-f3b44516-dee7-41c8-aea7-d7268ffe340a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462623544 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2462623544
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3237179278
Short name	T359
Test name
Test status
Simulation time	1557841500 ps
CPU time	384.71 seconds
Started	Jul 06 05:36:38 PM PDT 24
Finished	Jul 06 05:43:04 PM PDT 24
Peak memory	263760 kb
Host	smart-54fe65ac-6c1c-4695-896d-53c00d2add85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237179278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.3237179278
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1939985012
Short name	T1185
Test name
Test status
Simulation time	30141000 ps
CPU time	13.3 seconds
Started	Jul 06 05:37:43 PM PDT 24
Finished	Jul 06 05:37:57 PM PDT 24
Peak memory	261232 kb
Host	smart-058c1882-1899-4948-8710-b36b28ea1f0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939985012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test. 1939985012
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3292005580
Short name	T1228
Test name
Test status
Simulation time	16676500 ps
CPU time	13.56 seconds
Started	Jul 06 05:37:41 PM PDT 24
Finished	Jul 06 05:37:54 PM PDT 24
Peak memory	261104 kb
Host	smart-568537e0-ef57-4ec4-a8fc-b9abd1a6d1f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292005580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 3292005580
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.339594595
Short name	T1220
Test name
Test status
Simulation time	30594100 ps
CPU time	13.61 seconds
Started	Jul 06 05:37:46 PM PDT 24
Finished	Jul 06 05:38:00 PM PDT 24
Peak memory	261100 kb
Host	smart-f589367d-9824-4147-8eb8-d169f5c283c7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339594595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.339594595
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.799314718
Short name	T1190
Test name
Test status
Simulation time	20863900 ps
CPU time	13.85 seconds
Started	Jul 06 05:37:42 PM PDT 24
Finished	Jul 06 05:37:56 PM PDT 24
Peak memory	261228 kb
Host	smart-e32a59ce-a97b-453f-9279-d99577008d3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799314718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.799314718
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2699006408
Short name	T321
Test name
Test status
Simulation time	45062200 ps
CPU time	13.81 seconds
Started	Jul 06 05:37:44 PM PDT 24
Finished	Jul 06 05:37:58 PM PDT 24
Peak memory	261048 kb
Host	smart-881d1c61-f80b-4612-9e09-9c3c5ea5fa38
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699006408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 2699006408
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2941238336
Short name	T1234
Test name
Test status
Simulation time	24322000 ps
CPU time	13.6 seconds
Started	Jul 06 05:37:46 PM PDT 24
Finished	Jul 06 05:38:00 PM PDT 24
Peak memory	261168 kb
Host	smart-25967a6b-d342-41a2-a3e3-6a84bb4c461f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941238336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 2941238336
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3356209324
Short name	T1144
Test name
Test status
Simulation time	53512900 ps
CPU time	13.43 seconds
Started	Jul 06 05:37:47 PM PDT 24
Finished	Jul 06 05:38:01 PM PDT 24
Peak memory	261124 kb
Host	smart-2411a59c-14ed-4b48-b666-76aefadb796d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356209324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 3356209324
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1089727371
Short name	T318
Test name
Test status
Simulation time	17784300 ps
CPU time	13.25 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:04 PM PDT 24
Peak memory	261200 kb
Host	smart-24cf2914-899a-4eee-b230-53aa031e7224
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089727371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 1089727371
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.304979417
Short name	T1138
Test name
Test status
Simulation time	30680500 ps
CPU time	13.85 seconds
Started	Jul 06 05:37:48 PM PDT 24
Finished	Jul 06 05:38:02 PM PDT 24
Peak memory	261116 kb
Host	smart-1a7af813-f38d-4926-8176-eedd44f15e79
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304979417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.304979417
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4089486161
Short name	T1243
Test name
Test status
Simulation time	74650700 ps
CPU time	13.47 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:05 PM PDT 24
Peak memory	261240 kb
Host	smart-673c92cc-7582-4d6c-ad99-5c3290efd3e2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089486161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test. 4089486161
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4116526008
Short name	T1260
Test name
Test status
Simulation time	3825466800 ps
CPU time	63.97 seconds
Started	Jul 06 05:36:51 PM PDT 24
Finished	Jul 06 05:37:56 PM PDT 24
Peak memory	261320 kb
Host	smart-2d5e8357-5437-4cd0-b6b7-ac97e7e58474
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116526008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_aliasing.4116526008
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.191997392
Short name	T299
Test name
Test status
Simulation time	6318881500 ps
CPU time	96.43 seconds
Started	Jul 06 05:36:42 PM PDT 24
Finished	Jul 06 05:38:19 PM PDT 24
Peak memory	261228 kb
Host	smart-1e9a7efc-a7f2-4e0e-9645-34b320b47213
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191997392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_bit_bash.191997392
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3832817386
Short name	T1246
Test name
Test status
Simulation time	251938700 ps
CPU time	30.87 seconds
Started	Jul 06 05:36:42 PM PDT 24
Finished	Jul 06 05:37:13 PM PDT 24
Peak memory	261360 kb
Host	smart-90cf4e91-9ca0-486e-9820-aa45803517af
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832817386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.3832817386
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.802627153
Short name	T1257
Test name
Test status
Simulation time	123867200 ps
CPU time	17.3 seconds
Started	Jul 06 05:36:56 PM PDT 24
Finished	Jul 06 05:37:14 PM PDT 24
Peak memory	277736 kb
Host	smart-9268e517-a4de-4e6f-9b62-bd008db1049c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802627153 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.802627153
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.849989757
Short name	T298
Test name
Test status
Simulation time	72928000 ps
CPU time	15.34 seconds
Started	Jul 06 05:36:44 PM PDT 24
Finished	Jul 06 05:37:00 PM PDT 24
Peak memory	263728 kb
Host	smart-2ee34aab-f8c9-42dc-a6d7-16e9db66bb82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849989757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_csr_rw.849989757
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2839354749
Short name	T265
Test name
Test status
Simulation time	37577800 ps
CPU time	13.68 seconds
Started	Jul 06 05:36:41 PM PDT 24
Finished	Jul 06 05:36:55 PM PDT 24
Peak memory	261148 kb
Host	smart-c35f36a0-9675-4cd8-8403-6d598e28439a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839354749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2 839354749
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2893023789
Short name	T251
Test name
Test status
Simulation time	24406000 ps
CPU time	13.37 seconds
Started	Jul 06 05:36:42 PM PDT 24
Finished	Jul 06 05:36:56 PM PDT 24
Peak memory	262728 kb
Host	smart-cf362ea2-8902-450c-9bc6-8248bb91b8fb
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893023789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.2893023789
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2512099139
Short name	T1255
Test name
Test status
Simulation time	42437600 ps
CPU time	13.42 seconds
Started	Jul 06 05:36:42 PM PDT 24
Finished	Jul 06 05:36:56 PM PDT 24
Peak memory	261100 kb
Host	smart-03b2705e-1741-45dd-9069-2bfa88fd006f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512099139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.2512099139
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.155845887
Short name	T1213
Test name
Test status
Simulation time	110178400 ps
CPU time	16.81 seconds
Started	Jul 06 05:36:47 PM PDT 24
Finished	Jul 06 05:37:04 PM PDT 24
Peak memory	261156 kb
Host	smart-8becbdc1-3368-4b11-a19a-973a9a8e91a9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155845887 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.155845887
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4232718807
Short name	T1261
Test name
Test status
Simulation time	52821100 ps
CPU time	16.17 seconds
Started	Jul 06 05:36:37 PM PDT 24
Finished	Jul 06 05:36:54 PM PDT 24
Peak memory	253084 kb
Host	smart-39ecc833-fb15-4290-a1ee-5766cd1b78b7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232718807 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.4232718807
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.234779626
Short name	T1129
Test name
Test status
Simulation time	11957800 ps
CPU time	16.01 seconds
Started	Jul 06 05:36:42 PM PDT 24
Finished	Jul 06 05:36:59 PM PDT 24
Peak memory	252956 kb
Host	smart-0b210b2d-7660-40c9-923b-698531657481
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234779626 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.234779626
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3487099758
Short name	T1192
Test name
Test status
Simulation time	43010700 ps
CPU time	17.61 seconds
Started	Jul 06 05:36:36 PM PDT 24
Finished	Jul 06 05:36:54 PM PDT 24
Peak memory	262988 kb
Host	smart-439b4fa1-6665-47db-9b42-1e5d74ace773
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487099758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3 487099758
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1198714652
Short name	T1126
Test name
Test status
Simulation time	50677600 ps
CPU time	13.18 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:04 PM PDT 24
Peak memory	261136 kb
Host	smart-3795d06d-3a9b-401e-9ac5-385b8fa87aa7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198714652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 1198714652
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.463453146
Short name	T1206
Test name
Test status
Simulation time	15186100 ps
CPU time	14.1 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:06 PM PDT 24
Peak memory	261180 kb
Host	smart-207e8834-0f4a-4836-bd5f-4f50f72abb64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463453146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.463453146
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3583906083
Short name	T1150
Test name
Test status
Simulation time	223292500 ps
CPU time	14.55 seconds
Started	Jul 06 05:37:48 PM PDT 24
Finished	Jul 06 05:38:03 PM PDT 24
Peak memory	261212 kb
Host	smart-118e4bf1-0810-46ba-afe9-ed0110fcc26a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583906083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 3583906083
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1374483458
Short name	T1158
Test name
Test status
Simulation time	17872500 ps
CPU time	13.74 seconds
Started	Jul 06 05:37:47 PM PDT 24
Finished	Jul 06 05:38:01 PM PDT 24
Peak memory	260944 kb
Host	smart-a2d64e8f-d5ef-4a8d-a52a-d711e06a5ac3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374483458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 1374483458
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2140854493
Short name	T1251
Test name
Test status
Simulation time	57072900 ps
CPU time	14.54 seconds
Started	Jul 06 05:37:48 PM PDT 24
Finished	Jul 06 05:38:03 PM PDT 24
Peak memory	261184 kb
Host	smart-fc918475-8d4b-4c2d-a13f-6fbe3ab26b7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140854493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test. 2140854493
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2783337959
Short name	T1229
Test name
Test status
Simulation time	27716600 ps
CPU time	13.41 seconds
Started	Jul 06 05:37:47 PM PDT 24
Finished	Jul 06 05:38:01 PM PDT 24
Peak memory	261144 kb
Host	smart-ca7516dc-faa4-4efa-9909-655242d3ee4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783337959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 2783337959
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3393495307
Short name	T1162
Test name
Test status
Simulation time	18710300 ps
CPU time	14.15 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:06 PM PDT 24
Peak memory	261184 kb
Host	smart-6088236a-6d63-4de4-bd61-528f604783b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393495307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 3393495307
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2263361779
Short name	T317
Test name
Test status
Simulation time	39524600 ps
CPU time	13.37 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:05 PM PDT 24
Peak memory	261196 kb
Host	smart-6a25cee3-5418-4547-b899-b49389aa1e65
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263361779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 2263361779
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1693223040
Short name	T320
Test name
Test status
Simulation time	17124200 ps
CPU time	13.51 seconds
Started	Jul 06 05:37:51 PM PDT 24
Finished	Jul 06 05:38:04 PM PDT 24
Peak memory	261236 kb
Host	smart-8d63fbad-8d16-417f-ad0b-7e6b389056c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693223040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 1693223040
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1871552587
Short name	T1217
Test name
Test status
Simulation time	14478400 ps
CPU time	13.88 seconds
Started	Jul 06 05:37:47 PM PDT 24
Finished	Jul 06 05:38:01 PM PDT 24
Peak memory	261164 kb
Host	smart-dd2c54a8-9f3e-456a-9bd0-2f61a0edf8ef
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871552587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 1871552587
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2825061203
Short name	T1160
Test name
Test status
Simulation time	74053000 ps
CPU time	18.01 seconds
Started	Jul 06 05:36:47 PM PDT 24
Finished	Jul 06 05:37:05 PM PDT 24
Peak memory	264044 kb
Host	smart-a763f094-2435-409f-80fc-1d405c3de3f9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825061203 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2825061203
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1641686026
Short name	T261
Test name
Test status
Simulation time	73509900 ps
CPU time	17.11 seconds
Started	Jul 06 05:36:51 PM PDT 24
Finished	Jul 06 05:37:09 PM PDT 24
Peak memory	263720 kb
Host	smart-1d2fb96a-e5e6-45ee-af46-8a4645f43bc5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641686026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.1641686026
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2259436749
Short name	T1221
Test name
Test status
Simulation time	36092500 ps
CPU time	13.99 seconds
Started	Jul 06 05:36:48 PM PDT 24
Finished	Jul 06 05:37:03 PM PDT 24
Peak memory	261048 kb
Host	smart-56b89291-787e-4ca5-b601-81f151445e5c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259436749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2 259436749
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1883666486
Short name	T1264
Test name
Test status
Simulation time	3411293500 ps
CPU time	23.47 seconds
Started	Jul 06 05:36:46 PM PDT 24
Finished	Jul 06 05:37:10 PM PDT 24
Peak memory	263500 kb
Host	smart-458f4ea7-ef42-4222-a3c4-7e483db64203
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883666486 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1883666486
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.793718003
Short name	T1238
Test name
Test status
Simulation time	12541900 ps
CPU time	13.41 seconds
Started	Jul 06 05:36:46 PM PDT 24
Finished	Jul 06 05:36:59 PM PDT 24
Peak memory	252944 kb
Host	smart-e6a69058-bbcc-4e4a-9f23-e481f9d53c59
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793718003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.793718003
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3750290026
Short name	T1151
Test name
Test status
Simulation time	44185700 ps
CPU time	15.65 seconds
Started	Jul 06 05:36:45 PM PDT 24
Finished	Jul 06 05:37:01 PM PDT 24
Peak memory	253008 kb
Host	smart-aedf7526-22f3-425a-8abe-1004b30d1317
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750290026 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.3750290026
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.421132977
Short name	T1193
Test name
Test status
Simulation time	35640700 ps
CPU time	16.11 seconds
Started	Jul 06 05:36:56 PM PDT 24
Finished	Jul 06 05:37:12 PM PDT 24
Peak memory	263716 kb
Host	smart-23a8fcd7-fc9b-450f-a962-f745f31d2e90
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421132977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.421132977
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2111822217
Short name	T1205
Test name
Test status
Simulation time	25890300 ps
CPU time	15.91 seconds
Started	Jul 06 05:36:51 PM PDT 24
Finished	Jul 06 05:37:07 PM PDT 24
Peak memory	278400 kb
Host	smart-7a1f692d-26df-44bb-bcc2-eeb6dd24d60b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111822217 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2111822217
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2167391460
Short name	T1266
Test name
Test status
Simulation time	333749900 ps
CPU time	16.61 seconds
Started	Jul 06 05:36:52 PM PDT 24
Finished	Jul 06 05:37:09 PM PDT 24
Peak memory	261296 kb
Host	smart-a7d3eac0-2e74-46b5-8735-7a876721ffa8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167391460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.2167391460
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.223606106
Short name	T1176
Test name
Test status
Simulation time	98053800 ps
CPU time	13.48 seconds
Started	Jul 06 05:36:52 PM PDT 24
Finished	Jul 06 05:37:06 PM PDT 24
Peak memory	261100 kb
Host	smart-f70951b0-9b9a-4ba5-8ded-68723f84ebcb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223606106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.223606106
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.760305938
Short name	T1262
Test name
Test status
Simulation time	329498700 ps
CPU time	35.67 seconds
Started	Jul 06 05:36:52 PM PDT 24
Finished	Jul 06 05:37:28 PM PDT 24
Peak memory	263644 kb
Host	smart-80795691-9619-448a-acf6-dd2f5706e437
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760305938 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.760305938
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2969991008
Short name	T1232
Test name
Test status
Simulation time	32364900 ps
CPU time	13.05 seconds
Started	Jul 06 05:36:56 PM PDT 24
Finished	Jul 06 05:37:10 PM PDT 24
Peak memory	253012 kb
Host	smart-9b487251-a660-492c-ab2a-dad3bbd224f6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969991008 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2969991008
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2281440992
Short name	T1131
Test name
Test status
Simulation time	26703000 ps
CPU time	15.73 seconds
Started	Jul 06 05:38:06 PM PDT 24
Finished	Jul 06 05:38:22 PM PDT 24
Peak memory	252836 kb
Host	smart-9d7fdc05-d2b2-4140-8376-8c6feef70195
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281440992 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2281440992
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3831134347
Short name	T1252
Test name
Test status
Simulation time	51510900 ps
CPU time	19.86 seconds
Started	Jul 06 05:36:51 PM PDT 24
Finished	Jul 06 05:37:11 PM PDT 24
Peak memory	263680 kb
Host	smart-af63293e-10e8-470d-8484-7b21dfd1412c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831134347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3 831134347
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1005458796
Short name	T1235
Test name
Test status
Simulation time	377673700 ps
CPU time	450.76 seconds
Started	Jul 06 05:36:56 PM PDT 24
Finished	Jul 06 05:44:27 PM PDT 24
Peak memory	263760 kb
Host	smart-716634c2-f453-4637-8594-4b772aaf480e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005458796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl _tl_intg_err.1005458796
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2388826927
Short name	T1183
Test name
Test status
Simulation time	234810700 ps
CPU time	18.14 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:16 PM PDT 24
Peak memory	271892 kb
Host	smart-f15d0dea-1607-46e7-ae57-6a3521a17fb3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388826927 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2388826927
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1623277460
Short name	T1241
Test name
Test status
Simulation time	203148000 ps
CPU time	17.21 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:16 PM PDT 24
Peak memory	263752 kb
Host	smart-88ab8b35-3678-452d-b05a-837ec4893ed3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623277460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.1623277460
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2938610286
Short name	T1267
Test name
Test status
Simulation time	54302400 ps
CPU time	13.78 seconds
Started	Jul 06 05:36:56 PM PDT 24
Finished	Jul 06 05:37:11 PM PDT 24
Peak memory	261248 kb
Host	smart-9e1564aa-94b2-4a42-8ecd-13ae7c21869b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938610286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2 938610286
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2092157917
Short name	T294
Test name
Test status
Simulation time	100664100 ps
CPU time	18.56 seconds
Started	Jul 06 05:36:55 PM PDT 24
Finished	Jul 06 05:37:14 PM PDT 24
Peak memory	261236 kb
Host	smart-83415678-03e8-4ea1-bb05-87d172954f70
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092157917 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2092157917
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.285313298
Short name	T1236
Test name
Test status
Simulation time	17112500 ps
CPU time	13.94 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:13 PM PDT 24
Peak memory	252908 kb
Host	smart-aa81619d-942d-44bc-9fb5-a983250cb925
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285313298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.285313298
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1640806328
Short name	T1177
Test name
Test status
Simulation time	11661200 ps
CPU time	16.67 seconds
Started	Jul 06 05:36:57 PM PDT 24
Finished	Jul 06 05:37:14 PM PDT 24
Peak memory	252876 kb
Host	smart-d0dd732b-393f-47d7-a295-87228135cbfc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640806328 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1640806328
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.4176988162
Short name	T1210
Test name
Test status
Simulation time	50922300 ps
CPU time	19.54 seconds
Started	Jul 06 05:36:51 PM PDT 24
Finished	Jul 06 05:37:11 PM PDT 24
Peak memory	263712 kb
Host	smart-5c7fb7f8-97d5-45b3-9248-d26787dd806a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176988162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.4 176988162
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2461930392
Short name	T239
Test name
Test status
Simulation time	835045500 ps
CPU time	899.5 seconds
Started	Jul 06 05:36:55 PM PDT 24
Finished	Jul 06 05:51:54 PM PDT 24
Peak memory	263764 kb
Host	smart-65380509-2c9c-4018-b61a-e4a274ff4d99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461930392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.2461930392
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2937817117
Short name	T1191
Test name
Test status
Simulation time	249922600 ps
CPU time	18.78 seconds
Started	Jul 06 05:37:01 PM PDT 24
Finished	Jul 06 05:37:20 PM PDT 24
Peak memory	271208 kb
Host	smart-75281ab0-ea45-48db-9a4e-57b602895dee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937817117 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2937817117
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2207968431
Short name	T1164
Test name
Test status
Simulation time	75054000 ps
CPU time	17 seconds
Started	Jul 06 05:36:59 PM PDT 24
Finished	Jul 06 05:37:17 PM PDT 24
Peak memory	263672 kb
Host	smart-4f45a011-9808-4a0c-9675-4726400fc252
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207968431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.2207968431
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2467906290
Short name	T1152
Test name
Test status
Simulation time	17446100 ps
CPU time	14.2 seconds
Started	Jul 06 05:36:57 PM PDT 24
Finished	Jul 06 05:37:11 PM PDT 24
Peak memory	261108 kb
Host	smart-7c36c999-8db5-45a2-b965-6133178b24ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467906290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2 467906290
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2687115656
Short name	T1178
Test name
Test status
Simulation time	843149300 ps
CPU time	29.59 seconds
Started	Jul 06 05:37:03 PM PDT 24
Finished	Jul 06 05:37:32 PM PDT 24
Peak memory	261244 kb
Host	smart-964477bf-f21f-4d6d-afd8-6a44e97651c9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687115656 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.2687115656
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1343354139
Short name	T1218
Test name
Test status
Simulation time	11951000 ps
CPU time	16.2 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:14 PM PDT 24
Peak memory	252892 kb
Host	smart-ddfc9fbb-993a-41f9-aad5-e9e86cc154d9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343354139 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1343354139
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2833931641
Short name	T1215
Test name
Test status
Simulation time	37264500 ps
CPU time	13.34 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:11 PM PDT 24
Peak memory	252800 kb
Host	smart-d7d9e7c3-6b9a-470c-9f20-38c65a70f230
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833931641 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2833931641
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.256321503
Short name	T209
Test name
Test status
Simulation time	35996200 ps
CPU time	17.2 seconds
Started	Jul 06 05:36:58 PM PDT 24
Finished	Jul 06 05:37:16 PM PDT 24
Peak memory	263720 kb
Host	smart-bbe7e9d4-e222-4e53-8f14-cb03ad270f37
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256321503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.256321503
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3394145100
Short name	T243
Test name
Test status
Simulation time	31239900 ps
CPU time	16.86 seconds
Started	Jul 06 05:37:09 PM PDT 24
Finished	Jul 06 05:37:26 PM PDT 24
Peak memory	271356 kb
Host	smart-28bf28ca-1a2d-40a1-8d5d-a4ced7654cfe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394145100 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3394145100
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3660315543
Short name	T67
Test name
Test status
Simulation time	134381500 ps
CPU time	17.59 seconds
Started	Jul 06 05:37:02 PM PDT 24
Finished	Jul 06 05:37:19 PM PDT 24
Peak memory	263728 kb
Host	smart-31ea2678-be61-426e-83b8-5e77926228e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660315543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.3660315543
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.435868518
Short name	T1159
Test name
Test status
Simulation time	16058300 ps
CPU time	13.33 seconds
Started	Jul 06 05:37:00 PM PDT 24
Finished	Jul 06 05:37:14 PM PDT 24
Peak memory	260988 kb
Host	smart-f70d65a6-2a3c-4211-8b75-47271a02a74c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435868518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.435868518
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3710880600
Short name	T297
Test name
Test status
Simulation time	3577989700 ps
CPU time	36.33 seconds
Started	Jul 06 05:37:01 PM PDT 24
Finished	Jul 06 05:37:37 PM PDT 24
Peak memory	263752 kb
Host	smart-a21fa1f1-c349-4e68-a3e1-0eb0952935b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710880600 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3710880600
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2832925644
Short name	T1237
Test name
Test status
Simulation time	53737400 ps
CPU time	15.49 seconds
Started	Jul 06 05:37:00 PM PDT 24
Finished	Jul 06 05:37:16 PM PDT 24
Peak memory	253056 kb
Host	smart-e4b8d6b7-6592-4b3f-a086-7e61dd56943b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832925644 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2832925644
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.475971769
Short name	T1166
Test name
Test status
Simulation time	19567700 ps
CPU time	15.84 seconds
Started	Jul 06 05:37:02 PM PDT 24
Finished	Jul 06 05:37:18 PM PDT 24
Peak memory	252940 kb
Host	smart-9b896f5c-c234-47c8-8f5f-d2ff1a978eb8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475971769 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.475971769
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1342058073
Short name	T242
Test name
Test status
Simulation time	1316769800 ps
CPU time	912.37 seconds
Started	Jul 06 05:37:02 PM PDT 24
Finished	Jul 06 05:52:15 PM PDT 24
Peak memory	263760 kb
Host	smart-1dca96aa-9b2c-433c-8126-0d6eb91fab6a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342058073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl _tl_intg_err.1342058073
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.206364167
Short name	T669
Test name
Test status
Simulation time	129902500 ps
CPU time	14.24 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:49:11 PM PDT 24
Peak memory	258332 kb
Host	smart-b862d6c4-9821-4088-9971-62d55ed48262
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206364167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.206364167
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.35195450
Short name	T999
Test name
Test status
Simulation time	62082700 ps
CPU time	13.74 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:49:10 PM PDT 24
Peak memory	261540 kb
Host	smart-894ecd18-2eb2-488e-a54a-7f1a035e43af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35195450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ= flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.f lash_ctrl_config_regwen.35195450
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.4244418886
Short name	T865
Test name
Test status
Simulation time	97727900 ps
CPU time	13.4 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 05:49:03 PM PDT 24
Peak memory	284292 kb
Host	smart-6ead3121-ae8e-4fdc-990d-974e59dc9537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244418886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.4244418886
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.2804230780
Short name	T168
Test name
Test status
Simulation time	2702841800 ps
CPU time	451.26 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:56:20 PM PDT 24
Peak memory	263436 kb
Host	smart-6775acbe-c067-4084-b22b-6e9dc3d5db24
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2804230780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2804230780
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.3005339800
Short name	T800
Test name
Test status
Simulation time	1256085900 ps
CPU time	758.56 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 06:01:25 PM PDT 24
Peak memory	272816 kb
Host	smart-86b41539-910e-4d9b-93ca-8837407577c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005339800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3005339800
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.3067519478
Short name	T564
Test name
Test status
Simulation time	604712600 ps
CPU time	25.21 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 05:49:15 PM PDT 24
Peak memory	262480 kb
Host	smart-55f92642-eb66-4762-9400-ece52b4e1e4c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067519478 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3067519478
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.1480380368
Short name	T88
Test name
Test status
Simulation time	706966600 ps
CPU time	41.54 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:49:36 PM PDT 24
Peak memory	263016 kb
Host	smart-07166ae3-7df9-41c7-a23c-8f98395a7dec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480380368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.1480380368
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.1443520457
Short name	T874
Test name
Test status
Simulation time	62632500 ps
CPU time	30.31 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:49:28 PM PDT 24
Peak memory	275596 kb
Host	smart-fa8956d8-a4e9-4b2d-a7bf-d2a859b567d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443520457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1443520457
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2902040042
Short name	T199
Test name
Test status
Simulation time	312900283800 ps
CPU time	2703.62 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 06:33:54 PM PDT 24
Peak memory	264100 kb
Host	smart-51fca38f-79c0-4ab0-9121-940312352ace
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902040042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_host_ctrl_arb.2902040042
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.204400800
Short name	T728
Test name
Test status
Simulation time	10066100800 ps
CPU time	48.11 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:49:45 PM PDT 24
Peak memory	274484 kb
Host	smart-9e4c3ec8-cf41-410b-95a9-c355ab37203b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204400800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.204400800
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.3503884537
Short name	T871
Test name
Test status
Simulation time	83716712200 ps
CPU time	2003.66 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 06:22:13 PM PDT 24
Peak memory	265008 kb
Host	smart-1d9424c6-2b9b-40bb-884e-c7a1cff36957
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503884537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.3503884537
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3664314585
Short name	T602
Test name
Test status
Simulation time	80141421300 ps
CPU time	911.79 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 06:03:58 PM PDT 24
Peak memory	261008 kb
Host	smart-72e40937-e562-4935-85b1-46fd08c6bd63
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664314585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.3664314585
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3899089031
Short name	T308
Test name
Test status
Simulation time	1552266400 ps
CPU time	130.69 seconds
Started	Jul 06 05:48:45 PM PDT 24
Finished	Jul 06 05:50:56 PM PDT 24
Peak memory	262060 kb
Host	smart-5dacbbaf-e9f8-4d6e-9dcd-c4244230eec4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899089031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.3899089031
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.994897567
Short name	T657
Test name
Test status
Simulation time	3192926200 ps
CPU time	224.62 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:52:35 PM PDT 24
Peak memory	284900 kb
Host	smart-c4cd619e-3bad-4ef1-8e77-7e3805c52577
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994897567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_intr_rd.994897567
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3534348409
Short name	T987
Test name
Test status
Simulation time	108450736100 ps
CPU time	367.87 seconds
Started	Jul 06 05:48:53 PM PDT 24
Finished	Jul 06 05:55:02 PM PDT 24
Peak memory	291796 kb
Host	smart-a57e61c2-78b6-4ad9-97db-52e3726c21bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534348409 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3534348409
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.3985691221
Short name	T1051
Test name
Test status
Simulation time	10535562300 ps
CPU time	74.76 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:50:11 PM PDT 24
Peak memory	260716 kb
Host	smart-43a97ee7-751e-49fc-ba98-7a06d44e345b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985691221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.3985691221
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3554880399
Short name	T737
Test name
Test status
Simulation time	39095560800 ps
CPU time	160.09 seconds
Started	Jul 06 05:48:53 PM PDT 24
Finished	Jul 06 05:51:34 PM PDT 24
Peak memory	260452 kb
Host	smart-dd3c9d53-a366-474b-9d0a-e38a3c397ce4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355 4880399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3554880399
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.47352297
Short name	T153
Test name
Test status
Simulation time	1695758400 ps
CPU time	66.06 seconds
Started	Jul 06 05:48:47 PM PDT 24
Finished	Jul 06 05:49:54 PM PDT 24
Peak memory	262628 kb
Host	smart-ac808fb9-e07e-42e8-bdb7-5cecbf06189e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47352297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.47352297
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.143153231
Short name	T1071
Test name
Test status
Simulation time	15484300 ps
CPU time	13.58 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:49:09 PM PDT 24
Peak memory	259908 kb
Host	smart-4ba61367-5053-457d-9fc0-d08778c22425
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143153231 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.143153231
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.3936807666
Short name	T155
Test name
Test status
Simulation time	24628510700 ps
CPU time	293.67 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:53:42 PM PDT 24
Peak memory	274884 kb
Host	smart-8b5a2b1f-4fd0-412c-a390-a77f7c7a04fb
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936807666 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.3936807666
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.908012999
Short name	T74
Test name
Test status
Simulation time	37404000 ps
CPU time	111.46 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 05:50:38 PM PDT 24
Peak memory	265168 kb
Host	smart-f45adc6e-ca79-43fe-b419-1315ee20ab73
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908012999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp _reset.908012999
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.3352445319
Short name	T638
Test name
Test status
Simulation time	5040103500 ps
CPU time	191.04 seconds
Started	Jul 06 05:48:51 PM PDT 24
Finished	Jul 06 05:52:03 PM PDT 24
Peak memory	281984 kb
Host	smart-e79347bd-fee7-4caf-ae87-0c6e0decbf9f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352445319 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3352445319
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2920813523
Short name	T793
Test name
Test status
Simulation time	15510700 ps
CPU time	14.09 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:49:12 PM PDT 24
Peak memory	265040 kb
Host	smart-90a98922-6972-4054-ac5f-7c65a2152fba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2920813523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2920813523
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.520183941
Short name	T536
Test name
Test status
Simulation time	252024100 ps
CPU time	279.71 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 05:53:26 PM PDT 24
Peak memory	263312 kb
Host	smart-afdd8020-0b87-4971-9753-275433a13493
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=520183941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.520183941
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.74534673
Short name	T216
Test name
Test status
Simulation time	23147400 ps
CPU time	14.16 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:49:16 PM PDT 24
Peak memory	265436 kb
Host	smart-5860b047-0c84-4cc6-903f-442e48e773da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74534673 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.74534673
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.3576222260
Short name	T574
Test name
Test status
Simulation time	2813706600 ps
CPU time	36.71 seconds
Started	Jul 06 05:48:54 PM PDT 24
Finished	Jul 06 05:49:31 PM PDT 24
Peak memory	260336 kb
Host	smart-3ebdb776-5951-4df7-8551-af464b25d1b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576222260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.3576222260
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.2158347852
Short name	T427
Test name
Test status
Simulation time	178181200 ps
CPU time	570.18 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:58:19 PM PDT 24
Peak memory	284060 kb
Host	smart-0fc6be36-c862-4f35-b98c-bce4e7682631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2158347852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2158347852
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3851957117
Short name	T1094
Test name
Test status
Simulation time	737220300 ps
CPU time	113.39 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 05:50:43 PM PDT 24
Peak memory	263064 kb
Host	smart-1b706797-581d-4c03-a874-33380ed96595
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3851957117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3851957117
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.3028523147
Short name	T505
Test name
Test status
Simulation time	240040700 ps
CPU time	29.01 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:49:25 PM PDT 24
Peak memory	280320 kb
Host	smart-4610a573-df52-4ea2-9e10-e3713cd03c65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028523147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.3028523147
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.114279477
Short name	T829
Test name
Test status
Simulation time	58042000 ps
CPU time	42.74 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:49:40 PM PDT 24
Peak memory	275772 kb
Host	smart-07b99be2-05eb-4484-be79-2c39ff7ee567
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114279477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_rd_ooo.114279477
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.4057525634
Short name	T345
Test name
Test status
Simulation time	125439700 ps
CPU time	31.51 seconds
Started	Jul 06 05:48:53 PM PDT 24
Finished	Jul 06 05:49:24 PM PDT 24
Peak memory	267492 kb
Host	smart-0b9a0b87-fbee-4ace-ac2f-a5adeed9f4da
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057525634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.4057525634
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.4173857150
Short name	T1049
Test name
Test status
Simulation time	44442600 ps
CPU time	14.32 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 05:49:00 PM PDT 24
Peak memory	258792 kb
Host	smart-bf32b94a-1cbe-4684-8e7b-64e04cde60d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4173857150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep .4173857150
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3535335722
Short name	T783
Test name
Test status
Simulation time	31501900 ps
CPU time	22.38 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:49:12 PM PDT 24
Peak memory	264940 kb
Host	smart-d0c213a9-f690-42ba-932c-4b46ae58be1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535335722 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3535335722
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.4015561025
Short name	T789
Test name
Test status
Simulation time	86908000 ps
CPU time	23.28 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:49:11 PM PDT 24
Peak memory	265076 kb
Host	smart-b9fa596a-03c4-46a9-9d23-f775bcf9ba6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015561025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.4015561025
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.1229166583
Short name	T921
Test name
Test status
Simulation time	1082222600 ps
CPU time	144.57 seconds
Started	Jul 06 05:48:47 PM PDT 24
Finished	Jul 06 05:51:12 PM PDT 24
Peak memory	281740 kb
Host	smart-b23bbb8d-f15d-40b5-992a-8411f87836b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229166583 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.1229166583
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.2045200497
Short name	T954
Test name
Test status
Simulation time	2474423300 ps
CPU time	163.15 seconds
Started	Jul 06 05:48:54 PM PDT 24
Finished	Jul 06 05:51:37 PM PDT 24
Peak memory	281880 kb
Host	smart-ce4b8829-8269-43d0-92c0-8c9dd72ff13f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2045200497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2045200497
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.2065288324
Short name	T226
Test name
Test status
Simulation time	6983585700 ps
CPU time	552.14 seconds
Started	Jul 06 05:48:47 PM PDT 24
Finished	Jul 06 05:57:59 PM PDT 24
Peak memory	309920 kb
Host	smart-ab17e313-a65e-41b8-bb1c-862d1601c822
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065288324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.2065288324
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.3571319616
Short name	T221
Test name
Test status
Simulation time	37025400 ps
CPU time	30.94 seconds
Started	Jul 06 05:48:51 PM PDT 24
Finished	Jul 06 05:49:22 PM PDT 24
Peak memory	268492 kb
Host	smart-0b32329c-54d4-45b3-bb39-069703c9e903
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571319616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_rw_evict.3571319616
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.661987261
Short name	T343
Test name
Test status
Simulation time	30374700 ps
CPU time	31.2 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:49:22 PM PDT 24
Peak memory	275704 kb
Host	smart-6b933dfa-aace-41cb-aefa-c1e38fa6fd34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661987261 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.661987261
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.3122308437
Short name	T1063
Test name
Test status
Simulation time	2327979900 ps
CPU time	67.72 seconds
Started	Jul 06 05:48:50 PM PDT 24
Finished	Jul 06 05:49:58 PM PDT 24
Peak memory	263120 kb
Host	smart-bf0ac480-227b-4c65-b331-85915e50a156
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3122308437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3122308437
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.310487972
Short name	T43
Test name
Test status
Simulation time	3079678000 ps
CPU time	80.34 seconds
Started	Jul 06 05:48:52 PM PDT 24
Finished	Jul 06 05:50:13 PM PDT 24
Peak memory	265460 kb
Host	smart-2594759e-fcc6-4d11-9311-e00f83612a68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310487972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr_address.310487972
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.686379748
Short name	T781
Test name
Test status
Simulation time	3140666700 ps
CPU time	77.22 seconds
Started	Jul 06 05:48:51 PM PDT 24
Finished	Jul 06 05:50:08 PM PDT 24
Peak memory	276332 kb
Host	smart-0c7dde3b-9975-48a4-a263-7a473127497a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686379748 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_counter.686379748
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.2872459601
Short name	T884
Test name
Test status
Simulation time	14446200 ps
CPU time	49.63 seconds
Started	Jul 06 05:48:47 PM PDT 24
Finished	Jul 06 05:49:37 PM PDT 24
Peak memory	271328 kb
Host	smart-5015c5c0-532a-48d2-8015-10aa278186d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872459601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2872459601
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.2153935459
Short name	T62
Test name
Test status
Simulation time	123860600 ps
CPU time	26 seconds
Started	Jul 06 05:48:48 PM PDT 24
Finished	Jul 06 05:49:14 PM PDT 24
Peak memory	259756 kb
Host	smart-9bdb1942-02aa-4736-b590-de4f90244a98
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153935459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2153935459
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.2882763586
Short name	T631
Test name
Test status
Simulation time	156170200 ps
CPU time	212.17 seconds
Started	Jul 06 05:48:54 PM PDT 24
Finished	Jul 06 05:52:26 PM PDT 24
Peak memory	273184 kb
Host	smart-09825ba3-e994-49e7-9b6a-c90b26f146fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882763586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.2882763586
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.301830673
Short name	T503
Test name
Test status
Simulation time	27555700 ps
CPU time	27.36 seconds
Started	Jul 06 05:48:46 PM PDT 24
Finished	Jul 06 05:49:14 PM PDT 24
Peak memory	262348 kb
Host	smart-f3c5086a-0896-491c-83b9-7e0c97d27e97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301830673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.301830673
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.36034979
Short name	T873
Test name
Test status
Simulation time	5534840300 ps
CPU time	231.73 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 05:52:41 PM PDT 24
Peak memory	260396 kb
Host	smart-a4665b73-c5b0-44c6-8ec6-5c8574eef625
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034979 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_wo.36034979
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.1688366504
Short name	T942
Test name
Test status
Simulation time	211881200 ps
CPU time	15.84 seconds
Started	Jul 06 05:48:49 PM PDT 24
Finished	Jul 06 05:49:05 PM PDT 24
Peak memory	265256 kb
Host	smart-f1eb1f7e-29ec-493b-b0c7-01ed33581802
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1688366504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe ep.1688366504
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.2893408092
Short name	T8
Test name
Test status
Simulation time	12669900 ps
CPU time	13.58 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:49:27 PM PDT 24
Peak memory	265372 kb
Host	smart-1c153199-5363-4776-919c-55d92935adf3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893408092 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2893408092
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.784976825
Short name	T813
Test name
Test status
Simulation time	59791600 ps
CPU time	13.71 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:49:21 PM PDT 24
Peak memory	259476 kb
Host	smart-af60733d-7816-4142-bef5-082c2145a241
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784976825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.784976825
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.2194148190
Short name	T589
Test name
Test status
Simulation time	47040400 ps
CPU time	13.38 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:21 PM PDT 24
Peak memory	274924 kb
Host	smart-ee1cefb6-63d1-44a0-9215-977b363ea3ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194148190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.2194148190
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.3582854697
Short name	T514
Test name
Test status
Simulation time	32630400 ps
CPU time	21.76 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:49:29 PM PDT 24
Peak memory	265596 kb
Host	smart-9ec12c6b-b30a-4afa-ac04-ce594fe107df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582854697 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.3582854697
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.3713264453
Short name	T173
Test name
Test status
Simulation time	9530033400 ps
CPU time	648.87 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:59:51 PM PDT 24
Peak memory	263376 kb
Host	smart-52d08ac3-4e82-4500-a65a-024d4f289f3a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3713264453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3713264453
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.1829215740
Short name	T236
Test name
Test status
Simulation time	75268024500 ps
CPU time	2290.97 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 06:27:15 PM PDT 24
Peak memory	262780 kb
Host	smart-c6d6a2ad-458f-47d5-a0a8-b0cc4a0f4bed
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1829215740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.1829215740
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.1047259914
Short name	T94
Test name
Test status
Simulation time	1824735700 ps
CPU time	2763.28 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 06:35:02 PM PDT 24
Peak memory	263484 kb
Host	smart-6f68706a-9167-4b14-8759-609a99a5fc16
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047259914 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1047259914
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.3318994825
Short name	T52
Test name
Test status
Simulation time	156906200 ps
CPU time	23.38 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:49:21 PM PDT 24
Peak memory	263588 kb
Host	smart-3f4549d7-32d0-49d0-9496-e19b6e58ca98
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318994825 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.3318994825
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.1440905772
Short name	T87
Test name
Test status
Simulation time	1262455600 ps
CPU time	42.23 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:49:49 PM PDT 24
Peak memory	265304 kb
Host	smart-0d72f6ee-d940-44ac-9760-46984fd5641b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440905772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.1440905772
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.2937372941
Short name	T139
Test name
Test status
Simulation time	49892637100 ps
CPU time	4308.18 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 07:00:49 PM PDT 24
Peak memory	275072 kb
Host	smart-93704795-0fd1-4154-b955-fb6d308c726f
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937372941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.2937372941
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.1133495044
Short name	T500
Test name
Test status
Simulation time	64687500 ps
CPU time	28.55 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:37 PM PDT 24
Peak memory	268444 kb
Host	smart-5e34ca42-c586-4d9a-84a6-d626a6ef0d8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133495044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.1133495044
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.993341980
Short name	T85
Test name
Test status
Simulation time	482568594000 ps
CPU time	2145.98 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 06:24:43 PM PDT 24
Peak memory	264180 kb
Host	smart-8706e03c-dcb0-4617-8d57-287d2740638a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993341980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.flash_ctrl_host_ctrl_arb.993341980
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.3235716911
Short name	T470
Test name
Test status
Simulation time	120098400 ps
CPU time	91.55 seconds
Started	Jul 06 05:48:57 PM PDT 24
Finished	Jul 06 05:50:29 PM PDT 24
Peak memory	262636 kb
Host	smart-3f1aee4b-1a06-4653-99e9-a30e9e9f87a8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3235716911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3235716911
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.303418064
Short name	T502
Test name
Test status
Simulation time	15677700 ps
CPU time	13.47 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:49:19 PM PDT 24
Peak memory	265032 kb
Host	smart-1bf1f067-705f-4c99-a261-2688fffe76f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303418064 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.303418064
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2149121042
Short name	T187
Test name
Test status
Simulation time	190182026600 ps
CPU time	797.26 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 06:02:13 PM PDT 24
Peak memory	264492 kb
Host	smart-2ceedd35-f2c0-4365-9071-0c1876ed621f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149121042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.2149121042
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3418442760
Short name	T744
Test name
Test status
Simulation time	9779778800 ps
CPU time	194.84 seconds
Started	Jul 06 05:48:59 PM PDT 24
Finished	Jul 06 05:52:14 PM PDT 24
Peak memory	262780 kb
Host	smart-ede9630e-51c6-45d3-8b6d-7aac1ad0f09c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418442760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.3418442760
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.341114331
Short name	T771
Test name
Test status
Simulation time	651560300 ps
CPU time	142.1 seconds
Started	Jul 06 05:49:03 PM PDT 24
Finished	Jul 06 05:51:25 PM PDT 24
Peak memory	285568 kb
Host	smart-7c29bf01-f4ec-42d3-9450-a87aa43c8205
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341114331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash _ctrl_intr_rd.341114331
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2848780705
Short name	T811
Test name
Test status
Simulation time	23987865200 ps
CPU time	286.79 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:53:49 PM PDT 24
Peak memory	289992 kb
Host	smart-dd922b53-f62b-4e83-9709-cb26f3a4bf7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848780705 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2848780705
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.3967824115
Short name	T645
Test name
Test status
Simulation time	7958963200 ps
CPU time	70.59 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:50:14 PM PDT 24
Peak memory	261588 kb
Host	smart-b6b66095-525b-4ad8-af5a-f2f10969a675
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967824115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_wr.3967824115
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3871009365
Short name	T757
Test name
Test status
Simulation time	26111904800 ps
CPU time	211.38 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:52:33 PM PDT 24
Peak memory	260476 kb
Host	smart-16666d62-c34c-40f4-bb25-709846a3bf02
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387 1009365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3871009365
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2779651216
Short name	T672
Test name
Test status
Simulation time	45999200 ps
CPU time	13.2 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:49:27 PM PDT 24
Peak memory	264976 kb
Host	smart-855b7753-b125-434b-b4b6-ac2fa8b82243
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779651216 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2779651216
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.3478664452
Short name	T99
Test name
Test status
Simulation time	949844200 ps
CPU time	72.51 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:50:16 PM PDT 24
Peak memory	260700 kb
Host	smart-29f84da3-116c-4b01-a444-03b1f25c8aab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3478664452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3478664452
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.2927391299
Short name	T434
Test name
Test status
Simulation time	137722400 ps
CPU time	111.99 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:50:49 PM PDT 24
Peak memory	264848 kb
Host	smart-99e49004-26ef-4225-9895-3174a91dfb98
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927391299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.2927391299
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.2679110292
Short name	T780
Test name
Test status
Simulation time	5016738600 ps
CPU time	158.26 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:51:41 PM PDT 24
Peak memory	281740 kb
Host	smart-ec1a669d-bb86-4935-ae21-9d2ec01c80c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679110292 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2679110292
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1049602416
Short name	T547
Test name
Test status
Simulation time	17155600 ps
CPU time	14.13 seconds
Started	Jul 06 05:49:05 PM PDT 24
Finished	Jul 06 05:49:20 PM PDT 24
Peak memory	265172 kb
Host	smart-0a30f317-85aa-4365-a5dc-bf898fd612b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1049602416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1049602416
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.720409287
Short name	T646
Test name
Test status
Simulation time	94738200 ps
CPU time	195.02 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:52:11 PM PDT 24
Peak memory	263184 kb
Host	smart-8d111675-43d0-44ca-ac9a-7ec9d94776ea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=720409287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.720409287
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.288219657
Short name	T859
Test name
Test status
Simulation time	15566833000 ps
CPU time	224.78 seconds
Started	Jul 06 05:49:03 PM PDT 24
Finished	Jul 06 05:52:48 PM PDT 24
Peak memory	260664 kb
Host	smart-1e8600d5-fcb9-44a4-a708-88897825b2d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288219657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_prog_reset.288219657
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.396458968
Short name	T509
Test name
Test status
Simulation time	87808100 ps
CPU time	97.23 seconds
Started	Jul 06 05:48:58 PM PDT 24
Finished	Jul 06 05:50:35 PM PDT 24
Peak memory	262800 kb
Host	smart-92c01ace-7ca8-4396-8867-a316091fb48e
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=396458968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.396458968
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.2666200288
Short name	T435
Test name
Test status
Simulation time	223490800 ps
CPU time	29.27 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	275680 kb
Host	smart-f22503f9-aa7d-4a8c-b6cb-d188953163fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666200288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.2666200288
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3182669577
Short name	T376
Test name
Test status
Simulation time	59423400 ps
CPU time	22.69 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:49:24 PM PDT 24
Peak memory	265412 kb
Host	smart-5469189b-0c25-4568-bcdf-dce47a4c47de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182669577 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3182669577
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1760573961
Short name	T851
Test name
Test status
Simulation time	25041400 ps
CPU time	22.64 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:49:25 PM PDT 24
Peak memory	265100 kb
Host	smart-bce06b9c-9f66-46c6-99da-8ef71662aee3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760573961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.1760573961
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.2473309322
Short name	T200
Test name
Test status
Simulation time	77390113200 ps
CPU time	923.52 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 06:04:30 PM PDT 24
Peak memory	263548 kb
Host	smart-198f5f89-caf1-44fa-a0c1-c5cf6d4afa79
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473309322 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2473309322
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.922577628
Short name	T220
Test name
Test status
Simulation time	578556100 ps
CPU time	127.43 seconds
Started	Jul 06 05:48:59 PM PDT 24
Finished	Jul 06 05:51:07 PM PDT 24
Peak memory	289236 kb
Host	smart-56d3cff2-d5a3-43ab-b319-f6f92c3adb68
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922577628 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_ro.922577628
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.3417542008
Short name	T5
Test name
Test status
Simulation time	726497300 ps
CPU time	171.66 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:51:53 PM PDT 24
Peak memory	283024 kb
Host	smart-18f82a10-e194-42ec-9ddd-0d2fcf711fa1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3417542008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3417542008
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.2598107399
Short name	T857
Test name
Test status
Simulation time	577951000 ps
CPU time	152.08 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:51:34 PM PDT 24
Peak memory	295204 kb
Host	smart-5562d842-4d3e-4a43-8cbe-687c389cdecf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598107399 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2598107399
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.3125223891
Short name	T694
Test name
Test status
Simulation time	4864815000 ps
CPU time	782.42 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 06:02:04 PM PDT 24
Peak memory	334596 kb
Host	smart-701e5725-0528-43bb-9547-0360de832f90
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125223891 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_rw_derr.3125223891
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.2548945374
Short name	T586
Test name
Test status
Simulation time	27355800 ps
CPU time	30.41 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:49:32 PM PDT 24
Peak memory	275672 kb
Host	smart-18e083f8-c1d0-4d73-a727-3037f903a800
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548945374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_rw_evict.2548945374
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.3507780711
Short name	T526
Test name
Test status
Simulation time	77548200 ps
CPU time	31.2 seconds
Started	Jul 06 05:49:02 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	275712 kb
Host	smart-95e882fe-2f79-49b1-ab7b-f772fc5cbb6f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507780711 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.3507780711
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.4231162596
Short name	T103
Test name
Test status
Simulation time	8620518900 ps
CPU time	661.8 seconds
Started	Jul 06 05:49:03 PM PDT 24
Finished	Jul 06 06:00:05 PM PDT 24
Peak memory	320956 kb
Host	smart-f1984e7a-fce9-41e5-8390-85cf2d3f7cc7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231162596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s err.4231162596
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.313251782
Short name	T59
Test name
Test status
Simulation time	4271673100 ps
CPU time	4735.02 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 07:08:00 PM PDT 24
Peak memory	289624 kb
Host	smart-d6841e76-673e-436b-9d79-3f045aeb5a91
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313251782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.313251782
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.3920264098
Short name	T843
Test name
Test status
Simulation time	500424200 ps
CPU time	62.73 seconds
Started	Jul 06 05:49:05 PM PDT 24
Finished	Jul 06 05:50:08 PM PDT 24
Peak memory	264520 kb
Host	smart-d52c73c8-de9c-448c-a500-8f8f1a735bd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920264098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3920264098
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.2225760274
Short name	T448
Test name
Test status
Simulation time	2715387200 ps
CPU time	77.73 seconds
Started	Jul 06 05:49:00 PM PDT 24
Finished	Jul 06 05:50:18 PM PDT 24
Peak memory	273612 kb
Host	smart-a19682a5-2c6f-4931-a957-2c8733bd3ab4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225760274 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.2225760274
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.500420192
Short name	T1015
Test name
Test status
Simulation time	2359923600 ps
CPU time	78.43 seconds
Started	Jul 06 05:48:59 PM PDT 24
Finished	Jul 06 05:50:18 PM PDT 24
Peak memory	276428 kb
Host	smart-9a465b64-cd99-4299-a992-d92f9c130561
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500420192 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_counter.500420192
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.3090928197
Short name	T1091
Test name
Test status
Simulation time	709347600 ps
CPU time	219.66 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:52:35 PM PDT 24
Peak memory	277736 kb
Host	smart-52627a3a-b27f-4f06-b3a8-cc5efa0dd0a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090928197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3090928197
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.532852527
Short name	T417
Test name
Test status
Simulation time	16353600 ps
CPU time	26.76 seconds
Started	Jul 06 05:48:56 PM PDT 24
Finished	Jul 06 05:49:23 PM PDT 24
Peak memory	259740 kb
Host	smart-7acc8f26-1141-4a45-8437-4a4162375698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532852527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.532852527
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.3300629123
Short name	T580
Test name
Test status
Simulation time	415573500 ps
CPU time	1221.16 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 06:09:28 PM PDT 24
Peak memory	289824 kb
Host	smart-13089e18-2571-4794-bd0b-0f9a6cba0542
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300629123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.3300629123
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.1803917131
Short name	T1077
Test name
Test status
Simulation time	26560100 ps
CPU time	27.19 seconds
Started	Jul 06 05:48:55 PM PDT 24
Finished	Jul 06 05:49:23 PM PDT 24
Peak memory	262236 kb
Host	smart-6acf0ded-3c3f-411b-8b32-cac74bb01864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803917131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1803917131
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.7415050
Short name	T652
Test name
Test status
Simulation time	9230175500 ps
CPU time	193.47 seconds
Started	Jul 06 05:49:01 PM PDT 24
Finished	Jul 06 05:52:15 PM PDT 24
Peak memory	259476 kb
Host	smart-e6af0761-db4c-48e1-8153-57df056db9a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7415050 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_wo.7415050
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.1123580909
Short name	T817
Test name
Test status
Simulation time	108861700 ps
CPU time	13.75 seconds
Started	Jul 06 05:51:29 PM PDT 24
Finished	Jul 06 05:51:43 PM PDT 24
Peak memory	258160 kb
Host	smart-082a760d-a11b-4bb3-85e4-f3b0042d0951
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123580909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test. 1123580909
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.1071978808
Short name	T791
Test name
Test status
Simulation time	49127400 ps
CPU time	15.87 seconds
Started	Jul 06 05:51:23 PM PDT 24
Finished	Jul 06 05:51:39 PM PDT 24
Peak memory	284432 kb
Host	smart-4cba23f7-597b-4147-b0e8-f82ad869137b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071978808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1071978808
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.420413114
Short name	T46
Test name
Test status
Simulation time	12780600 ps
CPU time	20.17 seconds
Started	Jul 06 05:51:24 PM PDT 24
Finished	Jul 06 05:51:44 PM PDT 24
Peak memory	265648 kb
Host	smart-74eb3a4f-7e28-4a5b-b4d0-7af77f2d4150
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420413114 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.420413114
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.4101629649
Short name	T802
Test name
Test status
Simulation time	15859600 ps
CPU time	13.63 seconds
Started	Jul 06 05:51:24 PM PDT 24
Finished	Jul 06 05:51:38 PM PDT 24
Peak memory	265348 kb
Host	smart-90fb40af-1818-4569-b8b4-5e0a71fa6503
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101629649 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.4101629649
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1210478596
Short name	T579
Test name
Test status
Simulation time	40125137500 ps
CPU time	912.07 seconds
Started	Jul 06 05:51:21 PM PDT 24
Finished	Jul 06 06:06:33 PM PDT 24
Peak memory	263884 kb
Host	smart-0caba47f-b8bf-40ba-86eb-cf508bc1459c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210478596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.1210478596
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.589527005
Short name	T750
Test name
Test status
Simulation time	10825399300 ps
CPU time	145.95 seconds
Started	Jul 06 05:51:19 PM PDT 24
Finished	Jul 06 05:53:45 PM PDT 24
Peak memory	262768 kb
Host	smart-05a724a7-d0c5-4e05-87a2-ff29b535d5fe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589527005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h w_sec_otp.589527005
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.3348151054
Short name	T713
Test name
Test status
Simulation time	598510100 ps
CPU time	124.13 seconds
Started	Jul 06 05:51:22 PM PDT 24
Finished	Jul 06 05:53:26 PM PDT 24
Peak memory	293032 kb
Host	smart-bb7386aa-7a33-45a9-a79e-924ad7de6944
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348151054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.3348151054
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2195022990
Short name	T654
Test name
Test status
Simulation time	19910048600 ps
CPU time	314.67 seconds
Started	Jul 06 05:51:20 PM PDT 24
Finished	Jul 06 05:56:35 PM PDT 24
Peak memory	285056 kb
Host	smart-6d052f82-dfe6-48b1-aed1-621454d5ea18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195022990 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2195022990
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.1683804546
Short name	T719
Test name
Test status
Simulation time	12218454200 ps
CPU time	68.02 seconds
Started	Jul 06 05:51:21 PM PDT 24
Finished	Jul 06 05:52:29 PM PDT 24
Peak memory	262644 kb
Host	smart-9f35893e-4ebb-4de9-8364-1aaea404380a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683804546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1 683804546
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.2088112577
Short name	T795
Test name
Test status
Simulation time	9196030000 ps
CPU time	246.67 seconds
Started	Jul 06 05:51:19 PM PDT 24
Finished	Jul 06 05:55:26 PM PDT 24
Peak memory	275128 kb
Host	smart-5866d130-99d8-4f12-9407-ecc2ee3dbafd
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088112577 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.2088112577
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.289135015
Short name	T134
Test name
Test status
Simulation time	39929200 ps
CPU time	110.01 seconds
Started	Jul 06 05:51:20 PM PDT 24
Finished	Jul 06 05:53:10 PM PDT 24
Peak memory	261036 kb
Host	smart-dae4cc94-00a5-4d23-893e-4899ad0fbf0e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289135015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot p_reset.289135015
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3609593813
Short name	T647
Test name
Test status
Simulation time	421845300 ps
CPU time	361.7 seconds
Started	Jul 06 05:51:17 PM PDT 24
Finished	Jul 06 05:57:19 PM PDT 24
Peak memory	263020 kb
Host	smart-81feb48f-1962-4d1a-a084-4e5dbea0bf46
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3609593813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3609593813
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.3869980160
Short name	T687
Test name
Test status
Simulation time	39578100 ps
CPU time	13.71 seconds
Started	Jul 06 05:51:20 PM PDT 24
Finished	Jul 06 05:51:34 PM PDT 24
Peak memory	259172 kb
Host	smart-755dca17-2aa5-43b3-8622-1baf56f88d03
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869980160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.flash_ctrl_prog_reset.3869980160
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.2619231832
Short name	T1081
Test name
Test status
Simulation time	293340900 ps
CPU time	274.35 seconds
Started	Jul 06 05:51:16 PM PDT 24
Finished	Jul 06 05:55:51 PM PDT 24
Peak memory	281624 kb
Host	smart-214c3f7d-b73f-4eed-bf7a-0ae92179fdfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2619231832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2619231832
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.1568228270
Short name	T340
Test name
Test status
Simulation time	125487800 ps
CPU time	35.11 seconds
Started	Jul 06 05:51:24 PM PDT 24
Finished	Jul 06 05:52:00 PM PDT 24
Peak memory	268488 kb
Host	smart-1c7edad9-b680-474b-938c-765428d391c6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568228270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.1568228270
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.541691996
Short name	T224
Test name
Test status
Simulation time	411234800 ps
CPU time	123.6 seconds
Started	Jul 06 05:51:21 PM PDT 24
Finished	Jul 06 05:53:25 PM PDT 24
Peak memory	291508 kb
Host	smart-19308aea-3dd2-498f-9b86-50b875b46f33
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541691996 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.flash_ctrl_ro.541691996
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.868642520
Short name	T1000
Test name
Test status
Simulation time	5895232300 ps
CPU time	517.03 seconds
Started	Jul 06 05:51:19 PM PDT 24
Finished	Jul 06 05:59:56 PM PDT 24
Peak memory	309804 kb
Host	smart-e8ebfe30-0fd8-4644-a838-7a29c7650c75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868642520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.868642520
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.544992817
Short name	T686
Test name
Test status
Simulation time	45242200 ps
CPU time	28.1 seconds
Started	Jul 06 05:51:21 PM PDT 24
Finished	Jul 06 05:51:49 PM PDT 24
Peak memory	275680 kb
Host	smart-9f474e96-b654-4c65-8e4c-181d1d3ab19c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544992817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_rw_evict.544992817
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.2009751514
Short name	T418
Test name
Test status
Simulation time	7417846800 ps
CPU time	65.28 seconds
Started	Jul 06 05:51:26 PM PDT 24
Finished	Jul 06 05:52:31 PM PDT 24
Peak memory	264872 kb
Host	smart-13e26760-49a1-47eb-b549-c8e9120ab2a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009751514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2009751514
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.982733808
Short name	T508
Test name
Test status
Simulation time	18640200 ps
CPU time	77.88 seconds
Started	Jul 06 05:51:18 PM PDT 24
Finished	Jul 06 05:52:36 PM PDT 24
Peak memory	276700 kb
Host	smart-67d62461-1b3c-4d0a-8389-0c354b86bff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982733808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.982733808
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.3833685889
Short name	T634
Test name
Test status
Simulation time	10539363400 ps
CPU time	176.68 seconds
Started	Jul 06 05:51:20 PM PDT 24
Finished	Jul 06 05:54:17 PM PDT 24
Peak memory	265248 kb
Host	smart-9446a5f8-5482-447a-afba-80ae08ed55fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833685889 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.3833685889
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.1104343234
Short name	T952
Test name
Test status
Simulation time	85792700 ps
CPU time	13.9 seconds
Started	Jul 06 05:51:47 PM PDT 24
Finished	Jul 06 05:52:01 PM PDT 24
Peak memory	265208 kb
Host	smart-dd1ddb34-a681-4340-95ab-5dc9fcf7a018
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104343234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 1104343234
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.1474094537
Short name	T480
Test name
Test status
Simulation time	15997800 ps
CPU time	16.13 seconds
Started	Jul 06 05:51:40 PM PDT 24
Finished	Jul 06 05:51:56 PM PDT 24
Peak memory	284280 kb
Host	smart-01caa31e-4b30-4261-8542-3fe88757c4d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474094537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1474094537
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.7116960
Short name	T507
Test name
Test status
Simulation time	270274960200 ps
CPU time	990.52 seconds
Started	Jul 06 05:51:31 PM PDT 24
Finished	Jul 06 06:08:02 PM PDT 24
Peak memory	264508 kb
Host	smart-eaf29f3e-508d-498b-b4f0-75fa7ad00cfa
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7116960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_reset.7116960
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3789634842
Short name	T991
Test name
Test status
Simulation time	1678688800 ps
CPU time	65.28 seconds
Started	Jul 06 05:51:28 PM PDT 24
Finished	Jul 06 05:52:34 PM PDT 24
Peak memory	260972 kb
Host	smart-61b1e65a-dd4d-41f2-937a-e7a4fd792413
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789634842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ hw_sec_otp.3789634842
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.1582446080
Short name	T929
Test name
Test status
Simulation time	4450666900 ps
CPU time	143.47 seconds
Started	Jul 06 05:51:35 PM PDT 24
Finished	Jul 06 05:53:59 PM PDT 24
Peak memory	291000 kb
Host	smart-494ce044-77e7-44ae-9fd1-3ef2d6056b83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582446080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_intr_rd.1582446080
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.3751166058
Short name	T900
Test name
Test status
Simulation time	2144931400 ps
CPU time	72.74 seconds
Started	Jul 06 05:51:36 PM PDT 24
Finished	Jul 06 05:52:49 PM PDT 24
Peak memory	262656 kb
Host	smart-5a826893-9db5-47fe-bead-25937d7c37ca
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751166058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3 751166058
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3547386147
Short name	T1114
Test name
Test status
Simulation time	46851600 ps
CPU time	13.91 seconds
Started	Jul 06 05:51:42 PM PDT 24
Finished	Jul 06 05:51:56 PM PDT 24
Peak memory	265404 kb
Host	smart-2964dac3-d2d8-46f0-a6f7-8479cf79069f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547386147 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3547386147
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.2515287468
Short name	T747
Test name
Test status
Simulation time	21264191300 ps
CPU time	172.26 seconds
Started	Jul 06 05:51:29 PM PDT 24
Finished	Jul 06 05:54:21 PM PDT 24
Peak memory	262956 kb
Host	smart-3cd92ada-4b85-4fa8-a25e-216f70769657
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515287468 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.2515287468
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.1802251886
Short name	T576
Test name
Test status
Simulation time	107791600 ps
CPU time	132.62 seconds
Started	Jul 06 05:51:31 PM PDT 24
Finished	Jul 06 05:53:44 PM PDT 24
Peak memory	259920 kb
Host	smart-c0e5e21f-9af8-4a2d-93e8-531af7eec431
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802251886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.1802251886
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.1556584603
Short name	T761
Test name
Test status
Simulation time	10221019000 ps
CPU time	606.14 seconds
Started	Jul 06 05:51:31 PM PDT 24
Finished	Jul 06 06:01:37 PM PDT 24
Peak memory	263148 kb
Host	smart-d3388637-7c04-4475-bf20-a8d7635eb73b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1556584603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1556584603
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.1890535270
Short name	T997
Test name
Test status
Simulation time	18098800 ps
CPU time	13.46 seconds
Started	Jul 06 05:51:41 PM PDT 24
Finished	Jul 06 05:51:55 PM PDT 24
Peak memory	259120 kb
Host	smart-fbd0a999-59e7-42e1-b22c-4b75b9b99df9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890535270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.1890535270
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.3112095495
Short name	T556
Test name
Test status
Simulation time	81603000 ps
CPU time	107.28 seconds
Started	Jul 06 05:51:29 PM PDT 24
Finished	Jul 06 05:53:16 PM PDT 24
Peak memory	278620 kb
Host	smart-e9c04dad-eb17-4265-9034-b18daedd38a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112095495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3112095495
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.4077706753
Short name	T1079
Test name
Test status
Simulation time	329914700 ps
CPU time	35.05 seconds
Started	Jul 06 05:51:42 PM PDT 24
Finished	Jul 06 05:52:17 PM PDT 24
Peak memory	275720 kb
Host	smart-545c2bab-2718-48b4-90b8-603a6768b1b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077706753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.4077706753
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.2987255289
Short name	T916
Test name
Test status
Simulation time	520806600 ps
CPU time	133.78 seconds
Started	Jul 06 05:51:35 PM PDT 24
Finished	Jul 06 05:53:49 PM PDT 24
Peak memory	281724 kb
Host	smart-1912df02-32c8-43d4-90d4-8811377fa28b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987255289 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.2987255289
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.2385507583
Short name	T955
Test name
Test status
Simulation time	8589489800 ps
CPU time	545.03 seconds
Started	Jul 06 05:51:40 PM PDT 24
Finished	Jul 06 06:00:45 PM PDT 24
Peak memory	309540 kb
Host	smart-a95f271a-c5bb-49d7-b0da-3e1206aca9b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385507583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.2385507583
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.114519176
Short name	T30
Test name
Test status
Simulation time	30244600 ps
CPU time	29.2 seconds
Started	Jul 06 05:51:41 PM PDT 24
Finished	Jul 06 05:52:10 PM PDT 24
Peak memory	275692 kb
Host	smart-fad231fb-9a4f-4e4c-ae34-b864892f2cba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114519176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_rw_evict.114519176
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.764793770
Short name	T157
Test name
Test status
Simulation time	1271031600 ps
CPU time	64.7 seconds
Started	Jul 06 05:51:41 PM PDT 24
Finished	Jul 06 05:52:46 PM PDT 24
Peak memory	263200 kb
Host	smart-50f295c4-e162-4660-8620-d8d022ee6204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764793770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.764793770
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.3782093636
Short name	T493
Test name
Test status
Simulation time	19575100 ps
CPU time	99.77 seconds
Started	Jul 06 05:51:30 PM PDT 24
Finished	Jul 06 05:53:10 PM PDT 24
Peak memory	276844 kb
Host	smart-489df792-b192-4935-af50-798b4d6bba51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782093636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3782093636
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.3585170976
Short name	T693
Test name
Test status
Simulation time	2658911500 ps
CPU time	207.84 seconds
Started	Jul 06 05:51:34 PM PDT 24
Finished	Jul 06 05:55:02 PM PDT 24
Peak memory	260060 kb
Host	smart-97254f18-467e-489e-adaa-e4c0d0dbe168
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585170976 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.flash_ctrl_wo.3585170976
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.3327956215
Short name	T451
Test name
Test status
Simulation time	60326400 ps
CPU time	14.2 seconds
Started	Jul 06 05:51:59 PM PDT 24
Finished	Jul 06 05:52:13 PM PDT 24
Peak memory	258368 kb
Host	smart-65940f81-3edb-43bf-85ac-2b3904dbb161
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327956215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 3327956215
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.3579085791
Short name	T717
Test name
Test status
Simulation time	64824000 ps
CPU time	15.97 seconds
Started	Jul 06 05:51:50 PM PDT 24
Finished	Jul 06 05:52:06 PM PDT 24
Peak memory	274868 kb
Host	smart-22985067-7344-4d36-803d-28e6d6405bca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579085791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3579085791
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.2630229196
Short name	T534
Test name
Test status
Simulation time	14886700 ps
CPU time	21.23 seconds
Started	Jul 06 05:51:53 PM PDT 24
Finished	Jul 06 05:52:15 PM PDT 24
Peak memory	273424 kb
Host	smart-5c91e618-f863-47fd-9876-4ba22d8f351f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630229196 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.2630229196
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3594016966
Short name	T89
Test name
Test status
Simulation time	10012019600 ps
CPU time	335.44 seconds
Started	Jul 06 05:51:58 PM PDT 24
Finished	Jul 06 05:57:34 PM PDT 24
Peak memory	326372 kb
Host	smart-36788eed-ac6a-4725-90d0-c11f3c401dff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594016966 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3594016966
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2795477427
Short name	T667
Test name
Test status
Simulation time	26935000 ps
CPU time	13.83 seconds
Started	Jul 06 05:51:51 PM PDT 24
Finished	Jul 06 05:52:05 PM PDT 24
Peak memory	260220 kb
Host	smart-1af0c4ee-43ad-4416-83eb-a8b349671618
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795477427 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2795477427
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.1635413359
Short name	T727
Test name
Test status
Simulation time	2160712900 ps
CPU time	175.13 seconds
Started	Jul 06 05:51:46 PM PDT 24
Finished	Jul 06 05:54:41 PM PDT 24
Peak memory	263108 kb
Host	smart-f9899654-97d8-47ab-9779-c9806e57c334
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635413359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ hw_sec_otp.1635413359
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.2065664783
Short name	T712
Test name
Test status
Simulation time	19581388200 ps
CPU time	246.54 seconds
Started	Jul 06 05:51:52 PM PDT 24
Finished	Jul 06 05:55:58 PM PDT 24
Peak memory	291360 kb
Host	smart-6697a919-0fd0-4747-b230-55f28a5b9021
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065664783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.2065664783
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2797023588
Short name	T928
Test name
Test status
Simulation time	11495058900 ps
CPU time	162.18 seconds
Started	Jul 06 05:51:51 PM PDT 24
Finished	Jul 06 05:54:33 PM PDT 24
Peak memory	294228 kb
Host	smart-ac144849-964a-49f8-8f9c-b540f8651d3e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797023588 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2797023588
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.1718424029
Short name	T48
Test name
Test status
Simulation time	7678938200 ps
CPU time	69.46 seconds
Started	Jul 06 05:51:45 PM PDT 24
Finished	Jul 06 05:52:55 PM PDT 24
Peak memory	262712 kb
Host	smart-3f9a6623-bd65-4859-81d9-dc8882a7cdd3
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718424029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1 718424029
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.129793103
Short name	T181
Test name
Test status
Simulation time	119406900 ps
CPU time	13.56 seconds
Started	Jul 06 05:51:51 PM PDT 24
Finished	Jul 06 05:52:05 PM PDT 24
Peak memory	259848 kb
Host	smart-755961ba-2161-4aac-a445-d5034d5be4c5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129793103 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.129793103
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.3033611814
Short name	T144
Test name
Test status
Simulation time	5291758800 ps
CPU time	169.9 seconds
Started	Jul 06 05:51:46 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	272924 kb
Host	smart-aa656b8b-fc35-458a-9713-1079ba38589c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033611814 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3033611814
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.2229676863
Short name	T1025
Test name
Test status
Simulation time	38394400 ps
CPU time	134.73 seconds
Started	Jul 06 05:51:47 PM PDT 24
Finished	Jul 06 05:54:02 PM PDT 24
Peak memory	260204 kb
Host	smart-86eadac3-a201-41a6-a4ce-00e63eef9b43
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229676863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.2229676863
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.1205887515
Short name	T248
Test name
Test status
Simulation time	104869200 ps
CPU time	69.17 seconds
Started	Jul 06 05:51:49 PM PDT 24
Finished	Jul 06 05:52:58 PM PDT 24
Peak memory	263128 kb
Host	smart-a2b4fabb-a51d-4316-98ff-81b589d0ad56
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1205887515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1205887515
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.4040842684
Short name	T171
Test name
Test status
Simulation time	41290700 ps
CPU time	14.03 seconds
Started	Jul 06 05:51:52 PM PDT 24
Finished	Jul 06 05:52:07 PM PDT 24
Peak memory	265280 kb
Host	smart-3375b0a5-cb68-4a43-bc77-3be4c3d4e1c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040842684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.4040842684
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.2532292597
Short name	T160
Test name
Test status
Simulation time	326856200 ps
CPU time	423.05 seconds
Started	Jul 06 05:51:46 PM PDT 24
Finished	Jul 06 05:58:50 PM PDT 24
Peak memory	281664 kb
Host	smart-34b85020-2395-4b54-9d87-cbe32b40f18f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532292597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2532292597
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.3928146797
Short name	T339
Test name
Test status
Simulation time	84921800 ps
CPU time	32.55 seconds
Started	Jul 06 05:51:51 PM PDT 24
Finished	Jul 06 05:52:24 PM PDT 24
Peak memory	268436 kb
Host	smart-8a54797a-7a5f-4743-9393-3a4554e6ddbd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928146797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.3928146797
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.3436731082
Short name	T496
Test name
Test status
Simulation time	1385325100 ps
CPU time	125.59 seconds
Started	Jul 06 05:51:48 PM PDT 24
Finished	Jul 06 05:53:54 PM PDT 24
Peak memory	281776 kb
Host	smart-b14da55c-d30b-4bee-a0ce-45163d648ef0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436731082 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.3436731082
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.732576381
Short name	T658
Test name
Test status
Simulation time	51998900 ps
CPU time	31.42 seconds
Started	Jul 06 05:51:53 PM PDT 24
Finished	Jul 06 05:52:25 PM PDT 24
Peak memory	268508 kb
Host	smart-e85941a4-bdee-4204-96f6-de8abbe90f64
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732576381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_rw_evict.732576381
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.470408958
Short name	T357
Test name
Test status
Simulation time	41880200 ps
CPU time	32.32 seconds
Started	Jul 06 05:51:52 PM PDT 24
Finished	Jul 06 05:52:24 PM PDT 24
Peak memory	268528 kb
Host	smart-793ff49c-3ace-4dde-a314-29d62f870024
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470408958 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.470408958
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.1315407664
Short name	T460
Test name
Test status
Simulation time	68384400 ps
CPU time	169.36 seconds
Started	Jul 06 05:51:46 PM PDT 24
Finished	Jul 06 05:54:35 PM PDT 24
Peak memory	277592 kb
Host	smart-e0d206a8-cbcc-4339-9c2f-e4ecac0b4430
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315407664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1315407664
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.1943453601
Short name	T619
Test name
Test status
Simulation time	11338598200 ps
CPU time	252.77 seconds
Started	Jul 06 05:51:48 PM PDT 24
Finished	Jul 06 05:56:01 PM PDT 24
Peak memory	265324 kb
Host	smart-7851c95c-0dd4-47b1-9319-25dd26df237a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943453601 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.flash_ctrl_wo.1943453601
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.2883509290
Short name	T115
Test name
Test status
Simulation time	47132700 ps
CPU time	14.01 seconds
Started	Jul 06 05:52:12 PM PDT 24
Finished	Jul 06 05:52:26 PM PDT 24
Peak memory	258312 kb
Host	smart-fa62127a-b65e-4988-9658-cf527a01bbc0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883509290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 2883509290
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.1174820019
Short name	T21
Test name
Test status
Simulation time	30358300 ps
CPU time	15.76 seconds
Started	Jul 06 05:52:04 PM PDT 24
Finished	Jul 06 05:52:20 PM PDT 24
Peak memory	274948 kb
Host	smart-1d6eaf92-34e4-4871-ad78-14d9e361d4cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174820019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1174820019
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.815116565
Short name	T778
Test name
Test status
Simulation time	10018044000 ps
CPU time	96.93 seconds
Started	Jul 06 05:52:12 PM PDT 24
Finished	Jul 06 05:53:50 PM PDT 24
Peak memory	332436 kb
Host	smart-772485ce-664c-4103-a905-a80358a3dce4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815116565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.815116565
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1669397551
Short name	T518
Test name
Test status
Simulation time	78192400 ps
CPU time	13.49 seconds
Started	Jul 06 05:52:13 PM PDT 24
Finished	Jul 06 05:52:27 PM PDT 24
Peak memory	264964 kb
Host	smart-3e8201cc-d915-41aa-a243-2cc14e8a80fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669397551 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1669397551
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2484917519
Short name	T989
Test name
Test status
Simulation time	270201863400 ps
CPU time	845.79 seconds
Started	Jul 06 05:51:57 PM PDT 24
Finished	Jul 06 06:06:04 PM PDT 24
Peak memory	264496 kb
Host	smart-250b4f4f-5dc9-4881-8414-2139e5bf8925
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484917519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.2484917519
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2865301727
Short name	T307
Test name
Test status
Simulation time	6689866900 ps
CPU time	40.28 seconds
Started	Jul 06 05:51:59 PM PDT 24
Finished	Jul 06 05:52:39 PM PDT 24
Peak memory	260620 kb
Host	smart-1b4f1bc8-a304-4e97-86b3-dc239b87be66
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865301727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.2865301727
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.1629757194
Short name	T358
Test name
Test status
Simulation time	7400415400 ps
CPU time	203.79 seconds
Started	Jul 06 05:52:05 PM PDT 24
Finished	Jul 06 05:55:29 PM PDT 24
Peak memory	291488 kb
Host	smart-f560ff8a-b037-4807-9e35-96a0b11d5531
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629757194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.1629757194
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2146048374
Short name	T612
Test name
Test status
Simulation time	11292255300 ps
CPU time	155.72 seconds
Started	Jul 06 05:52:06 PM PDT 24
Finished	Jul 06 05:54:43 PM PDT 24
Peak memory	293020 kb
Host	smart-56c1eeda-fb9d-49c0-ab0e-79d2da12150c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146048374 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2146048374
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.2511344841
Short name	T1075
Test name
Test status
Simulation time	7831621100 ps
CPU time	67.41 seconds
Started	Jul 06 05:51:58 PM PDT 24
Finished	Jul 06 05:53:05 PM PDT 24
Peak memory	263624 kb
Host	smart-9d2748da-6a87-4b3d-9b68-ae2ef4845d03
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511344841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.2 511344841
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.1333010293
Short name	T1033
Test name
Test status
Simulation time	96587700 ps
CPU time	14.06 seconds
Started	Jul 06 05:52:06 PM PDT 24
Finished	Jul 06 05:52:21 PM PDT 24
Peak memory	264980 kb
Host	smart-9769b5b9-1d0b-4dfb-8f05-0075629fb94e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333010293 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.1333010293
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.196840963
Short name	T70
Test name
Test status
Simulation time	88590065100 ps
CPU time	316.38 seconds
Started	Jul 06 05:51:59 PM PDT 24
Finished	Jul 06 05:57:15 PM PDT 24
Peak memory	274736 kb
Host	smart-35f4864e-c93a-4606-9db7-64ee14f31dee
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196840963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.196840963
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.1221136825
Short name	T731
Test name
Test status
Simulation time	86974400 ps
CPU time	131.88 seconds
Started	Jul 06 05:51:57 PM PDT 24
Finished	Jul 06 05:54:09 PM PDT 24
Peak memory	264832 kb
Host	smart-dd24a697-0683-4b52-8af4-299ea7d79e6a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221136825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.1221136825
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.2820270222
Short name	T697
Test name
Test status
Simulation time	831275500 ps
CPU time	204.47 seconds
Started	Jul 06 05:51:57 PM PDT 24
Finished	Jul 06 05:55:22 PM PDT 24
Peak memory	263224 kb
Host	smart-229994af-39e4-44f8-9a50-5f946dc423ad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2820270222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2820270222
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.570966681
Short name	T468
Test name
Test status
Simulation time	2708419800 ps
CPU time	197.62 seconds
Started	Jul 06 05:52:05 PM PDT 24
Finished	Jul 06 05:55:23 PM PDT 24
Peak memory	265328 kb
Host	smart-440be1f5-c708-4e08-98ef-f4369c311b3f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570966681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.flash_ctrl_prog_reset.570966681
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.3062009358
Short name	T141
Test name
Test status
Simulation time	5537468900 ps
CPU time	767.89 seconds
Started	Jul 06 05:51:59 PM PDT 24
Finished	Jul 06 06:04:48 PM PDT 24
Peak memory	285952 kb
Host	smart-5cd6af5d-21d8-49d8-9346-44818edb0746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062009358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3062009358
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.3516299350
Short name	T593
Test name
Test status
Simulation time	645748900 ps
CPU time	33.51 seconds
Started	Jul 06 05:52:06 PM PDT 24
Finished	Jul 06 05:52:40 PM PDT 24
Peak memory	275668 kb
Host	smart-cdb63b3a-7dad-4605-a85e-210e3f09e958
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516299350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.3516299350
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.2152760820
Short name	T901
Test name
Test status
Simulation time	2319486200 ps
CPU time	127.22 seconds
Started	Jul 06 05:51:58 PM PDT 24
Finished	Jul 06 05:54:05 PM PDT 24
Peak memory	291252 kb
Host	smart-0f185f25-ee53-48c9-9eed-1533c1e0071d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152760820 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.2152760820
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.204557085
Short name	T673
Test name
Test status
Simulation time	48027590100 ps
CPU time	615.7 seconds
Started	Jul 06 05:52:04 PM PDT 24
Finished	Jul 06 06:02:20 PM PDT 24
Peak memory	314184 kb
Host	smart-604b3017-4788-47fe-bb40-11e5725d85ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204557085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.204557085
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict.2028670769
Short name	T934
Test name
Test status
Simulation time	27762700 ps
CPU time	30.82 seconds
Started	Jul 06 05:52:05 PM PDT 24
Finished	Jul 06 05:52:36 PM PDT 24
Peak memory	275640 kb
Host	smart-6d0126d2-304f-4940-bbc0-e1f3731b1de1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028670769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_rw_evict.2028670769
Directory	/workspace/13.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1302156586
Short name	T861
Test name
Test status
Simulation time	92576300 ps
CPU time	30.92 seconds
Started	Jul 06 05:52:06 PM PDT 24
Finished	Jul 06 05:52:38 PM PDT 24
Peak memory	267512 kb
Host	smart-fdfde76e-fcab-4fad-9c94-070a4c96b376
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302156586 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1302156586
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.2902067491
Short name	T835
Test name
Test status
Simulation time	1111333600 ps
CPU time	65.02 seconds
Started	Jul 06 05:52:09 PM PDT 24
Finished	Jul 06 05:53:15 PM PDT 24
Peak memory	263748 kb
Host	smart-e1ae20ae-8c6d-4178-a18d-b7320609221e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902067491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2902067491
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.1057845524
Short name	T571
Test name
Test status
Simulation time	47040600 ps
CPU time	216.09 seconds
Started	Jul 06 05:51:59 PM PDT 24
Finished	Jul 06 05:55:35 PM PDT 24
Peak memory	279632 kb
Host	smart-e28d312c-0a8a-4898-bf3c-e2d81477cc3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057845524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1057845524
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.365257454
Short name	T836
Test name
Test status
Simulation time	4081119600 ps
CPU time	182.34 seconds
Started	Jul 06 05:51:58 PM PDT 24
Finished	Jul 06 05:55:00 PM PDT 24
Peak memory	261092 kb
Host	smart-a1ae6aa4-2c98-4d5a-b270-d61962deb405
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365257454 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.flash_ctrl_wo.365257454
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.3084373135
Short name	T19
Test name
Test status
Simulation time	147065100 ps
CPU time	13.87 seconds
Started	Jul 06 05:52:20 PM PDT 24
Finished	Jul 06 05:52:34 PM PDT 24
Peak memory	258256 kb
Host	smart-db8c8794-8629-498e-893a-2d6031f968d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084373135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 3084373135
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.2532830512
Short name	T1008
Test name
Test status
Simulation time	50058500 ps
CPU time	16.63 seconds
Started	Jul 06 05:52:17 PM PDT 24
Finished	Jul 06 05:52:33 PM PDT 24
Peak memory	284360 kb
Host	smart-56c2b73c-8dbd-4fc1-b268-f86670cc7586
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2532830512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2532830512
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.969528511
Short name	T194
Test name
Test status
Simulation time	10032521900 ps
CPU time	60.91 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:53:16 PM PDT 24
Peak memory	287004 kb
Host	smart-52d02681-1605-494e-b858-18ab3caa3d8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969528511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.969528511
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.564912086
Short name	T170
Test name
Test status
Simulation time	27062800 ps
CPU time	13.45 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:52:29 PM PDT 24
Peak memory	264924 kb
Host	smart-c2d1a52f-ce5f-4ec9-a710-d902c49701bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564912086 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.564912086
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.4194909219
Short name	T120
Test name
Test status
Simulation time	60132875500 ps
CPU time	864.73 seconds
Started	Jul 06 05:52:11 PM PDT 24
Finished	Jul 06 06:06:36 PM PDT 24
Peak memory	264972 kb
Host	smart-0b11bdc4-52a7-4cec-b95f-644d9221d9a7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194909219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.4194909219
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.159993685
Short name	T832
Test name
Test status
Simulation time	16926146700 ps
CPU time	136 seconds
Started	Jul 06 05:52:10 PM PDT 24
Finished	Jul 06 05:54:27 PM PDT 24
Peak memory	263260 kb
Host	smart-2ed01226-6a82-49b4-b643-a8050c95ce48
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159993685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h w_sec_otp.159993685
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.887364953
Short name	T38
Test name
Test status
Simulation time	4567347100 ps
CPU time	165.56 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:55:01 PM PDT 24
Peak memory	291476 kb
Host	smart-7d5e0b30-fb79-45b1-9b08-db15d5312fb1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887364953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas h_ctrl_intr_rd.887364953
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2123978012
Short name	T812
Test name
Test status
Simulation time	48715395500 ps
CPU time	355.34 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 05:58:10 PM PDT 24
Peak memory	291032 kb
Host	smart-67d41e2b-15e9-4c8e-a632-10cf555fb836
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123978012 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.2123978012
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.918580517
Short name	T985
Test name
Test status
Simulation time	63089579800 ps
CPU time	392.27 seconds
Started	Jul 06 05:52:10 PM PDT 24
Finished	Jul 06 05:58:43 PM PDT 24
Peak memory	274456 kb
Host	smart-21e8a04a-80fd-4a64-bea6-4929d70aea9a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918580517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.918580517
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.823655076
Short name	T382
Test name
Test status
Simulation time	67994600 ps
CPU time	109.52 seconds
Started	Jul 06 05:52:11 PM PDT 24
Finished	Jul 06 05:54:01 PM PDT 24
Peak memory	264920 kb
Host	smart-462e55e7-ac37-446d-977d-d2d9a76de33f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823655076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ot p_reset.823655076
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.1300709796
Short name	T232
Test name
Test status
Simulation time	721270200 ps
CPU time	429.84 seconds
Started	Jul 06 05:52:13 PM PDT 24
Finished	Jul 06 05:59:23 PM PDT 24
Peak memory	263152 kb
Host	smart-b9b0dcfe-480f-4713-af51-b4425564b21e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1300709796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1300709796
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.4143119295
Short name	T726
Test name
Test status
Simulation time	38769600 ps
CPU time	13.43 seconds
Started	Jul 06 05:52:16 PM PDT 24
Finished	Jul 06 05:52:29 PM PDT 24
Peak memory	259168 kb
Host	smart-61c3a0f6-9faf-463b-b8dd-7c962d7e6cdd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143119295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.4143119295
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.1778397995
Short name	T581
Test name
Test status
Simulation time	59097200 ps
CPU time	182.65 seconds
Started	Jul 06 05:52:12 PM PDT 24
Finished	Jul 06 05:55:15 PM PDT 24
Peak memory	275028 kb
Host	smart-b613ea06-95f1-4ead-89fb-053f8300e91d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778397995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1778397995
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.1823841303
Short name	T336
Test name
Test status
Simulation time	181719800 ps
CPU time	31.39 seconds
Started	Jul 06 05:52:14 PM PDT 24
Finished	Jul 06 05:52:46 PM PDT 24
Peak memory	268516 kb
Host	smart-68740411-731a-44e7-810a-af6de159438e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823841303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.1823841303
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.2480397526
Short name	T993
Test name
Test status
Simulation time	1975515500 ps
CPU time	136.41 seconds
Started	Jul 06 05:52:16 PM PDT 24
Finished	Jul 06 05:54:32 PM PDT 24
Peak memory	291392 kb
Host	smart-043e3489-8d86-45ef-b134-82b1e213ad0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480397526 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 14.flash_ctrl_ro.2480397526
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.705325992
Short name	T146
Test name
Test status
Simulation time	16129939700 ps
CPU time	682.89 seconds
Started	Jul 06 05:52:15 PM PDT 24
Finished	Jul 06 06:03:39 PM PDT 24
Peak memory	309780 kb
Host	smart-b0fd31e1-2e45-4148-a180-a0bf5f438d99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705325992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.705325992
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.2853960177
Short name	T614
Test name
Test status
Simulation time	82698400 ps
CPU time	28.79 seconds
Started	Jul 06 05:52:17 PM PDT 24
Finished	Jul 06 05:52:46 PM PDT 24
Peak memory	275628 kb
Host	smart-dacedc45-ecc3-479b-9a24-94dda85a648a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853960177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.2853960177
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.3711783019
Short name	T441
Test name
Test status
Simulation time	1479109200 ps
CPU time	56.63 seconds
Started	Jul 06 05:52:18 PM PDT 24
Finished	Jul 06 05:53:15 PM PDT 24
Peak memory	263820 kb
Host	smart-0e636b19-8e99-426d-9b82-b01298d55aca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711783019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3711783019
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.1791930910
Short name	T542
Test name
Test status
Simulation time	37529900 ps
CPU time	49.51 seconds
Started	Jul 06 05:52:10 PM PDT 24
Finished	Jul 06 05:53:00 PM PDT 24
Peak memory	271344 kb
Host	smart-c7777728-7d5d-4b1d-a48c-673cd201b23f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1791930910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1791930910
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.3236195219
Short name	T776
Test name
Test status
Simulation time	2271242800 ps
CPU time	172.75 seconds
Started	Jul 06 05:52:12 PM PDT 24
Finished	Jul 06 05:55:05 PM PDT 24
Peak memory	260060 kb
Host	smart-e4f4b007-869d-403c-9f37-39c332d238d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236195219 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.3236195219
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.3135288677
Short name	T912
Test name
Test status
Simulation time	21900700 ps
CPU time	15.85 seconds
Started	Jul 06 05:52:31 PM PDT 24
Finished	Jul 06 05:52:47 PM PDT 24
Peak memory	284244 kb
Host	smart-30996d68-24ee-41ce-aa98-696d4c392696
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135288677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3135288677
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.2470774691
Short name	T689
Test name
Test status
Simulation time	13173800 ps
CPU time	20.74 seconds
Started	Jul 06 05:52:28 PM PDT 24
Finished	Jul 06 05:52:49 PM PDT 24
Peak memory	273644 kb
Host	smart-5a88ca90-6701-4e9f-9524-5214266f66d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470774691 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.2470774691
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.660146553
Short name	T980
Test name
Test status
Simulation time	10012658400 ps
CPU time	129.96 seconds
Started	Jul 06 05:52:35 PM PDT 24
Finished	Jul 06 05:54:45 PM PDT 24
Peak memory	362376 kb
Host	smart-ff416b72-c8f0-400c-b3ec-8782003745eb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660146553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.660146553
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3612705212
Short name	T649
Test name
Test status
Simulation time	47225100 ps
CPU time	13.41 seconds
Started	Jul 06 05:52:35 PM PDT 24
Finished	Jul 06 05:52:49 PM PDT 24
Peak memory	264984 kb
Host	smart-3f5ddd57-6577-4abc-9613-658a7b5de1f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612705212 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3612705212
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.109714354
Short name	T1017
Test name
Test status
Simulation time	160190800300 ps
CPU time	872.69 seconds
Started	Jul 06 05:52:21 PM PDT 24
Finished	Jul 06 06:06:54 PM PDT 24
Peak memory	260904 kb
Host	smart-d071395f-30e3-4652-b940-9c250009f206
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109714354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.flash_ctrl_hw_rma_reset.109714354
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3145281802
Short name	T419
Test name
Test status
Simulation time	4733219500 ps
CPU time	130.9 seconds
Started	Jul 06 05:52:19 PM PDT 24
Finished	Jul 06 05:54:30 PM PDT 24
Peak memory	262856 kb
Host	smart-f5564eac-be1f-4235-99b2-5952ba9e8d6c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145281802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ hw_sec_otp.3145281802
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.2694084581
Short name	T725
Test name
Test status
Simulation time	2989287800 ps
CPU time	135.66 seconds
Started	Jul 06 05:52:25 PM PDT 24
Finished	Jul 06 05:54:41 PM PDT 24
Peak memory	291468 kb
Host	smart-2af3da85-d2e0-4895-b283-4ac144f1e3a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694084581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.2694084581
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.4005109716
Short name	T455
Test name
Test status
Simulation time	5754325600 ps
CPU time	141.06 seconds
Started	Jul 06 05:52:26 PM PDT 24
Finished	Jul 06 05:54:47 PM PDT 24
Peak memory	293008 kb
Host	smart-72cb8490-b17c-40b2-9c7a-d7669e0ccf42
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005109716 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.4005109716
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.2376905660
Short name	T972
Test name
Test status
Simulation time	8076507200 ps
CPU time	96.93 seconds
Started	Jul 06 05:52:20 PM PDT 24
Finished	Jul 06 05:53:57 PM PDT 24
Peak memory	263476 kb
Host	smart-9eb2893e-d17d-4df0-ad39-2e6fdc4f8800
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376905660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2 376905660
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.394143107
Short name	T290
Test name
Test status
Simulation time	15207800 ps
CPU time	13.34 seconds
Started	Jul 06 05:52:32 PM PDT 24
Finished	Jul 06 05:52:46 PM PDT 24
Peak memory	265024 kb
Host	smart-50f532e9-6607-4a29-8ff3-b1d957a1ce6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394143107 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.394143107
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.4175947764
Short name	T587
Test name
Test status
Simulation time	8352759200 ps
CPU time	198.89 seconds
Started	Jul 06 05:52:22 PM PDT 24
Finished	Jul 06 05:55:42 PM PDT 24
Peak memory	265096 kb
Host	smart-0fe6f72b-79d6-4a4d-b88c-cc0299789ff3
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175947764 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.4175947764
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.2484960337
Short name	T885
Test name
Test status
Simulation time	41621400 ps
CPU time	133.15 seconds
Started	Jul 06 05:52:22 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	260980 kb
Host	smart-d9ac6b2c-d43a-40ed-b2fd-4a3d3ce148a5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484960337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o tp_reset.2484960337
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.1567358352
Short name	T481
Test name
Test status
Simulation time	119141900 ps
CPU time	110.39 seconds
Started	Jul 06 05:52:22 PM PDT 24
Finished	Jul 06 05:54:13 PM PDT 24
Peak memory	263112 kb
Host	smart-825307fb-9ae7-45b3-91f6-a3bb83dd7b42
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1567358352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1567358352
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.2422559003
Short name	T485
Test name
Test status
Simulation time	62480000 ps
CPU time	13.37 seconds
Started	Jul 06 05:52:25 PM PDT 24
Finished	Jul 06 05:52:39 PM PDT 24
Peak memory	259204 kb
Host	smart-f1695d8f-138d-4494-8f05-7fa8c35a3667
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422559003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.flash_ctrl_prog_reset.2422559003
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.649849675
Short name	T919
Test name
Test status
Simulation time	68285900 ps
CPU time	293.24 seconds
Started	Jul 06 05:52:19 PM PDT 24
Finished	Jul 06 05:57:12 PM PDT 24
Peak memory	274316 kb
Host	smart-014339d5-16e2-452b-859f-17b3e39a7bf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649849675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.649849675
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.3437481749
Short name	T1117
Test name
Test status
Simulation time	745171500 ps
CPU time	34.48 seconds
Started	Jul 06 05:52:26 PM PDT 24
Finished	Jul 06 05:53:01 PM PDT 24
Peak memory	275724 kb
Host	smart-e97cbfd1-97dc-41dd-aa6a-29c65c0148e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437481749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.3437481749
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.1408739552
Short name	T826
Test name
Test status
Simulation time	1801995300 ps
CPU time	116.31 seconds
Started	Jul 06 05:52:25 PM PDT 24
Finished	Jul 06 05:54:22 PM PDT 24
Peak memory	291364 kb
Host	smart-8802e3a1-45c7-4800-ae4b-875319542653
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408739552 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_ro.1408739552
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.1152698051
Short name	T867
Test name
Test status
Simulation time	9631180900 ps
CPU time	592.74 seconds
Started	Jul 06 05:52:26 PM PDT 24
Finished	Jul 06 06:02:19 PM PDT 24
Peak memory	318964 kb
Host	smart-181ad623-5874-4e6d-b9f3-9e76f5b9e190
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152698051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.1152698051
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.4275543278
Short name	T642
Test name
Test status
Simulation time	37397900 ps
CPU time	30.06 seconds
Started	Jul 06 05:52:26 PM PDT 24
Finished	Jul 06 05:52:56 PM PDT 24
Peak memory	275660 kb
Host	smart-b5fba5bc-3edd-4b37-a5c8-dfd94fe507a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275543278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_rw_evict.4275543278
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2103756963
Short name	T1058
Test name
Test status
Simulation time	82419300 ps
CPU time	32.39 seconds
Started	Jul 06 05:52:25 PM PDT 24
Finished	Jul 06 05:52:57 PM PDT 24
Peak memory	275688 kb
Host	smart-295fe2b7-7111-4395-8212-06bbb19431c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103756963 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.2103756963
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.3116919221
Short name	T870
Test name
Test status
Simulation time	1969678200 ps
CPU time	70.92 seconds
Started	Jul 06 05:52:27 PM PDT 24
Finished	Jul 06 05:53:38 PM PDT 24
Peak memory	264680 kb
Host	smart-a7a80eaa-66a7-412a-a793-37e375ed4c0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116919221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3116919221
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.3840788264
Short name	T45
Test name
Test status
Simulation time	38345900 ps
CPU time	174.93 seconds
Started	Jul 06 05:52:21 PM PDT 24
Finished	Jul 06 05:55:17 PM PDT 24
Peak memory	278280 kb
Host	smart-98c50388-193a-45a8-88b1-13405bad4bca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840788264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3840788264
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.3923976175
Short name	T560
Test name
Test status
Simulation time	9576961800 ps
CPU time	170.8 seconds
Started	Jul 06 05:52:26 PM PDT 24
Finished	Jul 06 05:55:18 PM PDT 24
Peak memory	260016 kb
Host	smart-730f4aae-e98c-416a-a83c-5fd345d3628e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923976175 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.3923976175
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.1466473992
Short name	T639
Test name
Test status
Simulation time	69073300 ps
CPU time	13.58 seconds
Started	Jul 06 05:52:42 PM PDT 24
Finished	Jul 06 05:52:56 PM PDT 24
Peak memory	258248 kb
Host	smart-5ee80353-4b65-4623-816c-c63eae37ffbb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466473992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test. 1466473992
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.1932372422
Short name	T735
Test name
Test status
Simulation time	133383200 ps
CPU time	16.01 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:52:55 PM PDT 24
Peak memory	274924 kb
Host	smart-744e58e2-65e2-4d91-bc4f-245a7e94e69a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932372422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.1932372422
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3828427594
Short name	T90
Test name
Test status
Simulation time	10011637700 ps
CPU time	347.98 seconds
Started	Jul 06 05:52:42 PM PDT 24
Finished	Jul 06 05:58:30 PM PDT 24
Peak memory	336248 kb
Host	smart-94779bf9-7685-4154-8907-f42537461259
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828427594 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3828427594
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2224229483
Short name	T177
Test name
Test status
Simulation time	25600700 ps
CPU time	13.59 seconds
Started	Jul 06 05:52:41 PM PDT 24
Finished	Jul 06 05:52:55 PM PDT 24
Peak memory	265332 kb
Host	smart-16497a68-8ba5-4a1d-b254-a9c21a51fdf2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224229483 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2224229483
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.2969198725
Short name	T203
Test name
Test status
Simulation time	80140690300 ps
CPU time	922.85 seconds
Started	Jul 06 05:52:32 PM PDT 24
Finished	Jul 06 06:07:56 PM PDT 24
Peak memory	264436 kb
Host	smart-88b1416a-058f-482c-b364-107ad2cf3717
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969198725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.2969198725
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1525904405
Short name	T830
Test name
Test status
Simulation time	10492609200 ps
CPU time	100.89 seconds
Started	Jul 06 05:52:32 PM PDT 24
Finished	Jul 06 05:54:14 PM PDT 24
Peak memory	263164 kb
Host	smart-f90cc10b-de85-4ba5-b992-d64c368793e4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525904405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.1525904405
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.2325897352
Short name	T325
Test name
Test status
Simulation time	593171900 ps
CPU time	154.89 seconds
Started	Jul 06 05:52:40 PM PDT 24
Finished	Jul 06 05:55:15 PM PDT 24
Peak memory	291552 kb
Host	smart-84105944-c495-4e3e-b31f-502fa33c4e74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325897352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.2325897352
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2313668238
Short name	T923
Test name
Test status
Simulation time	51541774200 ps
CPU time	330.04 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 05:58:08 PM PDT 24
Peak memory	284980 kb
Host	smart-7d3934cc-3ad8-4068-80f0-1284b3487a04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313668238 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2313668238
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.4199172629
Short name	T151
Test name
Test status
Simulation time	1940691200 ps
CPU time	89.99 seconds
Started	Jul 06 05:52:40 PM PDT 24
Finished	Jul 06 05:54:10 PM PDT 24
Peak memory	260600 kb
Host	smart-93e3696b-43a5-4f0b-934d-0d8b6f9c675a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199172629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.4 199172629
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.3456115737
Short name	T291
Test name
Test status
Simulation time	14888100 ps
CPU time	13.42 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:52:53 PM PDT 24
Peak memory	259944 kb
Host	smart-e4079fbe-70b4-436f-b5b5-d57d154971ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456115737 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.3456115737
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.3887609065
Short name	T1119
Test name
Test status
Simulation time	8345035100 ps
CPU time	241.05 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:56:40 PM PDT 24
Peak memory	274844 kb
Host	smart-e1cd7da2-d691-4001-bc8c-55d7c3827680
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887609065 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.3887609065
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.4000866098
Short name	T183
Test name
Test status
Simulation time	120089900 ps
CPU time	131.2 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 05:54:50 PM PDT 24
Peak memory	260164 kb
Host	smart-948d320d-f10f-4514-877b-979ae8a8450b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000866098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.4000866098
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.344429940
Short name	T947
Test name
Test status
Simulation time	1422264400 ps
CPU time	398.56 seconds
Started	Jul 06 05:52:33 PM PDT 24
Finished	Jul 06 05:59:11 PM PDT 24
Peak memory	263436 kb
Host	smart-f8376f4e-e105-4d70-b79e-87bb1dad34c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=344429940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.344429940
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.4089916325
Short name	T950
Test name
Test status
Simulation time	32876600 ps
CPU time	13.82 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:52:53 PM PDT 24
Peak memory	259164 kb
Host	smart-05c092db-a893-48d1-81cc-e3664481db4a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089916325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.4089916325
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.2052068143
Short name	T653
Test name
Test status
Simulation time	213744000 ps
CPU time	1405.79 seconds
Started	Jul 06 05:52:33 PM PDT 24
Finished	Jul 06 06:15:59 PM PDT 24
Peak memory	289860 kb
Host	smart-88cb5b5e-e240-4ad8-a9e0-39bf25782fc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052068143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2052068143
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.153711064
Short name	T349
Test name
Test status
Simulation time	109997500 ps
CPU time	34.73 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:53:14 PM PDT 24
Peak memory	270580 kb
Host	smart-e88ed36c-763e-4e48-ba64-88dd2a8d3ccd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153711064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_re_evict.153711064
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.3097373671
Short name	T970
Test name
Test status
Simulation time	2040252500 ps
CPU time	126.45 seconds
Started	Jul 06 05:52:41 PM PDT 24
Finished	Jul 06 05:54:47 PM PDT 24
Peak memory	289260 kb
Host	smart-10613510-23be-4b5c-b3b3-65a677f01e34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097373671 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.3097373671
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.708650719
Short name	T1029
Test name
Test status
Simulation time	23994768500 ps
CPU time	513.23 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 06:01:11 PM PDT 24
Peak memory	314512 kb
Host	smart-779f7e2d-a37c-4bdb-90d4-adf4e908e84a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708650719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.708650719
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.2742110668
Short name	T656
Test name
Test status
Simulation time	44789900 ps
CPU time	30.39 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 05:53:08 PM PDT 24
Peak memory	267724 kb
Host	smart-7a58e913-0889-4cc8-90d6-5d806fcddacc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742110668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_rw_evict.2742110668
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.328204019
Short name	T825
Test name
Test status
Simulation time	31546500 ps
CPU time	32.27 seconds
Started	Jul 06 05:52:38 PM PDT 24
Finished	Jul 06 05:53:11 PM PDT 24
Peak memory	267508 kb
Host	smart-da4da394-0a6f-4252-93f1-44c4aeec50c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328204019 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.328204019
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.1758036153
Short name	T389
Test name
Test status
Simulation time	1564522800 ps
CPU time	62.61 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:53:42 PM PDT 24
Peak memory	263120 kb
Host	smart-e898f727-482d-45ee-80c7-201e51ed0e6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758036153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1758036153
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.4249161039
Short name	T506
Test name
Test status
Simulation time	43864600 ps
CPU time	121.65 seconds
Started	Jul 06 05:52:31 PM PDT 24
Finished	Jul 06 05:54:33 PM PDT 24
Peak memory	277668 kb
Host	smart-652b6acf-1cba-4c25-83c4-80c9a0181d18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249161039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.4249161039
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.2536706033
Short name	T958
Test name
Test status
Simulation time	8565423600 ps
CPU time	168.61 seconds
Started	Jul 06 05:52:39 PM PDT 24
Finished	Jul 06 05:55:28 PM PDT 24
Peak memory	260036 kb
Host	smart-49851ca2-1d03-4124-a7eb-91cbab7e8d5e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536706033 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.2536706033
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.1552569374
Short name	T490
Test name
Test status
Simulation time	329652100 ps
CPU time	13.96 seconds
Started	Jul 06 05:52:54 PM PDT 24
Finished	Jul 06 05:53:08 PM PDT 24
Peak memory	265164 kb
Host	smart-043f28b1-a0bc-4fd6-aa7f-891af55eaffd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552569374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 1552569374
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.4137483537
Short name	T539
Test name
Test status
Simulation time	50615100 ps
CPU time	16 seconds
Started	Jul 06 05:52:52 PM PDT 24
Finished	Jul 06 05:53:08 PM PDT 24
Peak memory	284228 kb
Host	smart-b88fcc7a-f1f8-48d9-b37e-fec9317308b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137483537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4137483537
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.2851336770
Short name	T523
Test name
Test status
Simulation time	20640700 ps
CPU time	21.94 seconds
Started	Jul 06 05:52:49 PM PDT 24
Finished	Jul 06 05:53:11 PM PDT 24
Peak memory	265548 kb
Host	smart-ee28210c-6d42-44ff-ab00-56b9ba83bd20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851336770 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.2851336770
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.205479887
Short name	T1106
Test name
Test status
Simulation time	10032116900 ps
CPU time	107.35 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 05:54:41 PM PDT 24
Peak memory	271428 kb
Host	smart-26bb29a1-21fd-48d3-ac92-7d5625cb562f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205479887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.205479887
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.1913292649
Short name	T124
Test name
Test status
Simulation time	18102100 ps
CPU time	13.69 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 05:53:07 PM PDT 24
Peak memory	260260 kb
Host	smart-98972ce9-79f7-442b-948e-5c999277cfa2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913292649 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.1913292649
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.193836464
Short name	T524
Test name
Test status
Simulation time	18848186900 ps
CPU time	148.77 seconds
Started	Jul 06 05:52:44 PM PDT 24
Finished	Jul 06 05:55:13 PM PDT 24
Peak memory	262724 kb
Host	smart-0b0e46af-fd5c-4044-9aa3-226bc53af535
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193836464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h w_sec_otp.193836464
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.440821785
Short name	T752
Test name
Test status
Simulation time	1470262200 ps
CPU time	166.87 seconds
Started	Jul 06 05:52:50 PM PDT 24
Finished	Jul 06 05:55:37 PM PDT 24
Peak memory	294136 kb
Host	smart-129fdcc5-b6ff-417c-9acf-8b352a8c81e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440821785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_intr_rd.440821785
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.2327685570
Short name	T516
Test name
Test status
Simulation time	3918349400 ps
CPU time	90.3 seconds
Started	Jul 06 05:52:51 PM PDT 24
Finished	Jul 06 05:54:22 PM PDT 24
Peak memory	260604 kb
Host	smart-d420a7f0-81b5-4c58-8720-9f57ded24ffe
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327685570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2 327685570
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.4139979997
Short name	T588
Test name
Test status
Simulation time	36107200 ps
CPU time	13.47 seconds
Started	Jul 06 05:52:54 PM PDT 24
Finished	Jul 06 05:53:07 PM PDT 24
Peak memory	260936 kb
Host	smart-f4855dd8-c7dd-489d-a88c-40fbf75c9bbf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139979997 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.4139979997
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.4009452752
Short name	T68
Test name
Test status
Simulation time	22702368900 ps
CPU time	386.14 seconds
Started	Jul 06 05:52:50 PM PDT 24
Finished	Jul 06 05:59:16 PM PDT 24
Peak memory	273808 kb
Host	smart-131676e9-e175-4924-b074-0b90d78b842e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009452752 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.4009452752
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.1559895593
Short name	T739
Test name
Test status
Simulation time	136402500 ps
CPU time	112.42 seconds
Started	Jul 06 05:52:42 PM PDT 24
Finished	Jul 06 05:54:35 PM PDT 24
Peak memory	261024 kb
Host	smart-48d01a63-ed91-441e-a511-35a891fe6743
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559895593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.1559895593
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.3070188323
Short name	T1087
Test name
Test status
Simulation time	720241500 ps
CPU time	301.37 seconds
Started	Jul 06 05:52:44 PM PDT 24
Finished	Jul 06 05:57:46 PM PDT 24
Peak memory	263156 kb
Host	smart-22107634-685d-46c1-a625-1438c608cabc
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3070188323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3070188323
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.3213667964
Short name	T943
Test name
Test status
Simulation time	107762600 ps
CPU time	13.95 seconds
Started	Jul 06 05:52:49 PM PDT 24
Finished	Jul 06 05:53:03 PM PDT 24
Peak memory	265268 kb
Host	smart-b5599170-59bd-4be2-8c52-0caa97e7dbf9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213667964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.3213667964
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.812619118
Short name	T891
Test name
Test status
Simulation time	505239000 ps
CPU time	450.92 seconds
Started	Jul 06 05:52:41 PM PDT 24
Finished	Jul 06 06:00:12 PM PDT 24
Peak memory	279764 kb
Host	smart-2642de6a-c1e2-44d5-84c1-f2d759b79648
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812619118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.812619118
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.3741417837
Short name	T223
Test name
Test status
Simulation time	76029000 ps
CPU time	34.48 seconds
Started	Jul 06 05:52:49 PM PDT 24
Finished	Jul 06 05:53:24 PM PDT 24
Peak memory	275680 kb
Host	smart-4133f139-6688-49c9-b47a-e634d69187f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741417837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_re_evict.3741417837
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.411972958
Short name	T529
Test name
Test status
Simulation time	1095755900 ps
CPU time	136.81 seconds
Started	Jul 06 05:52:50 PM PDT 24
Finished	Jul 06 05:55:08 PM PDT 24
Peak memory	281000 kb
Host	smart-580c25cf-2425-478f-b054-892d5eb574b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411972958 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.flash_ctrl_ro.411972958
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.1028005408
Short name	T895
Test name
Test status
Simulation time	11530585500 ps
CPU time	705.05 seconds
Started	Jul 06 05:52:47 PM PDT 24
Finished	Jul 06 06:04:33 PM PDT 24
Peak memory	314664 kb
Host	smart-34e27edf-df80-474e-92ac-b6fa3b80ebb5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028005408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.1028005408
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.3823126649
Short name	T352
Test name
Test status
Simulation time	27429400 ps
CPU time	28.11 seconds
Started	Jul 06 05:52:49 PM PDT 24
Finished	Jul 06 05:53:18 PM PDT 24
Peak memory	275684 kb
Host	smart-93aae11e-6c36-41ff-ad62-881446c56695
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823126649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_rw_evict.3823126649
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2037519279
Short name	T148
Test name
Test status
Simulation time	29671100 ps
CPU time	28.73 seconds
Started	Jul 06 05:52:49 PM PDT 24
Finished	Jul 06 05:53:18 PM PDT 24
Peak memory	275712 kb
Host	smart-7f1420b8-39a0-4828-a0cc-96c4e8a01f45
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037519279 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2037519279
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.2901575777
Short name	T1089
Test name
Test status
Simulation time	4102733600 ps
CPU time	77.06 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 05:54:10 PM PDT 24
Peak memory	263716 kb
Host	smart-408efa93-be55-4a08-8458-bb7fbba51c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901575777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2901575777
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.1365255479
Short name	T437
Test name
Test status
Simulation time	579671800 ps
CPU time	146.59 seconds
Started	Jul 06 05:52:46 PM PDT 24
Finished	Jul 06 05:55:13 PM PDT 24
Peak memory	276988 kb
Host	smart-be4737ba-d8cd-49b7-9b4d-ca7d6cc1d02e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365255479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1365255479
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.3685568743
Short name	T822
Test name
Test status
Simulation time	2073914600 ps
CPU time	179.99 seconds
Started	Jul 06 05:52:50 PM PDT 24
Finished	Jul 06 05:55:50 PM PDT 24
Peak memory	260012 kb
Host	smart-60503d71-cc1e-46ac-a688-40c66558d68e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685568743 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.3685568743
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.286169705
Short name	T504
Test name
Test status
Simulation time	33201300 ps
CPU time	13.9 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 05:53:19 PM PDT 24
Peak memory	258320 kb
Host	smart-51431c1f-fa4b-4126-84c4-2047f1408d78
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286169705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.286169705
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.1162323191
Short name	T158
Test name
Test status
Simulation time	15299100 ps
CPU time	14.4 seconds
Started	Jul 06 05:53:05 PM PDT 24
Finished	Jul 06 05:53:19 PM PDT 24
Peak memory	274812 kb
Host	smart-a6e63007-4945-4521-8da1-ac923c48253c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162323191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1162323191
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.241995317
Short name	T570
Test name
Test status
Simulation time	36874200 ps
CPU time	22.17 seconds
Started	Jul 06 05:52:59 PM PDT 24
Finished	Jul 06 05:53:21 PM PDT 24
Peak memory	273644 kb
Host	smart-f07660e7-ad66-4592-a29f-0b8d70b15016
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241995317 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.241995317
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.71560449
Short name	T1066
Test name
Test status
Simulation time	10029108000 ps
CPU time	61.99 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 05:54:06 PM PDT 24
Peak memory	301412 kb
Host	smart-192d8a53-e327-45ef-a0ae-51d2c1ccb6bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71560449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.71560449
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1823881960
Short name	T286
Test name
Test status
Simulation time	18788600 ps
CPU time	13.65 seconds
Started	Jul 06 05:53:06 PM PDT 24
Finished	Jul 06 05:53:20 PM PDT 24
Peak memory	265060 kb
Host	smart-57af608e-8bb5-4ffd-a313-e541b62a6a7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823881960 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1823881960
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1080720116
Short name	T185
Test name
Test status
Simulation time	80136434400 ps
CPU time	783.32 seconds
Started	Jul 06 05:52:55 PM PDT 24
Finished	Jul 06 06:05:58 PM PDT 24
Peak memory	264560 kb
Host	smart-a6cf2e46-9d75-4754-86d0-16943796139e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080720116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.1080720116
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2223529346
Short name	T1112
Test name
Test status
Simulation time	2798140900 ps
CPU time	53.53 seconds
Started	Jul 06 05:52:55 PM PDT 24
Finished	Jul 06 05:53:49 PM PDT 24
Peak memory	260936 kb
Host	smart-0c735d28-4885-4453-b5ee-9394178cc074
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223529346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.2223529346
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.2419485058
Short name	T819
Test name
Test status
Simulation time	2063996000 ps
CPU time	155.43 seconds
Started	Jul 06 05:52:59 PM PDT 24
Finished	Jul 06 05:55:35 PM PDT 24
Peak memory	294032 kb
Host	smart-b22662c8-a481-40ca-ad8d-4097e676dbd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419485058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_intr_rd.2419485058
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3983427205
Short name	T471
Test name
Test status
Simulation time	8069354700 ps
CPU time	211.07 seconds
Started	Jul 06 05:53:01 PM PDT 24
Finished	Jul 06 05:56:32 PM PDT 24
Peak memory	294016 kb
Host	smart-4893b905-db3a-4d60-9496-448c6ac45e59
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983427205 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3983427205
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.4120413652
Short name	T854
Test name
Test status
Simulation time	2547402200 ps
CPU time	64 seconds
Started	Jul 06 05:52:59 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	262692 kb
Host	smart-19ac8249-5dbf-4542-86fd-e905dc8e99f9
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120413652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4 120413652
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2282125332
Short name	T180
Test name
Test status
Simulation time	19581400 ps
CPU time	13.57 seconds
Started	Jul 06 05:53:05 PM PDT 24
Finished	Jul 06 05:53:19 PM PDT 24
Peak memory	260848 kb
Host	smart-351583e3-a62e-461b-9be9-9aec6b94a9a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282125332 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2282125332
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.915607332
Short name	T1105
Test name
Test status
Simulation time	8537299600 ps
CPU time	122.26 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 05:54:55 PM PDT 24
Peak memory	265096 kb
Host	smart-04c4c60a-ec12-4bf1-b718-986418102836
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915607332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.915607332
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.1204471205
Short name	T1044
Test name
Test status
Simulation time	248763800 ps
CPU time	132.76 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 05:55:06 PM PDT 24
Peak memory	260028 kb
Host	smart-8686f58a-e7a9-4c29-a181-ac7da512249f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204471205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.1204471205
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.3334829400
Short name	T786
Test name
Test status
Simulation time	64761700 ps
CPU time	316.25 seconds
Started	Jul 06 05:52:56 PM PDT 24
Finished	Jul 06 05:58:12 PM PDT 24
Peak memory	263068 kb
Host	smart-9ed58028-e0fa-43d3-b99e-aed0170e4050
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3334829400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3334829400
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.2326785546
Short name	T617
Test name
Test status
Simulation time	93743700 ps
CPU time	13.58 seconds
Started	Jul 06 05:52:59 PM PDT 24
Finished	Jul 06 05:53:13 PM PDT 24
Peak memory	265256 kb
Host	smart-b2f97b9c-02fe-43a7-a39a-c40981b06d74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326785546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.2326785546
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.3738518629
Short name	T914
Test name
Test status
Simulation time	3009188600 ps
CPU time	831.21 seconds
Started	Jul 06 05:52:53 PM PDT 24
Finished	Jul 06 06:06:45 PM PDT 24
Peak memory	284448 kb
Host	smart-17485de0-0aa8-4d65-8e8e-392796b8626e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3738518629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3738518629
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.109382662
Short name	T554
Test name
Test status
Simulation time	219154100 ps
CPU time	33.99 seconds
Started	Jul 06 05:53:00 PM PDT 24
Finished	Jul 06 05:53:34 PM PDT 24
Peak memory	275664 kb
Host	smart-0d6e404e-77c1-4964-a95a-bf040f2beaa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109382662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_re_evict.109382662
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.2363445911
Short name	T1001
Test name
Test status
Simulation time	2239112100 ps
CPU time	123.26 seconds
Started	Jul 06 05:52:58 PM PDT 24
Finished	Jul 06 05:55:02 PM PDT 24
Peak memory	290412 kb
Host	smart-bbaf8f48-27df-43b2-b5e3-6ddb3d4cb89a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363445911 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.2363445911
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.2013019300
Short name	T217
Test name
Test status
Simulation time	25221679400 ps
CPU time	601.41 seconds
Started	Jul 06 05:53:02 PM PDT 24
Finished	Jul 06 06:03:04 PM PDT 24
Peak memory	314260 kb
Host	smart-cf0f6a8e-98ed-456d-872d-57ca4bf924bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013019300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.2013019300
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.525378018
Short name	T1018
Test name
Test status
Simulation time	38534800 ps
CPU time	28.14 seconds
Started	Jul 06 05:53:00 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	268516 kb
Host	smart-76d135ed-9dc0-4f68-9d5d-e0131186eeb8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525378018 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.525378018
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.3893361105
Short name	T392
Test name
Test status
Simulation time	1470915200 ps
CPU time	70.2 seconds
Started	Jul 06 05:53:02 PM PDT 24
Finished	Jul 06 05:54:13 PM PDT 24
Peak memory	263344 kb
Host	smart-efe78989-c52e-4181-a3e9-942c4f48919c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893361105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3893361105
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.2655487170
Short name	T56
Test name
Test status
Simulation time	132632500 ps
CPU time	51.03 seconds
Started	Jul 06 05:52:54 PM PDT 24
Finished	Jul 06 05:53:45 PM PDT 24
Peak memory	269908 kb
Host	smart-6e92299e-e3be-46ff-8ee0-ae71706f8cd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655487170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2655487170
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.2676993562
Short name	T620
Test name
Test status
Simulation time	23706232600 ps
CPU time	224.39 seconds
Started	Jul 06 05:53:01 PM PDT 24
Finished	Jul 06 05:56:45 PM PDT 24
Peak memory	265280 kb
Host	smart-35b3df75-4607-4b9f-af1f-f7aa6d47dad7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676993562 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.2676993562
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.1399744130
Short name	T718
Test name
Test status
Simulation time	36845300 ps
CPU time	14.22 seconds
Started	Jul 06 05:53:16 PM PDT 24
Finished	Jul 06 05:53:30 PM PDT 24
Peak memory	258340 kb
Host	smart-4e81fed7-5070-40cf-a754-a310ff4767f8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399744130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 1399744130
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.3776821826
Short name	T628
Test name
Test status
Simulation time	139010100 ps
CPU time	13.33 seconds
Started	Jul 06 05:53:12 PM PDT 24
Finished	Jul 06 05:53:26 PM PDT 24
Peak memory	284484 kb
Host	smart-7f5e0ff4-ad32-479a-8194-76070c4b8a17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776821826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3776821826
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1545074659
Short name	T936
Test name
Test status
Simulation time	10023737800 ps
CPU time	72.66 seconds
Started	Jul 06 05:53:16 PM PDT 24
Finished	Jul 06 05:54:29 PM PDT 24
Peak memory	299028 kb
Host	smart-105b4192-d482-44b9-a09c-10bba284141d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545074659 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1545074659
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.670840045
Short name	T1053
Test name
Test status
Simulation time	14949900 ps
CPU time	13.52 seconds
Started	Jul 06 05:53:17 PM PDT 24
Finished	Jul 06 05:53:31 PM PDT 24
Peak memory	264960 kb
Host	smart-dcc4e5b9-fa62-4393-a99e-6b6a59cdec0a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670840045 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.670840045
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.1274668168
Short name	T186
Test name
Test status
Simulation time	80138136700 ps
CPU time	877.15 seconds
Started	Jul 06 05:53:05 PM PDT 24
Finished	Jul 06 06:07:43 PM PDT 24
Peak memory	262212 kb
Host	smart-620f34ad-84c2-4449-8c8a-748cc6ff124f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274668168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.1274668168
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2400762107
Short name	T443
Test name
Test status
Simulation time	921409200 ps
CPU time	46.16 seconds
Started	Jul 06 05:53:05 PM PDT 24
Finished	Jul 06 05:53:52 PM PDT 24
Peak memory	260896 kb
Host	smart-5d732442-e2eb-4a73-bd82-bad9dfa519cf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400762107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.2400762107
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.486623195
Short name	T680
Test name
Test status
Simulation time	564355500 ps
CPU time	121.02 seconds
Started	Jul 06 05:53:11 PM PDT 24
Finished	Jul 06 05:55:13 PM PDT 24
Peak memory	291540 kb
Host	smart-fdecd2ca-2124-436d-a61c-e7e332e40a21
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486623195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas h_ctrl_intr_rd.486623195
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1603124768
Short name	T551
Test name
Test status
Simulation time	11845077500 ps
CPU time	146.37 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:55:36 PM PDT 24
Peak memory	291996 kb
Host	smart-54d604cc-11e9-4d66-a8bc-583b57cef643
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603124768 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1603124768
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.1505139014
Short name	T411
Test name
Test status
Simulation time	3386917100 ps
CPU time	72.04 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 05:54:17 PM PDT 24
Peak memory	260680 kb
Host	smart-a2ca5d08-809d-473a-b752-ebafff3ac42c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505139014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1 505139014
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.552058973
Short name	T472
Test name
Test status
Simulation time	46308000 ps
CPU time	13.27 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:53:23 PM PDT 24
Peak memory	261168 kb
Host	smart-18a36c18-2a9c-4270-9084-da0100871102
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552058973 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.552058973
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.1084617723
Short name	T143
Test name
Test status
Simulation time	24207280200 ps
CPU time	941.41 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 06:08:46 PM PDT 24
Peak memory	274576 kb
Host	smart-07be75ba-f366-46c4-89d8-64a03bcefe73
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084617723 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1084617723
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.2145478019
Short name	T594
Test name
Test status
Simulation time	167900800 ps
CPU time	135.36 seconds
Started	Jul 06 05:53:03 PM PDT 24
Finished	Jul 06 05:55:19 PM PDT 24
Peak memory	260072 kb
Host	smart-de3a394b-747e-4e58-bb43-f2b50280544e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145478019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.2145478019
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.2477944762
Short name	T515
Test name
Test status
Simulation time	1436276700 ps
CPU time	344.43 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 05:58:49 PM PDT 24
Peak memory	263160 kb
Host	smart-0084c4d7-9aa4-4cc5-a669-e7460556023d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2477944762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2477944762
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.483323685
Short name	T908
Test name
Test status
Simulation time	437525800 ps
CPU time	24.24 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:53:34 PM PDT 24
Peak memory	265216 kb
Host	smart-86475636-b02f-4b84-a170-b5b5e1e44fce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483323685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.flash_ctrl_prog_reset.483323685
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.3110648627
Short name	T1047
Test name
Test status
Simulation time	2923845200 ps
CPU time	929.95 seconds
Started	Jul 06 05:53:04 PM PDT 24
Finished	Jul 06 06:08:34 PM PDT 24
Peak memory	285836 kb
Host	smart-872c1cfc-185e-40c5-8467-885ed5bfdff2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110648627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3110648627
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.3160946473
Short name	T222
Test name
Test status
Simulation time	793076600 ps
CPU time	36.54 seconds
Started	Jul 06 05:53:11 PM PDT 24
Finished	Jul 06 05:53:48 PM PDT 24
Peak memory	270508 kb
Host	smart-3816b6df-f942-4072-9c1a-c92b70be81f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160946473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.3160946473
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.634453026
Short name	T428
Test name
Test status
Simulation time	2247143300 ps
CPU time	132.23 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:55:23 PM PDT 24
Peak memory	297372 kb
Host	smart-c4b18beb-2635-4b64-824e-b8d404446cd5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634453026 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.flash_ctrl_ro.634453026
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.56322403
Short name	T888
Test name
Test status
Simulation time	7588651700 ps
CPU time	662.48 seconds
Started	Jul 06 05:53:11 PM PDT 24
Finished	Jul 06 06:04:14 PM PDT 24
Peak memory	314340 kb
Host	smart-e2077e93-8f00-425c-8f84-595b75e4b623
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56322403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.56322403
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.4063362995
Short name	T1016
Test name
Test status
Simulation time	38157000 ps
CPU time	30.45 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:53:41 PM PDT 24
Peak memory	268552 kb
Host	smart-f2f14a2c-dc00-4d56-ac40-65570bd38143
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063362995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.4063362995
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3047766675
Short name	T41
Test name
Test status
Simulation time	77158300 ps
CPU time	30.41 seconds
Started	Jul 06 05:53:12 PM PDT 24
Finished	Jul 06 05:53:43 PM PDT 24
Peak memory	268536 kb
Host	smart-184dba97-aa8a-4b15-882f-7e8636f5dee8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047766675 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3047766675
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.3627710067
Short name	T846
Test name
Test status
Simulation time	1845663100 ps
CPU time	65.81 seconds
Started	Jul 06 05:53:12 PM PDT 24
Finished	Jul 06 05:54:18 PM PDT 24
Peak memory	263816 kb
Host	smart-14fd0bd9-6c40-4a96-a34f-63a28aa10019
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627710067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3627710067
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.1197725351
Short name	T135
Test name
Test status
Simulation time	67954300 ps
CPU time	170.01 seconds
Started	Jul 06 05:53:05 PM PDT 24
Finished	Jul 06 05:55:55 PM PDT 24
Peak memory	277456 kb
Host	smart-b5fa9340-04e2-4312-834a-562b5ffe84b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197725351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1197725351
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.87110307
Short name	T585
Test name
Test status
Simulation time	4937805900 ps
CPU time	173.87 seconds
Started	Jul 06 05:53:10 PM PDT 24
Finished	Jul 06 05:56:04 PM PDT 24
Peak memory	260056 kb
Host	smart-5def99e1-b9c2-4999-958e-e3d29f39b489
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87110307 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_wo.87110307
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.2313185778
Short name	T24
Test name
Test status
Simulation time	13854600 ps
CPU time	13.62 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:49:27 PM PDT 24
Peak memory	261324 kb
Host	smart-5462f137-eec2-4162-9a93-4638f14dd8fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313185778 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2313185778
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.3646534056
Short name	T599
Test name
Test status
Simulation time	167155400 ps
CPU time	13.77 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:49:30 PM PDT 24
Peak memory	258332 kb
Host	smart-6d2d41a7-557e-440e-97f0-ab800d481ea8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646534056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3 646534056
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.3307134806
Short name	T369
Test name
Test status
Simulation time	48497900 ps
CPU time	14 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:49:30 PM PDT 24
Peak memory	265040 kb
Host	smart-22c03756-8268-4a1b-9b6b-b5e33d6f9041
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307134806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.3307134806
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.80557638
Short name	T650
Test name
Test status
Simulation time	47727600 ps
CPU time	13.35 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:22 PM PDT 24
Peak memory	284284 kb
Host	smart-2379a488-a264-4b8c-a93c-b0ff891a86ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80557638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.80557638
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.3690085956
Short name	T63
Test name
Test status
Simulation time	75711700 ps
CPU time	21.64 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:49:30 PM PDT 24
Peak memory	265676 kb
Host	smart-8bef8444-0baf-46e6-bb7d-3a1ef16dce4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690085956 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.3690085956
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.1245504749
Short name	T237
Test name
Test status
Simulation time	48541538300 ps
CPU time	2333 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 06:28:02 PM PDT 24
Peak memory	262820 kb
Host	smart-e224c8d2-99ea-45df-8ac6-1941c57d25ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1245504749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1245504749
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.3599762493
Short name	T92
Test name
Test status
Simulation time	1164936500 ps
CPU time	3042.76 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 06:39:51 PM PDT 24
Peak memory	264348 kb
Host	smart-044ec1cd-c9cf-4206-8174-39c03cbefe15
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599762493 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3599762493
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.699358383
Short name	T616
Test name
Test status
Simulation time	383774200 ps
CPU time	927.24 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 06:04:41 PM PDT 24
Peak memory	273164 kb
Host	smart-9612f589-7a21-4b51-980d-ab217d55ec71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699358383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.699358383
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.3414962480
Short name	T960
Test name
Test status
Simulation time	4819574600 ps
CPU time	40.27 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:49:50 PM PDT 24
Peak memory	262724 kb
Host	smart-f74e9759-60f0-4237-bb16-ca59f19c80ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414962480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.flash_ctrl_fs_sup.3414962480
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.1364121631
Short name	T833
Test name
Test status
Simulation time	48916230100 ps
CPU time	4153.23 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 06:58:28 PM PDT 24
Peak memory	264768 kb
Host	smart-9b395524-3143-4234-9f88-1b20388483ae
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364121631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c trl_full_mem_access.1364121631
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.403404536
Short name	T881
Test name
Test status
Simulation time	26966000 ps
CPU time	30.3 seconds
Started	Jul 06 05:49:17 PM PDT 24
Finished	Jul 06 05:49:48 PM PDT 24
Peak memory	275620 kb
Host	smart-1b4d8b3d-b925-4603-8c29-add625223ef1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403404536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_host_addr_infection.403404536
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.292872594
Short name	T1048
Test name
Test status
Simulation time	30785700 ps
CPU time	49.45 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:49:56 PM PDT 24
Peak memory	265240 kb
Host	smart-b709a54c-d84b-4f6f-9bb9-a8b4249f6055
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=292872594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.292872594
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3397444644
Short name	T193
Test name
Test status
Simulation time	10036914500 ps
CPU time	49.49 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:50:06 PM PDT 24
Peak memory	275564 kb
Host	smart-73847883-b943-4585-b624-1620c9f5f0f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397444644 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3397444644
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2745210661
Short name	T809
Test name
Test status
Simulation time	53387000 ps
CPU time	13.45 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:49:28 PM PDT 24
Peak memory	264940 kb
Host	smart-dab397ad-49e9-4d38-b2e3-18e7d54edbc4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745210661 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2745210661
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.3787932484
Short name	T1009
Test name
Test status
Simulation time	272165210700 ps
CPU time	2103.12 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 06:24:11 PM PDT 24
Peak memory	260864 kb
Host	smart-92a31f0e-2775-4d15-a532-8813c7a12517
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787932484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_hw_rma.3787932484
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3413737950
Short name	T926
Test name
Test status
Simulation time	350306861900 ps
CPU time	908.16 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 06:04:16 PM PDT 24
Peak memory	263956 kb
Host	smart-ab677ac7-5721-436a-a44a-2e9c0f5872a1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413737950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.3413737950
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2578569904
Short name	T1107
Test name
Test status
Simulation time	1241055400 ps
CPU time	51.48 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:49:59 PM PDT 24
Peak memory	263160 kb
Host	smart-7e9aa720-e6d6-483f-9491-210b30d2c800
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578569904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.2578569904
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.238956968
Short name	T165
Test name
Test status
Simulation time	4140884500 ps
CPU time	560.13 seconds
Started	Jul 06 05:49:12 PM PDT 24
Finished	Jul 06 05:58:33 PM PDT 24
Peak memory	338256 kb
Host	smart-a87e4094-f331-4586-b65a-3b4bc9724bfa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238956968 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.flash_ctrl_integrity.238956968
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.4176872523
Short name	T824
Test name
Test status
Simulation time	782121100 ps
CPU time	158.55 seconds
Started	Jul 06 05:49:09 PM PDT 24
Finished	Jul 06 05:51:48 PM PDT 24
Peak memory	292372 kb
Host	smart-14c4af2f-e6d6-440b-a3ef-68940f128dc7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176872523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.4176872523
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3098460144
Short name	T544
Test name
Test status
Simulation time	5983901700 ps
CPU time	130.55 seconds
Started	Jul 06 05:49:08 PM PDT 24
Finished	Jul 06 05:51:19 PM PDT 24
Peak memory	293040 kb
Host	smart-0bfa75b4-29b2-433b-9b5b-957d9d487b37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098460144 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3098460144
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.1577648591
Short name	T721
Test name
Test status
Simulation time	4825512800 ps
CPU time	63.67 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:50:14 PM PDT 24
Peak memory	260568 kb
Host	smart-5bedf820-8d75-42a4-a60c-137a0e2ab7e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577648591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.1577648591
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1774226335
Short name	T33
Test name
Test status
Simulation time	25301739300 ps
CPU time	212.63 seconds
Started	Jul 06 05:49:09 PM PDT 24
Finished	Jul 06 05:52:42 PM PDT 24
Peak memory	260736 kb
Host	smart-570c8484-c942-48cc-8baf-9e806d5dd955
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177 4226335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1774226335
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.2694168600
Short name	T892
Test name
Test status
Simulation time	1980798600 ps
CPU time	61.22 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:50:09 PM PDT 24
Peak memory	260848 kb
Host	smart-be3746f3-1d6e-449f-a980-2c4a67546c6e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694168600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2694168600
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3686731170
Short name	T996
Test name
Test status
Simulation time	46141100 ps
CPU time	13.62 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:49:32 PM PDT 24
Peak memory	265036 kb
Host	smart-59eaf6c1-5ce1-42ae-9dda-c22b6c65f0ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686731170 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3686731170
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.2236054701
Short name	T962
Test name
Test status
Simulation time	955646400 ps
CPU time	69.97 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:50:21 PM PDT 24
Peak memory	260672 kb
Host	smart-90e5bec6-ec18-4391-bb52-cbb6f9937903
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236054701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2236054701
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.610151148
Short name	T121
Test name
Test status
Simulation time	46206100 ps
CPU time	109.28 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 05:50:54 PM PDT 24
Peak memory	260204 kb
Host	smart-4e33bff3-bdf8-47ff-922e-c5cf89a352ea
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610151148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp _reset.610151148
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.2126591146
Short name	T977
Test name
Test status
Simulation time	6372130200 ps
CPU time	262.01 seconds
Started	Jul 06 05:49:12 PM PDT 24
Finished	Jul 06 05:53:35 PM PDT 24
Peak memory	281704 kb
Host	smart-1d743d36-ee8e-456e-883d-31fd63ed7769
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126591146 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2126591146
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.550866610
Short name	T230
Test name
Test status
Simulation time	83558700 ps
CPU time	14.82 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:49:30 PM PDT 24
Peak memory	265092 kb
Host	smart-a883bbcd-8bea-44da-95e9-e4ae97e7603f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=550866610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.550866610
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.2458974450
Short name	T643
Test name
Test status
Simulation time	60469100 ps
CPU time	279.82 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:53:46 PM PDT 24
Peak memory	263168 kb
Host	smart-395e64ff-cfe0-4e8c-bed7-581a6f35bbc7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2458974450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2458974450
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2691400251
Short name	T228
Test name
Test status
Simulation time	14894000 ps
CPU time	14.14 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:49:30 PM PDT 24
Peak memory	264972 kb
Host	smart-4234c0ed-e92b-4556-9514-79b2abcc590b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691400251 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2691400251
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.1196856331
Short name	T129
Test name
Test status
Simulation time	95528900 ps
CPU time	13.7 seconds
Started	Jul 06 05:49:11 PM PDT 24
Finished	Jul 06 05:49:25 PM PDT 24
Peak memory	259072 kb
Host	smart-7e93382f-d7fd-4614-b677-4347e524752d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196856331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.1196856331
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.1711525279
Short name	T1113
Test name
Test status
Simulation time	201018300 ps
CPU time	873.28 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 06:03:46 PM PDT 24
Peak memory	284124 kb
Host	smart-8758e0b6-c25e-4784-8404-b86d0c708c28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711525279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1711525279
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.386437058
Short name	T234
Test name
Test status
Simulation time	1388839400 ps
CPU time	193.3 seconds
Started	Jul 06 05:49:03 PM PDT 24
Finished	Jul 06 05:52:17 PM PDT 24
Peak memory	262828 kb
Host	smart-c49b083b-eba6-4f05-a90a-6157fe0bd2cc
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=386437058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.386437058
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.3223986792
Short name	T641
Test name
Test status
Simulation time	111764300 ps
CPU time	32.86 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:49:46 PM PDT 24
Peak memory	275892 kb
Host	smart-c65401aa-5633-42e2-93ca-c431d26fe84c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223986792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.3223986792
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.1095138117
Short name	T691
Test name
Test status
Simulation time	157504200 ps
CPU time	34.89 seconds
Started	Jul 06 05:49:13 PM PDT 24
Finished	Jul 06 05:49:49 PM PDT 24
Peak memory	278692 kb
Host	smart-3a337ddd-b7fb-46eb-bd81-dd97db29d7e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095138117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.1095138117
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1210926315
Short name	T377
Test name
Test status
Simulation time	62016200 ps
CPU time	22.91 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	265392 kb
Host	smart-d80b98bb-98e9-4315-b80a-10748f1ac3e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210926315 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1210926315
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2752341950
Short name	T42
Test name
Test status
Simulation time	24238500 ps
CPU time	22.94 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	265436 kb
Host	smart-6581005e-321e-4e54-850e-f7d0c9131759
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752341950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.2752341950
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.1263436871
Short name	T201
Test name
Test status
Simulation time	163790537000 ps
CPU time	922.69 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 06:04:39 PM PDT 24
Peak memory	262704 kb
Host	smart-f4a5fa10-be72-4011-a26d-dad49a4206dc
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263436871 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.1263436871
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.672958405
Short name	T499
Test name
Test status
Simulation time	2387938500 ps
CPU time	108.83 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:50:55 PM PDT 24
Peak memory	282076 kb
Host	smart-9b8aa9d4-73ba-4ccd-b57c-34f86dfcd4c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672958405 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.flash_ctrl_ro.672958405
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.3607894446
Short name	T163
Test name
Test status
Simulation time	2716648700 ps
CPU time	149.24 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:51:40 PM PDT 24
Peak memory	282780 kb
Host	smart-2c263826-1b2e-417a-b278-25005edf929f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3607894446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3607894446
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.2550916577
Short name	T903
Test name
Test status
Simulation time	3702624400 ps
CPU time	141.25 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:51:31 PM PDT 24
Peak memory	281760 kb
Host	smart-e4d9592c-87a4-4903-9839-9def21cdf87a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550916577 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2550916577
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.633584331
Short name	T530
Test name
Test status
Simulation time	14445054700 ps
CPU time	557.42 seconds
Started	Jul 06 05:49:05 PM PDT 24
Finished	Jul 06 05:58:23 PM PDT 24
Peak memory	314332 kb
Host	smart-b3c050f9-5bcf-4dc9-941d-6dd35caf01d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633584331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.633584331
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.3826727507
Short name	T637
Test name
Test status
Simulation time	43010600 ps
CPU time	28.1 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:49:42 PM PDT 24
Peak memory	275516 kb
Host	smart-9a77d611-6351-4925-b70b-2a8cc80fece8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826727507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.3826727507
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2818259627
Short name	T1086
Test name
Test status
Simulation time	136630200 ps
CPU time	31.54 seconds
Started	Jul 06 05:49:09 PM PDT 24
Finished	Jul 06 05:49:41 PM PDT 24
Peak memory	275684 kb
Host	smart-4918c0c5-2758-4fc5-b78f-08039604de21
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818259627 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2818259627
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.3358575364
Short name	T17
Test name
Test status
Simulation time	3201164900 ps
CPU time	4727.12 seconds
Started	Jul 06 05:49:12 PM PDT 24
Finished	Jul 06 07:08:00 PM PDT 24
Peak memory	288592 kb
Host	smart-1102f97b-4b4f-4b0c-9a30-b9b657c9bf06
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358575364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3358575364
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.3513770119
Short name	T35
Test name
Test status
Simulation time	1317938100 ps
CPU time	63.78 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:50:14 PM PDT 24
Peak memory	263612 kb
Host	smart-f02f705f-d9e7-457f-b706-672a80a2d6ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513770119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3513770119
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.2214295366
Short name	T734
Test name
Test status
Simulation time	1639797500 ps
CPU time	87.25 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:50:38 PM PDT 24
Peak memory	265404 kb
Host	smart-8b5b13b7-d6b8-4f55-bc49-9a6a6c0c93b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214295366 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.2214295366
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.1325771172
Short name	T1073
Test name
Test status
Simulation time	2234612500 ps
CPU time	109.45 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:51:04 PM PDT 24
Peak memory	265456 kb
Host	smart-e4933513-7b88-43c1-9f84-88af214d9918
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325771172 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_serr_counter.1325771172
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.1431804669
Short name	T785
Test name
Test status
Simulation time	21861600 ps
CPU time	74.95 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:50:26 PM PDT 24
Peak memory	276740 kb
Host	smart-2f570132-b533-4128-ac56-f726ec3bbe0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431804669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.1431804669
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.3153175512
Short name	T626
Test name
Test status
Simulation time	27283000 ps
CPU time	26.43 seconds
Started	Jul 06 05:49:06 PM PDT 24
Finished	Jul 06 05:49:33 PM PDT 24
Peak memory	259556 kb
Host	smart-10417378-5d67-42ba-a479-c7829136ecb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153175512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3153175512
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.2640886096
Short name	T559
Test name
Test status
Simulation time	93633000 ps
CPU time	257.45 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	275428 kb
Host	smart-71123c16-bf94-4566-b124-72ac743a4124
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640886096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.2640886096
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.1972692414
Short name	T541
Test name
Test status
Simulation time	50117700 ps
CPU time	24.02 seconds
Started	Jul 06 05:49:07 PM PDT 24
Finished	Jul 06 05:49:32 PM PDT 24
Peak memory	259768 kb
Host	smart-c4fa9268-563d-43a9-a161-12f5ce55bff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972692414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1972692414
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.1638332601
Short name	T1061
Test name
Test status
Simulation time	8223356200 ps
CPU time	187.24 seconds
Started	Jul 06 05:49:04 PM PDT 24
Finished	Jul 06 05:52:12 PM PDT 24
Peak memory	261112 kb
Host	smart-32590a07-e835-4022-938f-6fecb1295fa0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638332601 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_wo.1638332601
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.667953656
Short name	T10
Test name
Test status
Simulation time	44679700 ps
CPU time	14.99 seconds
Started	Jul 06 05:49:10 PM PDT 24
Finished	Jul 06 05:49:26 PM PDT 24
Peak memory	264964 kb
Host	smart-19db88c4-207c-44de-8fa5-d4e4f8591cc4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667953656 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.667953656
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.1262703258
Short name	T632
Test name
Test status
Simulation time	132247700 ps
CPU time	13.87 seconds
Started	Jul 06 05:53:16 PM PDT 24
Finished	Jul 06 05:53:30 PM PDT 24
Peak memory	258304 kb
Host	smart-127e7851-ce66-43c1-a8c0-a5e169aecdeb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262703258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test. 1262703258
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.2312080785
Short name	T1118
Test name
Test status
Simulation time	17112900 ps
CPU time	15.79 seconds
Started	Jul 06 05:53:16 PM PDT 24
Finished	Jul 06 05:53:32 PM PDT 24
Peak memory	274992 kb
Host	smart-79e57fe8-994c-455a-9d1e-7cfb23fc19c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312080785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2312080785
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.1500935333
Short name	T532
Test name
Test status
Simulation time	26653600 ps
CPU time	21.87 seconds
Started	Jul 06 05:53:17 PM PDT 24
Finished	Jul 06 05:53:39 PM PDT 24
Peak memory	273620 kb
Host	smart-cfb9770a-a5f7-4d1e-afe1-9180f8900ae6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500935333 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.1500935333
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2640755333
Short name	T311
Test name
Test status
Simulation time	12384125400 ps
CPU time	129.23 seconds
Started	Jul 06 05:53:16 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	263188 kb
Host	smart-f580a4f6-b5fd-4aac-bf30-c340f64cf30a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640755333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.2640755333
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.3393482954
Short name	T313
Test name
Test status
Simulation time	7158526500 ps
CPU time	219.24 seconds
Started	Jul 06 05:53:17 PM PDT 24
Finished	Jul 06 05:56:56 PM PDT 24
Peak memory	284948 kb
Host	smart-ee6a7edd-8d44-4f73-9288-5cb4dd8d0fc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393482954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.3393482954
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.359252492
Short name	T531
Test name
Test status
Simulation time	11463099100 ps
CPU time	129.16 seconds
Started	Jul 06 05:53:14 PM PDT 24
Finished	Jul 06 05:55:24 PM PDT 24
Peak memory	292988 kb
Host	smart-216c5af1-8f41-4434-9fa2-8d5ed8f9689b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359252492 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.359252492
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.247940288
Short name	T633
Test name
Test status
Simulation time	134038500 ps
CPU time	110.55 seconds
Started	Jul 06 05:53:17 PM PDT 24
Finished	Jul 06 05:55:08 PM PDT 24
Peak memory	261088 kb
Host	smart-502c5a34-769d-434b-8d5a-e51f6412db38
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247940288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ot p_reset.247940288
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.155529724
Short name	T1102
Test name
Test status
Simulation time	38134600 ps
CPU time	13.41 seconds
Started	Jul 06 05:53:14 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	259008 kb
Host	smart-32c86df6-79c5-430c-a1d3-058f2a985b36
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155529724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 20.flash_ctrl_prog_reset.155529724
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict.943263152
Short name	T925
Test name
Test status
Simulation time	32194500 ps
CPU time	28.55 seconds
Started	Jul 06 05:53:15 PM PDT 24
Finished	Jul 06 05:53:43 PM PDT 24
Peak memory	275652 kb
Host	smart-2f7f9fcd-0a31-4389-950f-26cd264d2248
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943263152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_rw_evict.943263152
Directory	/workspace/20.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.3917471278
Short name	T1070
Test name
Test status
Simulation time	27789600 ps
CPU time	30.72 seconds
Started	Jul 06 05:53:18 PM PDT 24
Finished	Jul 06 05:53:49 PM PDT 24
Peak memory	268492 kb
Host	smart-614ca9fc-f927-43fd-adf6-88f36ecc9ccc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917471278 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.3917471278
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.1426112903
Short name	T590
Test name
Test status
Simulation time	1893877200 ps
CPU time	71.18 seconds
Started	Jul 06 05:53:15 PM PDT 24
Finished	Jul 06 05:54:27 PM PDT 24
Peak memory	264712 kb
Host	smart-c29389c8-82c1-4905-8523-01c95b1f1656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426112903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1426112903
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.61084151
Short name	T573
Test name
Test status
Simulation time	51452200 ps
CPU time	148.59 seconds
Started	Jul 06 05:53:15 PM PDT 24
Finished	Jul 06 05:55:44 PM PDT 24
Peak memory	277088 kb
Host	smart-474c6622-2160-43be-ab23-afd48fa222c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61084151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.61084151
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.4233406362
Short name	T605
Test name
Test status
Simulation time	252571400 ps
CPU time	14.44 seconds
Started	Jul 06 05:53:27 PM PDT 24
Finished	Jul 06 05:53:42 PM PDT 24
Peak memory	265268 kb
Host	smart-a09df203-b158-433f-94ca-cfd52323a9cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233406362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 4233406362
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.1825103425
Short name	T878
Test name
Test status
Simulation time	53513200 ps
CPU time	15.83 seconds
Started	Jul 06 05:53:26 PM PDT 24
Finished	Jul 06 05:53:42 PM PDT 24
Peak memory	274896 kb
Host	smart-a9469c29-a116-4a39-87ef-4dca9cd231f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825103425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1825103425
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.4052372573
Short name	T381
Test name
Test status
Simulation time	12659200 ps
CPU time	20.92 seconds
Started	Jul 06 05:53:26 PM PDT 24
Finished	Jul 06 05:53:47 PM PDT 24
Peak memory	273572 kb
Host	smart-107dd0fc-8ae9-42e0-aafa-ce6ed001ee6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052372573 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.4052372573
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1436521644
Short name	T309
Test name
Test status
Simulation time	6620720500 ps
CPU time	266.36 seconds
Started	Jul 06 05:53:26 PM PDT 24
Finished	Jul 06 05:57:53 PM PDT 24
Peak memory	260988 kb
Host	smart-c9304058-8e72-44c4-895c-54482f53529f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436521644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.1436521644
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.887617100
Short name	T36
Test name
Test status
Simulation time	7659819900 ps
CPU time	216.22 seconds
Started	Jul 06 05:53:21 PM PDT 24
Finished	Jul 06 05:56:57 PM PDT 24
Peak memory	291064 kb
Host	smart-07d8555f-aefa-4556-8a3b-fed11507a238
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887617100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas h_ctrl_intr_rd.887617100
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2873952556
Short name	T329
Test name
Test status
Simulation time	48788108400 ps
CPU time	312.86 seconds
Started	Jul 06 05:53:21 PM PDT 24
Finished	Jul 06 05:58:34 PM PDT 24
Peak memory	290972 kb
Host	smart-61e5793d-0a92-46a1-8904-21280752f386
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873952556 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2873952556
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.2396442363
Short name	T627
Test name
Test status
Simulation time	38086100 ps
CPU time	109.89 seconds
Started	Jul 06 05:53:19 PM PDT 24
Finished	Jul 06 05:55:09 PM PDT 24
Peak memory	261236 kb
Host	smart-65767be7-df59-4493-bf58-31004526a8b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396442363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.2396442363
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.1481323530
Short name	T886
Test name
Test status
Simulation time	20251000 ps
CPU time	13.48 seconds
Started	Jul 06 05:53:22 PM PDT 24
Finished	Jul 06 05:53:35 PM PDT 24
Peak memory	265304 kb
Host	smart-c5d9f79f-4787-486f-b9f2-c0bd055a751a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481323530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.1481323530
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.279134688
Short name	T355
Test name
Test status
Simulation time	30956500 ps
CPU time	30.76 seconds
Started	Jul 06 05:53:21 PM PDT 24
Finished	Jul 06 05:53:52 PM PDT 24
Peak memory	275684 kb
Host	smart-6d599ea0-f248-4e37-af05-6b685ad5b2b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279134688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_rw_evict.279134688
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.2883126290
Short name	T695
Test name
Test status
Simulation time	64982600 ps
CPU time	30.76 seconds
Started	Jul 06 05:53:25 PM PDT 24
Finished	Jul 06 05:53:57 PM PDT 24
Peak memory	273656 kb
Host	smart-ac9d8f4b-122e-457a-b35d-cf1438f6fefe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883126290 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.2883126290
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.3004374979
Short name	T402
Test name
Test status
Simulation time	533534800 ps
CPU time	69.22 seconds
Started	Jul 06 05:53:27 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	264852 kb
Host	smart-0b5fe942-db68-4496-8d33-365e225aba6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004374979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3004374979
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.76925113
Short name	T561
Test name
Test status
Simulation time	68567400 ps
CPU time	100.06 seconds
Started	Jul 06 05:53:20 PM PDT 24
Finished	Jul 06 05:55:01 PM PDT 24
Peak memory	277356 kb
Host	smart-5b579062-8bc8-4228-97fb-11a0457b7a81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76925113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.76925113
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.2220096427
Short name	T431
Test name
Test status
Simulation time	40564100 ps
CPU time	13.53 seconds
Started	Jul 06 05:53:31 PM PDT 24
Finished	Jul 06 05:53:45 PM PDT 24
Peak memory	265156 kb
Host	smart-01c98075-e384-4519-bcfd-ecf66cbbd492
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220096427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test. 2220096427
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.1401217658
Short name	T862
Test name
Test status
Simulation time	29372100 ps
CPU time	16.03 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:53:48 PM PDT 24
Peak memory	274912 kb
Host	smart-5d3a420f-3b41-4231-b1c0-f33d01641317
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401217658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1401217658
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.1345127327
Short name	T47
Test name
Test status
Simulation time	38800400 ps
CPU time	21.73 seconds
Started	Jul 06 05:53:38 PM PDT 24
Finished	Jul 06 05:54:00 PM PDT 24
Peak memory	273548 kb
Host	smart-84adff58-cce2-4039-8b6c-1176bbf4a49b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345127327 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.1345127327
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2922020218
Short name	T1065
Test name
Test status
Simulation time	2504942400 ps
CPU time	65.54 seconds
Started	Jul 06 05:53:26 PM PDT 24
Finished	Jul 06 05:54:31 PM PDT 24
Peak memory	263260 kb
Host	smart-a1402f0d-f010-4ce6-b002-989f56a87d4a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922020218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.2922020218
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.1441014930
Short name	T995
Test name
Test status
Simulation time	460991500 ps
CPU time	114.57 seconds
Started	Jul 06 05:53:26 PM PDT 24
Finished	Jul 06 05:55:21 PM PDT 24
Peak memory	291020 kb
Host	smart-6fb11b91-6ef6-4efa-b396-0f708ee017f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441014930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.1441014930
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1959785384
Short name	T1005
Test name
Test status
Simulation time	27288607100 ps
CPU time	348.75 seconds
Started	Jul 06 05:53:25 PM PDT 24
Finished	Jul 06 05:59:15 PM PDT 24
Peak memory	284816 kb
Host	smart-717c1e71-6e9f-494f-a993-741779bf11f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959785384 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1959785384
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.3166315897
Short name	T494
Test name
Test status
Simulation time	95005500 ps
CPU time	14.83 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:53:47 PM PDT 24
Peak memory	259760 kb
Host	smart-6a397f67-5f5f-4015-b053-63dcb39d3f2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166315897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.3166315897
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.247663776
Short name	T577
Test name
Test status
Simulation time	27794300 ps
CPU time	30.16 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:54:02 PM PDT 24
Peak memory	274808 kb
Host	smart-92cea1b7-6e21-4872-ab99-19635444f7f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247663776 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.247663776
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.1776175888
Short name	T1050
Test name
Test status
Simulation time	93288600 ps
CPU time	75.84 seconds
Started	Jul 06 05:53:25 PM PDT 24
Finished	Jul 06 05:54:41 PM PDT 24
Peak memory	275644 kb
Host	smart-4fffdb77-0c93-45c8-a564-eaa5c8c534cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776175888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1776175888
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.1625329034
Short name	T535
Test name
Test status
Simulation time	52904700 ps
CPU time	13.67 seconds
Started	Jul 06 05:53:38 PM PDT 24
Finished	Jul 06 05:53:51 PM PDT 24
Peak memory	258492 kb
Host	smart-675a692a-ab87-4a38-8659-59de4eb70457
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625329034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test. 1625329034
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.2669690762
Short name	T676
Test name
Test status
Simulation time	30038300 ps
CPU time	15.73 seconds
Started	Jul 06 05:53:38 PM PDT 24
Finished	Jul 06 05:53:54 PM PDT 24
Peak memory	274912 kb
Host	smart-7e0ff744-d22d-4c72-8237-6084fa04c6d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669690762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2669690762
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.2020478661
Short name	T738
Test name
Test status
Simulation time	38044700 ps
CPU time	20.2 seconds
Started	Jul 06 05:53:39 PM PDT 24
Finished	Jul 06 05:53:59 PM PDT 24
Peak memory	274720 kb
Host	smart-baa5bf9e-2d2f-4d4b-a307-20277719eb9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020478661 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.2020478661
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.490919331
Short name	T935
Test name
Test status
Simulation time	817122600 ps
CPU time	56.48 seconds
Started	Jul 06 05:53:31 PM PDT 24
Finished	Jul 06 05:54:28 PM PDT 24
Peak memory	263140 kb
Host	smart-e07a6c79-b536-4fbb-a658-72b39f4764ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490919331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h w_sec_otp.490919331
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.2349596087
Short name	T866
Test name
Test status
Simulation time	2622413800 ps
CPU time	137.72 seconds
Started	Jul 06 05:53:34 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	291532 kb
Host	smart-005824b3-5450-4709-b174-ad525757195b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349596087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.2349596087
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2145051154
Short name	T665
Test name
Test status
Simulation time	5931373800 ps
CPU time	129.38 seconds
Started	Jul 06 05:53:33 PM PDT 24
Finished	Jul 06 05:55:42 PM PDT 24
Peak memory	293060 kb
Host	smart-43083e76-26bb-476e-aeec-f52f12296817
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145051154 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2145051154
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.1329152208
Short name	T114
Test name
Test status
Simulation time	36107600 ps
CPU time	133.48 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:55:45 PM PDT 24
Peak memory	261088 kb
Host	smart-5597c9d4-4591-4e2a-8e2a-863cfe11e3d5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329152208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.1329152208
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.1774365470
Short name	T469
Test name
Test status
Simulation time	71736300 ps
CPU time	13.75 seconds
Started	Jul 06 05:53:33 PM PDT 24
Finished	Jul 06 05:53:47 PM PDT 24
Peak memory	259100 kb
Host	smart-8ea958e1-506c-472f-8b8b-ad3733b4d3a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774365470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.1774365470
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.612891372
Short name	T555
Test name
Test status
Simulation time	43377400 ps
CPU time	31.7 seconds
Started	Jul 06 05:53:32 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	275676 kb
Host	smart-057a2346-aed4-47a8-93c1-550239af93d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612891372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_rw_evict.612891372
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.607109340
Short name	T711
Test name
Test status
Simulation time	78977700 ps
CPU time	28.41 seconds
Started	Jul 06 05:53:33 PM PDT 24
Finished	Jul 06 05:54:01 PM PDT 24
Peak memory	275644 kb
Host	smart-69818679-673e-453b-98cc-d4c86e2062af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607109340 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.607109340
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.377309105
Short name	T409
Test name
Test status
Simulation time	3238807500 ps
CPU time	75.76 seconds
Started	Jul 06 05:53:36 PM PDT 24
Finished	Jul 06 05:54:53 PM PDT 24
Peak memory	263756 kb
Host	smart-07208e39-4046-4a3f-956e-a701f27c56ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377309105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.377309105
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.2176904232
Short name	T450
Test name
Test status
Simulation time	90768200 ps
CPU time	100.85 seconds
Started	Jul 06 05:53:37 PM PDT 24
Finished	Jul 06 05:55:18 PM PDT 24
Peak memory	269884 kb
Host	smart-aed6a76b-9771-4c3e-8d22-195cc3686537
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2176904232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2176904232
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.3505536713
Short name	T852
Test name
Test status
Simulation time	113207800 ps
CPU time	13.9 seconds
Started	Jul 06 05:53:43 PM PDT 24
Finished	Jul 06 05:53:57 PM PDT 24
Peak memory	258288 kb
Host	smart-7e794be3-72ec-49ac-8158-04190a30b6d2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505536713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 3505536713
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.2319014348
Short name	T439
Test name
Test status
Simulation time	16369700 ps
CPU time	16.52 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:54:01 PM PDT 24
Peak memory	274944 kb
Host	smart-a055182c-604f-41be-926d-bce602d987cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2319014348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2319014348
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.3899028560
Short name	T660
Test name
Test status
Simulation time	21734400 ps
CPU time	20.61 seconds
Started	Jul 06 05:53:43 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	273616 kb
Host	smart-235c5b97-960e-4b9a-95c6-c98b26627b3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899028560 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.3899028560
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3465870470
Short name	T314
Test name
Test status
Simulation time	8251310800 ps
CPU time	138.58 seconds
Started	Jul 06 05:53:38 PM PDT 24
Finished	Jul 06 05:55:57 PM PDT 24
Peak memory	263300 kb
Host	smart-2953e364-3432-46c0-9326-4c19c4e8e18a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465870470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.3465870470
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2658370275
Short name	T732
Test name
Test status
Simulation time	30059151600 ps
CPU time	143.18 seconds
Started	Jul 06 05:53:42 PM PDT 24
Finished	Jul 06 05:56:05 PM PDT 24
Peak memory	293060 kb
Host	smart-f92951df-4e96-4cde-8abe-f7add66ad52a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658370275 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2658370275
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.695499719
Short name	T519
Test name
Test status
Simulation time	68783100 ps
CPU time	111.37 seconds
Started	Jul 06 05:53:39 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	260348 kb
Host	smart-a05b4c46-bc64-4e51-b427-b42751e533aa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695499719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot p_reset.695499719
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.2643802640
Short name	T922
Test name
Test status
Simulation time	20654600 ps
CPU time	13.88 seconds
Started	Jul 06 05:53:43 PM PDT 24
Finished	Jul 06 05:53:57 PM PDT 24
Peak memory	265284 kb
Host	smart-6a2e8618-53bf-439d-b506-8c26527c6175
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643802640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.2643802640
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.3078878062
Short name	T350
Test name
Test status
Simulation time	62105200 ps
CPU time	27.6 seconds
Started	Jul 06 05:53:42 PM PDT 24
Finished	Jul 06 05:54:10 PM PDT 24
Peak memory	275660 kb
Host	smart-bb53f2d8-2a4b-453a-9d55-f21775b8f4cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078878062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.3078878062
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3341991856
Short name	T1037
Test name
Test status
Simulation time	33123900 ps
CPU time	27.93 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:54:12 PM PDT 24
Peak memory	275676 kb
Host	smart-ff19d418-153b-4703-a41e-cad55be716fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341991856 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3341991856
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.2248256757
Short name	T390
Test name
Test status
Simulation time	404114000 ps
CPU time	58.99 seconds
Started	Jul 06 05:53:43 PM PDT 24
Finished	Jul 06 05:54:42 PM PDT 24
Peak memory	263832 kb
Host	smart-dfb87b5c-6256-465d-acb7-4dd944572397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248256757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2248256757
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.3069583347
Short name	T258
Test name
Test status
Simulation time	277085300 ps
CPU time	73.83 seconds
Started	Jul 06 05:53:40 PM PDT 24
Finished	Jul 06 05:54:54 PM PDT 24
Peak memory	275600 kb
Host	smart-ad036d9e-87b0-4b39-ae99-7e96a99d0045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069583347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3069583347
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.1024434356
Short name	T790
Test name
Test status
Simulation time	155611900 ps
CPU time	14.5 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:54:02 PM PDT 24
Peak memory	258308 kb
Host	smart-77ea0897-4de5-4422-aaa6-36003c6b51a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024434356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 1024434356
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.617103129
Short name	T624
Test name
Test status
Simulation time	18092700 ps
CPU time	16.76 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	284288 kb
Host	smart-1bedf834-1caa-46ea-9250-3681bf935470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617103129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.617103129
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2693257101
Short name	T1036
Test name
Test status
Simulation time	25897249700 ps
CPU time	139.48 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:56:04 PM PDT 24
Peak memory	260608 kb
Host	smart-6445f681-3673-4792-83b9-dc5005299c40
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693257101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.2693257101
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.3980793119
Short name	T1007
Test name
Test status
Simulation time	9621218100 ps
CPU time	216.06 seconds
Started	Jul 06 05:53:41 PM PDT 24
Finished	Jul 06 05:57:18 PM PDT 24
Peak memory	291436 kb
Host	smart-61568798-b592-4de2-a561-52fa7688f50f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980793119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.3980793119
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3467266034
Short name	T1020
Test name
Test status
Simulation time	23804751600 ps
CPU time	141.34 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:56:05 PM PDT 24
Peak memory	293088 kb
Host	smart-cba089d1-c5b7-4aa8-9cd1-ecb1fb4f22e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467266034 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3467266034
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.1881774728
Short name	T12
Test name
Test status
Simulation time	38097300 ps
CPU time	132.22 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:55:57 PM PDT 24
Peak memory	260152 kb
Host	smart-b3d37c5d-be08-4082-8ee6-e6c987e8b1d6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881774728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.1881774728
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.2904325558
Short name	T465
Test name
Test status
Simulation time	20413800 ps
CPU time	13.74 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:54:01 PM PDT 24
Peak memory	265240 kb
Host	smart-962f14a0-b196-475a-a443-a7fd64f2426f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904325558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.flash_ctrl_prog_reset.2904325558
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.3379004671
Short name	T346
Test name
Test status
Simulation time	29138400 ps
CPU time	31.28 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:54:19 PM PDT 24
Peak memory	275652 kb
Host	smart-467db34c-467f-4995-b3a5-2015eab1a1cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379004671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl ash_ctrl_rw_evict.3379004671
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2065115108
Short name	T356
Test name
Test status
Simulation time	29577600 ps
CPU time	31.12 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:54:22 PM PDT 24
Peak memory	268440 kb
Host	smart-342de0af-3a29-4a0b-bf37-ead8db1583fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065115108 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2065115108
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.1090468939
Short name	T397
Test name
Test status
Simulation time	2035956700 ps
CPU time	69.85 seconds
Started	Jul 06 05:53:48 PM PDT 24
Finished	Jul 06 05:54:58 PM PDT 24
Peak memory	259640 kb
Host	smart-141b5744-9f6f-4b80-8638-a4966683b76f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090468939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1090468939
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.2394270470
Short name	T257
Test name
Test status
Simulation time	55548700 ps
CPU time	122.9 seconds
Started	Jul 06 05:53:44 PM PDT 24
Finished	Jul 06 05:55:47 PM PDT 24
Peak memory	276288 kb
Host	smart-1a0caed2-d1b8-4b26-b102-7de4f17b994c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394270470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2394270470
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.1243964987
Short name	T1012
Test name
Test status
Simulation time	56381900 ps
CPU time	13.96 seconds
Started	Jul 06 05:53:53 PM PDT 24
Finished	Jul 06 05:54:08 PM PDT 24
Peak memory	259208 kb
Host	smart-be612026-32a5-4f2f-a081-fb8e4c73e459
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243964987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 1243964987
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.1956839833
Short name	T670
Test name
Test status
Simulation time	48574700 ps
CPU time	13.46 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:54:05 PM PDT 24
Peak memory	274916 kb
Host	smart-145954ee-9667-4bc2-ba46-8eed45728060
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1956839833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1956839833
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.2103358509
Short name	T11
Test name
Test status
Simulation time	41879700 ps
CPU time	21.66 seconds
Started	Jul 06 05:53:53 PM PDT 24
Finished	Jul 06 05:54:15 PM PDT 24
Peak memory	273584 kb
Host	smart-595f96ad-2efb-41f0-a1c7-63557eac19f5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103358509 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.2103358509
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2959836417
Short name	T692
Test name
Test status
Simulation time	1662333400 ps
CPU time	78.83 seconds
Started	Jul 06 05:53:48 PM PDT 24
Finished	Jul 06 05:55:07 PM PDT 24
Peak memory	263280 kb
Host	smart-055ef8ce-4064-40b6-9c9e-bb65e82b3a0c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959836417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.2959836417
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.540085198
Short name	T582
Test name
Test status
Simulation time	30419453500 ps
CPU time	223.8 seconds
Started	Jul 06 05:53:48 PM PDT 24
Finished	Jul 06 05:57:32 PM PDT 24
Peak memory	284908 kb
Host	smart-cde69f56-1751-4cf2-8bb0-14949509e07e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540085198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flas h_ctrl_intr_rd.540085198
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.730254016
Short name	T1093
Test name
Test status
Simulation time	23097052200 ps
CPU time	156.12 seconds
Started	Jul 06 05:53:52 PM PDT 24
Finished	Jul 06 05:56:28 PM PDT 24
Peak memory	293168 kb
Host	smart-3d69d52f-af74-4b61-be17-1829e173872a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730254016 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.730254016
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.2571457769
Short name	T383
Test name
Test status
Simulation time	49619400 ps
CPU time	132.49 seconds
Started	Jul 06 05:53:48 PM PDT 24
Finished	Jul 06 05:56:00 PM PDT 24
Peak memory	261084 kb
Host	smart-cbe747c1-92d1-4f7a-b0ef-e2349bd16e15
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571457769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.2571457769
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.4027705838
Short name	T1028
Test name
Test status
Simulation time	23897200 ps
CPU time	13.33 seconds
Started	Jul 06 05:53:53 PM PDT 24
Finished	Jul 06 05:54:06 PM PDT 24
Peak memory	259156 kb
Host	smart-a4e405f4-ec14-4149-bf92-2902ab327fea
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027705838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.4027705838
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.1487380966
Short name	T513
Test name
Test status
Simulation time	32312400 ps
CPU time	31.43 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:54:23 PM PDT 24
Peak memory	268508 kb
Host	smart-ea727b36-8722-4660-8825-393b7697d6c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487380966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.1487380966
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3724174725
Short name	T890
Test name
Test status
Simulation time	32967000 ps
CPU time	31.58 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:54:23 PM PDT 24
Peak memory	268484 kb
Host	smart-1e203e1b-15c5-4d56-a12f-a0b35dabd6ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724174725 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3724174725
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.1100343078
Short name	T399
Test name
Test status
Simulation time	3210543100 ps
CPU time	75.34 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:55:06 PM PDT 24
Peak memory	263144 kb
Host	smart-85a3c5b1-bc17-465d-a88c-a7548d65e042
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100343078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1100343078
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.1194163315
Short name	T478
Test name
Test status
Simulation time	63946500 ps
CPU time	96.63 seconds
Started	Jul 06 05:53:47 PM PDT 24
Finished	Jul 06 05:55:23 PM PDT 24
Peak memory	275872 kb
Host	smart-d0b47328-5892-41c8-9c18-ec572093914d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194163315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1194163315
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.2038477944
Short name	T456
Test name
Test status
Simulation time	45790000 ps
CPU time	14.49 seconds
Started	Jul 06 05:54:00 PM PDT 24
Finished	Jul 06 05:54:15 PM PDT 24
Peak memory	265236 kb
Host	smart-eff7c21a-2b23-471f-b20d-7decd2169229
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038477944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 2038477944
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.557541486
Short name	T425
Test name
Test status
Simulation time	22126900 ps
CPU time	15.88 seconds
Started	Jul 06 05:54:01 PM PDT 24
Finished	Jul 06 05:54:17 PM PDT 24
Peak memory	275012 kb
Host	smart-428ecdd5-b62a-4101-af63-6ca980676da7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=557541486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.557541486
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.1000374250
Short name	T112
Test name
Test status
Simulation time	10405600 ps
CPU time	20.52 seconds
Started	Jul 06 05:54:04 PM PDT 24
Finished	Jul 06 05:54:24 PM PDT 24
Peak memory	265720 kb
Host	smart-ce85f8f9-8367-46de-b8cd-7876f48f5d70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000374250 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.1000374250
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.698001250
Short name	T1098
Test name
Test status
Simulation time	17563338500 ps
CPU time	166.83 seconds
Started	Jul 06 05:53:56 PM PDT 24
Finished	Jul 06 05:56:43 PM PDT 24
Peak memory	260800 kb
Host	smart-bc723a56-53e4-42bb-992d-4eed99cd49f6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698001250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h w_sec_otp.698001250
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2370498321
Short name	T39
Test name
Test status
Simulation time	1129995600 ps
CPU time	123.63 seconds
Started	Jul 06 05:53:55 PM PDT 24
Finished	Jul 06 05:55:59 PM PDT 24
Peak memory	294076 kb
Host	smart-367bf860-b953-4b15-bda7-3e227376846c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370498321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2370498321
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2386352589
Short name	T527
Test name
Test status
Simulation time	12766726400 ps
CPU time	297.18 seconds
Started	Jul 06 05:53:55 PM PDT 24
Finished	Jul 06 05:58:53 PM PDT 24
Peak memory	291608 kb
Host	smart-020d9c7a-d019-48cc-aa6c-3d37b7df725b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386352589 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.2386352589
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.506965068
Short name	T1099
Test name
Test status
Simulation time	241663500 ps
CPU time	133.07 seconds
Started	Jul 06 05:53:59 PM PDT 24
Finished	Jul 06 05:56:12 PM PDT 24
Peak memory	259944 kb
Host	smart-38c128c1-6120-4e0e-bfb5-491d4ad263b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506965068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot p_reset.506965068
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.3244520808
Short name	T414
Test name
Test status
Simulation time	57724400 ps
CPU time	13.74 seconds
Started	Jul 06 05:53:56 PM PDT 24
Finished	Jul 06 05:54:10 PM PDT 24
Peak memory	259080 kb
Host	smart-f3e2c4ff-7372-475c-a05f-70e47fca9549
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244520808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.3244520808
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.550183595
Short name	T27
Test name
Test status
Simulation time	27073900 ps
CPU time	31.49 seconds
Started	Jul 06 05:53:55 PM PDT 24
Finished	Jul 06 05:54:27 PM PDT 24
Peak memory	273656 kb
Host	smart-99e03069-d91a-46fb-af82-0ecaa98df405
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550183595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_rw_evict.550183595
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4053937322
Short name	T420
Test name
Test status
Simulation time	76383700 ps
CPU time	31.04 seconds
Started	Jul 06 05:54:01 PM PDT 24
Finished	Jul 06 05:54:33 PM PDT 24
Peak memory	275684 kb
Host	smart-7bec45b4-d072-499a-866d-75ea017aa63c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053937322 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.4053937322
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.2882516110
Short name	T615
Test name
Test status
Simulation time	116701900 ps
CPU time	99.91 seconds
Started	Jul 06 05:53:51 PM PDT 24
Finished	Jul 06 05:55:32 PM PDT 24
Peak memory	276204 kb
Host	smart-d98cc950-a70d-45ba-b4dc-4183efd837a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882516110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2882516110
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.172445490
Short name	T938
Test name
Test status
Simulation time	35754100 ps
CPU time	14.2 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:54:20 PM PDT 24
Peak memory	265196 kb
Host	smart-83c55878-aff6-44c8-80b1-c9580a46c3d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172445490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.172445490
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.117794424
Short name	T565
Test name
Test status
Simulation time	49237200 ps
CPU time	16.12 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:54:21 PM PDT 24
Peak memory	274904 kb
Host	smart-cdd1eb0b-656e-47e8-b3d2-0900763f747c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117794424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.117794424
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.1659507137
Short name	T370
Test name
Test status
Simulation time	12759500 ps
CPU time	21.85 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:54:28 PM PDT 24
Peak memory	273560 kb
Host	smart-2f9f619f-81eb-417f-8784-250df6e3a115
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659507137 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.1659507137
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2572755221
Short name	T1115
Test name
Test status
Simulation time	3082821200 ps
CPU time	79.76 seconds
Started	Jul 06 05:54:00 PM PDT 24
Finished	Jul 06 05:55:20 PM PDT 24
Peak memory	260816 kb
Host	smart-f3f4af48-8868-4b91-a743-ecbafad6f05c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572755221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.2572755221
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.409419649
Short name	T779
Test name
Test status
Simulation time	4045965500 ps
CPU time	228.38 seconds
Started	Jul 06 05:54:02 PM PDT 24
Finished	Jul 06 05:57:51 PM PDT 24
Peak memory	291460 kb
Host	smart-69fc7af5-23b8-432f-8c24-c566e6b69370
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409419649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas h_ctrl_intr_rd.409419649
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3478805832
Short name	T553
Test name
Test status
Simulation time	5591517200 ps
CPU time	135.37 seconds
Started	Jul 06 05:54:07 PM PDT 24
Finished	Jul 06 05:56:23 PM PDT 24
Peak memory	292704 kb
Host	smart-f10bbbe4-cf35-414c-8152-6f12e83dbe64
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478805832 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3478805832
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.1747596715
Short name	T572
Test name
Test status
Simulation time	160451100 ps
CPU time	111.4 seconds
Started	Jul 06 05:54:04 PM PDT 24
Finished	Jul 06 05:55:56 PM PDT 24
Peak memory	261084 kb
Host	smart-54d6ee47-80e2-439e-a10d-727800452d86
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747596715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.1747596715
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.118286851
Short name	T1062
Test name
Test status
Simulation time	37847900 ps
CPU time	13.46 seconds
Started	Jul 06 05:54:06 PM PDT 24
Finished	Jul 06 05:54:20 PM PDT 24
Peak memory	259188 kb
Host	smart-4adebcbe-6f52-49d1-a87d-9149174c6b84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118286851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 28.flash_ctrl_prog_reset.118286851
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.2444037414
Short name	T1100
Test name
Test status
Simulation time	29095200 ps
CPU time	30.53 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	275736 kb
Host	smart-97cdefab-942b-44c9-9c75-655d66d483bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444037414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.2444037414
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1803929475
Short name	T335
Test name
Test status
Simulation time	96024400 ps
CPU time	31.77 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:54:37 PM PDT 24
Peak memory	269352 kb
Host	smart-2382727c-6cc7-4b80-935e-39bfa4978ee6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803929475 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1803929475
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.3408935580
Short name	T557
Test name
Test status
Simulation time	7186957800 ps
CPU time	80.06 seconds
Started	Jul 06 05:54:16 PM PDT 24
Finished	Jul 06 05:55:36 PM PDT 24
Peak memory	265052 kb
Host	smart-c774fd56-62f8-41da-aa90-359a342145b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3408935580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3408935580
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.796067452
Short name	T546
Test name
Test status
Simulation time	61440600 ps
CPU time	144.88 seconds
Started	Jul 06 05:54:02 PM PDT 24
Finished	Jul 06 05:56:28 PM PDT 24
Peak memory	277056 kb
Host	smart-ea11bd6d-ed11-4fdd-a2d9-6d381bc8ffd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796067452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.796067452
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.4023518664
Short name	T720
Test name
Test status
Simulation time	58725100 ps
CPU time	13.69 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:54:25 PM PDT 24
Peak memory	258288 kb
Host	smart-e02d10ec-8260-4679-9b07-7b629bc263b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023518664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 4023518664
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.3788858088
Short name	T1027
Test name
Test status
Simulation time	69470900 ps
CPU time	13.28 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:54:25 PM PDT 24
Peak memory	274904 kb
Host	smart-424aed3b-fcd2-4fea-8e63-627fcc807b4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788858088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.3788858088
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.1403499692
Short name	T510
Test name
Test status
Simulation time	27215300 ps
CPU time	20.49 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:54:32 PM PDT 24
Peak memory	273648 kb
Host	smart-74e983fc-ca7a-4f32-bffd-e61c8703b2d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403499692 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.1403499692
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.439951606
Short name	T310
Test name
Test status
Simulation time	3505238200 ps
CPU time	129.27 seconds
Started	Jul 06 05:54:04 PM PDT 24
Finished	Jul 06 05:56:14 PM PDT 24
Peak memory	262808 kb
Host	smart-5b511f7f-02ff-4dae-8356-343943490faa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439951606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_h w_sec_otp.439951606
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.1720815687
Short name	T331
Test name
Test status
Simulation time	10356839900 ps
CPU time	137.24 seconds
Started	Jul 06 05:54:10 PM PDT 24
Finished	Jul 06 05:56:28 PM PDT 24
Peak memory	285384 kb
Host	smart-30e248b1-d5b8-4d5b-b8a2-c2ee9a9a8a98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720815687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.1720815687
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.510081590
Short name	T705
Test name
Test status
Simulation time	45494537400 ps
CPU time	352.45 seconds
Started	Jul 06 05:54:12 PM PDT 24
Finished	Jul 06 06:00:05 PM PDT 24
Peak memory	291048 kb
Host	smart-96389a9a-e97f-4911-ade4-f4aac4826980
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510081590 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.510081590
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.2989113008
Short name	T764
Test name
Test status
Simulation time	340286200 ps
CPU time	131.42 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:56:17 PM PDT 24
Peak memory	260092 kb
Host	smart-3f056e71-ca0d-490d-ba7e-ef8793a6cd74
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989113008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o tp_reset.2989113008
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.2626688680
Short name	T1084
Test name
Test status
Simulation time	38897500 ps
CPU time	13.66 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:54:25 PM PDT 24
Peak memory	259160 kb
Host	smart-45aaf995-a349-46df-a77f-47fcf1aa1593
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626688680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.flash_ctrl_prog_reset.2626688680
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.1633170257
Short name	T611
Test name
Test status
Simulation time	27242800 ps
CPU time	31.41 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:54:43 PM PDT 24
Peak memory	273668 kb
Host	smart-900611fc-4d66-4029-b4eb-447f405daf5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633170257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl ash_ctrl_rw_evict.1633170257
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.420894134
Short name	T432
Test name
Test status
Simulation time	122388400 ps
CPU time	31.31 seconds
Started	Jul 06 05:54:12 PM PDT 24
Finished	Jul 06 05:54:44 PM PDT 24
Peak memory	268544 kb
Host	smart-72078670-3135-4229-8d0a-0dc7c3f47d67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420894134 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.420894134
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.2067150196
Short name	T400
Test name
Test status
Simulation time	17304242200 ps
CPU time	100.5 seconds
Started	Jul 06 05:54:12 PM PDT 24
Finished	Jul 06 05:55:53 PM PDT 24
Peak memory	264824 kb
Host	smart-6041c41d-1119-4b67-8589-cbf78eb46f3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067150196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2067150196
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.860636786
Short name	T613
Test name
Test status
Simulation time	312027400 ps
CPU time	146.33 seconds
Started	Jul 06 05:54:05 PM PDT 24
Finished	Jul 06 05:56:32 PM PDT 24
Peak memory	276948 kb
Host	smart-ff9f20b5-5b0c-452b-a12f-5754b76cf7ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860636786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.860636786
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.3580034141
Short name	T426
Test name
Test status
Simulation time	40678300 ps
CPU time	13.92 seconds
Started	Jul 06 05:49:25 PM PDT 24
Finished	Jul 06 05:49:39 PM PDT 24
Peak memory	258156 kb
Host	smart-523ab8f2-9b6d-4514-a298-25969583e422
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580034141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3 580034141
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.2308455062
Short name	T259
Test name
Test status
Simulation time	180816400 ps
CPU time	14.48 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:49:33 PM PDT 24
Peak memory	261696 kb
Host	smart-6c3bcd6b-6a79-48cf-9231-9e73313ea516
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308455062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.2308455062
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.4293205356
Short name	T416
Test name
Test status
Simulation time	84123500 ps
CPU time	13.51 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	284252 kb
Host	smart-fd49e2f5-8224-4854-987d-83d3bd864286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4293205356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.4293205356
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.1625633350
Short name	T385
Test name
Test status
Simulation time	49748300 ps
CPU time	21.92 seconds
Started	Jul 06 05:49:22 PM PDT 24
Finished	Jul 06 05:49:44 PM PDT 24
Peak memory	265620 kb
Host	smart-febe439d-6f83-4ae8-815d-7e9410ff5b74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625633350 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.1625633350
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.1440124760
Short name	T684
Test name
Test status
Simulation time	1480810900 ps
CPU time	305.53 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:54:20 PM PDT 24
Peak memory	263560 kb
Host	smart-a683b125-4593-4b52-a1cf-efacc5970c6d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1440124760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1440124760
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.2748603476
Short name	T477
Test name
Test status
Simulation time	7899009400 ps
CPU time	2167.08 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 06:25:23 PM PDT 24
Peak memory	265216 kb
Host	smart-ff2a059b-6796-4925-a818-bb8fad8b1e40
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2748603476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.2748603476
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.4248458073
Short name	T93
Test name
Test status
Simulation time	3107792600 ps
CPU time	2057.75 seconds
Started	Jul 06 05:49:17 PM PDT 24
Finished	Jul 06 06:23:35 PM PDT 24
Peak memory	265156 kb
Host	smart-127d73f3-03ef-4b17-b411-cf6aa87e4f22
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248458073 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.4248458073
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.1369582897
Short name	T708
Test name
Test status
Simulation time	1005927900 ps
CPU time	815 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 06:02:49 PM PDT 24
Peak memory	273364 kb
Host	smart-dc7b0ca3-73fb-4b97-a6f4-5b35db96ccb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369582897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1369582897
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.1959571545
Short name	T51
Test name
Test status
Simulation time	376218400 ps
CPU time	28.06 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:49:44 PM PDT 24
Peak memory	262428 kb
Host	smart-01d69706-1580-4043-8f27-e5144492bd72
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959571545 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1959571545
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.2276793643
Short name	T946
Test name
Test status
Simulation time	603437100 ps
CPU time	36.55 seconds
Started	Jul 06 05:49:22 PM PDT 24
Finished	Jul 06 05:49:59 PM PDT 24
Peak memory	263040 kb
Host	smart-3eb7ca0c-064f-4fde-90e9-bd6828c08a31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276793643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 3.flash_ctrl_fs_sup.2276793643
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.3023319235
Short name	T1103
Test name
Test status
Simulation time	306186734400 ps
CPU time	4137.66 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 06:58:15 PM PDT 24
Peak memory	265140 kb
Host	smart-fde00aba-757f-4a68-a920-d2e3332ffdfe
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023319235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.3023319235
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.3172605964
Short name	T279
Test name
Test status
Simulation time	39038600 ps
CPU time	24.88 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:49:41 PM PDT 24
Peak memory	265252 kb
Host	smart-287b4310-077b-4f8a-a387-0de862790bea
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3172605964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3172605964
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.980565599
Short name	T966
Test name
Test status
Simulation time	10159655900 ps
CPU time	34.76 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:49:54 PM PDT 24
Peak memory	265420 kb
Host	smart-a55f5997-9d20-40de-9743-ae2c985ccd20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980565599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.980565599
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2795373384
Short name	T178
Test name
Test status
Simulation time	15892700 ps
CPU time	13.49 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	264948 kb
Host	smart-2f4c2786-4cbb-4eec-a4cc-1d5cc46371e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795373384 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2795373384
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.909689126
Short name	T119
Test name
Test status
Simulation time	40121455200 ps
CPU time	803.2 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 06:02:38 PM PDT 24
Peak memory	261068 kb
Host	smart-88761066-9c85-48fc-b294-e7ca9e1727b6
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909689126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_hw_rma_reset.909689126
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1561776606
Short name	T782
Test name
Test status
Simulation time	65058075500 ps
CPU time	288.06 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	260936 kb
Host	smart-2c1aca7b-1b49-4509-9587-c160e2438637
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561776606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.1561776606
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_integrity.2385130818
Short name	T827
Test name
Test status
Simulation time	27894310700 ps
CPU time	717.27 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 06:01:17 PM PDT 24
Peak memory	338288 kb
Host	smart-e9d030ec-8566-4a87-a568-70fa1ad6892c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385130818 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_integrity.2385130818
Directory	/workspace/3.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.3915621043
Short name	T323
Test name
Test status
Simulation time	744955300 ps
CPU time	167.03 seconds
Started	Jul 06 05:49:22 PM PDT 24
Finished	Jul 06 05:52:10 PM PDT 24
Peak memory	284940 kb
Host	smart-5e2bd1ec-45f6-493e-8611-a37ff5da847e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915621043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.3915621043
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3679087943
Short name	T1123
Test name
Test status
Simulation time	5869729800 ps
CPU time	167.32 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:52:07 PM PDT 24
Peak memory	284984 kb
Host	smart-2bf05667-fc79-4512-8d2b-73c86d71bf76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679087943 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3679087943
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.1149951857
Short name	T1111
Test name
Test status
Simulation time	2625693500 ps
CPU time	73.01 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:50:32 PM PDT 24
Peak memory	265332 kb
Host	smart-103ab00e-e82d-4144-b3ad-93b5da1b7a04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149951857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.1149951857
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1803324865
Short name	T552
Test name
Test status
Simulation time	95069271400 ps
CPU time	189.54 seconds
Started	Jul 06 05:49:23 PM PDT 24
Finished	Jul 06 05:52:32 PM PDT 24
Peak memory	259880 kb
Host	smart-de201bb2-08a4-4655-beb7-7453dff61850
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180 3324865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1803324865
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.950300170
Short name	T696
Test name
Test status
Simulation time	2098069100 ps
CPU time	64.99 seconds
Started	Jul 06 05:49:17 PM PDT 24
Finished	Jul 06 05:50:22 PM PDT 24
Peak memory	262616 kb
Host	smart-bf5345d7-bf62-4a89-95cb-9b257b254458
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950300170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.950300170
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3523477702
Short name	T767
Test name
Test status
Simulation time	26447500 ps
CPU time	13.54 seconds
Started	Jul 06 05:49:21 PM PDT 24
Finished	Jul 06 05:49:35 PM PDT 24
Peak memory	260876 kb
Host	smart-d25f0cf1-d21c-4347-a328-1ed581baba8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523477702 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3523477702
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.2307764060
Short name	T979
Test name
Test status
Simulation time	12030074800 ps
CPU time	741.77 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 06:01:37 PM PDT 24
Peak memory	274956 kb
Host	smart-533729e9-45df-40f2-b9d6-6410685a3b7a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307764060 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2307764060
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.3008362180
Short name	T640
Test name
Test status
Simulation time	66458200 ps
CPU time	110.81 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:51:07 PM PDT 24
Peak memory	261048 kb
Host	smart-ed33ddeb-a06e-4991-8830-262403dcfda4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008362180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.3008362180
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.1244607872
Short name	T931
Test name
Test status
Simulation time	875830700 ps
CPU time	147.55 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:51:47 PM PDT 24
Peak memory	281716 kb
Host	smart-a5337f97-6ca9-4ff9-852a-294491927917
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244607872 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1244607872
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.1075428677
Short name	T533
Test name
Test status
Simulation time	2958591000 ps
CPU time	568.57 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:58:44 PM PDT 24
Peak memory	263092 kb
Host	smart-eb1d825c-ab6c-40ed-bb72-f50faa045bb6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1075428677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1075428677
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3560183737
Short name	T77
Test name
Test status
Simulation time	845975400 ps
CPU time	15.95 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:49:36 PM PDT 24
Peak memory	265100 kb
Host	smart-6a9cd1f6-cd99-42d4-a098-07199975f0fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560183737 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3560183737
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.1861981008
Short name	T998
Test name
Test status
Simulation time	21595900 ps
CPU time	13.87 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:49:34 PM PDT 24
Peak memory	265240 kb
Host	smart-dc8a81a1-9916-4059-9ede-301f6757a64d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861981008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_prog_reset.1861981008
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.1551158489
Short name	T733
Test name
Test status
Simulation time	567911700 ps
CPU time	393.21 seconds
Started	Jul 06 05:49:17 PM PDT 24
Finished	Jul 06 05:55:50 PM PDT 24
Peak memory	282800 kb
Host	smart-98d73540-8ec4-42d6-9614-91ff34a3809e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551158489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1551158489
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1740234029
Short name	T281
Test name
Test status
Simulation time	1450874900 ps
CPU time	117.28 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:51:12 PM PDT 24
Peak memory	262764 kb
Host	smart-00778b6d-8a95-4f6d-995a-58e8d50d747b
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1740234029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1740234029
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.1744420300
Short name	T1096
Test name
Test status
Simulation time	42204600 ps
CPU time	22.86 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:49:42 PM PDT 24
Peak memory	265452 kb
Host	smart-e20df4d0-b900-4ba2-8b7e-3e3c37a5adb0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744420300 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.1744420300
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.987124608
Short name	T751
Test name
Test status
Simulation time	76806400 ps
CPU time	21.59 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:49:38 PM PDT 24
Peak memory	265076 kb
Host	smart-68289c1e-0340-48f5-865e-7d55ff766af4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987124608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_read_word_sweep_serr.987124608
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.2721327068
Short name	T679
Test name
Test status
Simulation time	2091225400 ps
CPU time	119 seconds
Started	Jul 06 05:49:19 PM PDT 24
Finished	Jul 06 05:51:18 PM PDT 24
Peak memory	281588 kb
Host	smart-b55c279a-3b75-444e-8044-70a7ea9214e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721327068 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.2721327068
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.1112266506
Short name	T655
Test name
Test status
Simulation time	671128600 ps
CPU time	158.55 seconds
Started	Jul 06 05:49:23 PM PDT 24
Finished	Jul 06 05:52:02 PM PDT 24
Peak memory	281844 kb
Host	smart-768d79a4-5957-46e1-bac1-d9ae960bc635
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1112266506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1112266506
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.1189856465
Short name	T763
Test name
Test status
Simulation time	2529638100 ps
CPU time	126.3 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:51:25 PM PDT 24
Peak memory	290436 kb
Host	smart-af6a002e-8f1f-4b45-b2ab-0ad5d5efbae6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189856465 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1189856465
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.284910913
Short name	T753
Test name
Test status
Simulation time	7572911400 ps
CPU time	572.14 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:58:48 PM PDT 24
Peak memory	309544 kb
Host	smart-c051273d-8334-4621-bebe-417af86ead0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284910913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.284910913
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.568254136
Short name	T164
Test name
Test status
Simulation time	3641387600 ps
CPU time	551.45 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:58:30 PM PDT 24
Peak memory	331504 kb
Host	smart-c1b4a6ef-50e2-4c97-82ce-10bbcf17959f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568254136 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.flash_ctrl_rw_derr.568254136
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.645835001
Short name	T663
Test name
Test status
Simulation time	119594700 ps
CPU time	30.95 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:49:51 PM PDT 24
Peak memory	275712 kb
Host	smart-629cec37-0044-4c27-a770-0c30e503c368
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645835001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_rw_evict.645835001
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2241440233
Short name	T945
Test name
Test status
Simulation time	42600100 ps
CPU time	30.82 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:49:51 PM PDT 24
Peak memory	275728 kb
Host	smart-6119e1d0-6e6f-468d-8be2-4667da59a03a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241440233 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2241440233
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.11252840
Short name	T897
Test name
Test status
Simulation time	2535923600 ps
CPU time	481.69 seconds
Started	Jul 06 05:49:21 PM PDT 24
Finished	Jul 06 05:57:23 PM PDT 24
Peak memory	321044 kb
Host	smart-d0144d80-2001-471a-8010-e2fa74c0b882
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash _ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_ser r.11252840
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.580075571
Short name	T391
Test name
Test status
Simulation time	10196019000 ps
CPU time	79.81 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:50:38 PM PDT 24
Peak memory	263624 kb
Host	smart-10ddf55e-c0bc-4089-a16b-5b0463dd1237
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580075571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.580075571
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.3145713920
Short name	T1003
Test name
Test status
Simulation time	1121367100 ps
CPU time	59.86 seconds
Started	Jul 06 05:49:20 PM PDT 24
Finished	Jul 06 05:50:20 PM PDT 24
Peak memory	273548 kb
Host	smart-9cf03d12-26d7-4b54-9292-ff4a3d8818fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145713920 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.3145713920
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.2087580337
Short name	T1120
Test name
Test status
Simulation time	1088436400 ps
CPU time	61 seconds
Started	Jul 06 05:49:18 PM PDT 24
Finished	Jul 06 05:50:20 PM PDT 24
Peak memory	265600 kb
Host	smart-cfafad51-dec6-4c96-8c21-08fedd2f6f37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087580337 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_serr_counter.2087580337
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.2945063283
Short name	T482
Test name
Test status
Simulation time	141911600 ps
CPU time	149.64 seconds
Started	Jul 06 05:49:16 PM PDT 24
Finished	Jul 06 05:51:46 PM PDT 24
Peak memory	276964 kb
Host	smart-4e06822b-c285-4a26-9c5e-99bf184173ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945063283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2945063283
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.1389852469
Short name	T710
Test name
Test status
Simulation time	16837200 ps
CPU time	26.44 seconds
Started	Jul 06 05:49:14 PM PDT 24
Finished	Jul 06 05:49:41 PM PDT 24
Peak memory	259756 kb
Host	smart-20332d42-41a1-4979-a9d6-b5d96ae99495
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389852469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1389852469
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.2552446129
Short name	T233
Test name
Test status
Simulation time	1893428600 ps
CPU time	1452.07 seconds
Started	Jul 06 05:49:22 PM PDT 24
Finished	Jul 06 06:13:34 PM PDT 24
Peak memory	289236 kb
Host	smart-bc3cb1c8-c53a-4043-9ccc-42f095037cf0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552446129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.2552446129
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.3562053054
Short name	T759
Test name
Test status
Simulation time	79502400 ps
CPU time	26.76 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:49:42 PM PDT 24
Peak memory	259548 kb
Host	smart-b6f502ac-c984-4bed-bb74-ec727af1ece2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3562053054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3562053054
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.1969608139
Short name	T446
Test name
Test status
Simulation time	5827161100 ps
CPU time	257.13 seconds
Started	Jul 06 05:49:15 PM PDT 24
Finished	Jul 06 05:53:33 PM PDT 24
Peak memory	261204 kb
Host	smart-afc612a3-570b-49a5-8f5f-b31226486a48
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969608139 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.1969608139
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.428402193
Short name	T454
Test name
Test status
Simulation time	81667300 ps
CPU time	14.11 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:54:35 PM PDT 24
Peak memory	258244 kb
Host	smart-78fe57b5-a2d8-4537-bd26-29be80d512ab
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428402193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.428402193
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.3443950945
Short name	T905
Test name
Test status
Simulation time	40788900 ps
CPU time	16.03 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	274964 kb
Host	smart-7fcc95e7-85a5-4b3b-a793-21d090ef921c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443950945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3443950945
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.1004477411
Short name	T82
Test name
Test status
Simulation time	10330500 ps
CPU time	21.26 seconds
Started	Jul 06 05:54:14 PM PDT 24
Finished	Jul 06 05:54:36 PM PDT 24
Peak memory	274876 kb
Host	smart-6f3c06b0-4383-4432-be93-48800cfb799a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004477411 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.1004477411
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.365087468
Short name	T816
Test name
Test status
Simulation time	1145126800 ps
CPU time	57.63 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:55:09 PM PDT 24
Peak memory	262712 kb
Host	smart-de4c85d0-3834-4225-81c9-cbcf85565fa5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365087468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.365087468
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.3977112363
Short name	T326
Test name
Test status
Simulation time	20984668300 ps
CPU time	220.73 seconds
Started	Jul 06 05:54:14 PM PDT 24
Finished	Jul 06 05:57:55 PM PDT 24
Peak memory	291428 kb
Host	smart-a123f69e-fa35-450f-96a0-1fa832fb68ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977112363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla sh_ctrl_intr_rd.3977112363
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.4238428153
Short name	T603
Test name
Test status
Simulation time	64518000 ps
CPU time	111.27 seconds
Started	Jul 06 05:54:14 PM PDT 24
Finished	Jul 06 05:56:06 PM PDT 24
Peak memory	260152 kb
Host	smart-ec94b27b-1f24-40c1-a5e1-b438eda94758
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238428153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o tp_reset.4238428153
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.704204289
Short name	T877
Test name
Test status
Simulation time	38888500 ps
CPU time	31.57 seconds
Started	Jul 06 05:54:15 PM PDT 24
Finished	Jul 06 05:54:47 PM PDT 24
Peak memory	275692 kb
Host	smart-932d41b8-9f3e-46c9-a2c9-020099f40f04
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704204289 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.704204289
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.4188318513
Short name	T398
Test name
Test status
Simulation time	11765070100 ps
CPU time	66.13 seconds
Started	Jul 06 05:54:15 PM PDT 24
Finished	Jul 06 05:55:21 PM PDT 24
Peak memory	264148 kb
Host	smart-9779694b-5cc8-44ba-9c37-c9b7afd6e429
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188318513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.4188318513
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.888404726
Short name	T130
Test name
Test status
Simulation time	65539500 ps
CPU time	75.63 seconds
Started	Jul 06 05:54:11 PM PDT 24
Finished	Jul 06 05:55:27 PM PDT 24
Peak memory	276800 kb
Host	smart-abc332ad-c8ce-4647-9884-c5b95bc35955
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888404726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.888404726
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.1918138282
Short name	T444
Test name
Test status
Simulation time	57959100 ps
CPU time	14.09 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:54:39 PM PDT 24
Peak memory	258352 kb
Host	smart-ebba5841-6c73-4249-9b58-0fb245d374aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918138282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 1918138282
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.3082015100
Short name	T1057
Test name
Test status
Simulation time	24373100 ps
CPU time	13.34 seconds
Started	Jul 06 05:54:26 PM PDT 24
Finished	Jul 06 05:54:40 PM PDT 24
Peak memory	274912 kb
Host	smart-183b02ef-0ba8-4fee-aaf3-6a8f2c88a46b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082015100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3082015100
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.2040641901
Short name	T176
Test name
Test status
Simulation time	21145000 ps
CPU time	22.1 seconds
Started	Jul 06 05:54:19 PM PDT 24
Finished	Jul 06 05:54:41 PM PDT 24
Peak memory	273616 kb
Host	smart-a12266bb-7427-49eb-a36a-2e7d6da746d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040641901 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.2040641901
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.2919141553
Short name	T698
Test name
Test status
Simulation time	979640100 ps
CPU time	121.19 seconds
Started	Jul 06 05:54:19 PM PDT 24
Finished	Jul 06 05:56:20 PM PDT 24
Peak memory	294276 kb
Host	smart-ec94c8e5-042f-4bc1-b23d-0a82513581f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919141553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.2919141553
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.90150133
Short name	T1011
Test name
Test status
Simulation time	6350152300 ps
CPU time	126.75 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:56:27 PM PDT 24
Peak memory	293136 kb
Host	smart-753b3001-29bc-459c-9c7d-a14c57dcfc2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90150133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.90150133
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.2441936941
Short name	T662
Test name
Test status
Simulation time	43629700 ps
CPU time	112.76 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:56:13 PM PDT 24
Peak memory	261196 kb
Host	smart-6c5d4e1e-9d72-4ca8-9392-1a734f114cfa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441936941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.2441936941
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.960737627
Short name	T742
Test name
Test status
Simulation time	44550300 ps
CPU time	31.13 seconds
Started	Jul 06 05:54:21 PM PDT 24
Finished	Jul 06 05:54:53 PM PDT 24
Peak memory	275692 kb
Host	smart-8e2eb043-2fc1-4f84-8b67-7efd08959d58
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960737627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_rw_evict.960737627
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3456534599
Short name	T569
Test name
Test status
Simulation time	45105500 ps
CPU time	30.92 seconds
Started	Jul 06 05:54:20 PM PDT 24
Finished	Jul 06 05:54:52 PM PDT 24
Peak memory	275644 kb
Host	smart-5190fd39-c675-47ca-b11c-804fc067c518
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456534599 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3456534599
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.3354953183
Short name	T910
Test name
Test status
Simulation time	3761846200 ps
CPU time	81.82 seconds
Started	Jul 06 05:54:23 PM PDT 24
Finished	Jul 06 05:55:45 PM PDT 24
Peak memory	265080 kb
Host	smart-2cf6ee12-5c3d-4403-a7a3-3901ba3a5613
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354953183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3354953183
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.1156284521
Short name	T592
Test name
Test status
Simulation time	36959500 ps
CPU time	147.19 seconds
Started	Jul 06 05:54:19 PM PDT 24
Finished	Jul 06 05:56:47 PM PDT 24
Peak memory	278232 kb
Host	smart-45ed8e8a-601c-465a-9e77-1565af5958fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156284521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1156284521
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.2728878878
Short name	T828
Test name
Test status
Simulation time	43994900 ps
CPU time	13.65 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:54:38 PM PDT 24
Peak memory	258384 kb
Host	smart-52219847-05da-4752-ad82-b6465706eacc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728878878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 2728878878
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.4011493037
Short name	T125
Test name
Test status
Simulation time	22446000 ps
CPU time	15.74 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:54:40 PM PDT 24
Peak memory	274768 kb
Host	smart-dc8aebd8-ed47-4604-ab0c-d74d78e38fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011493037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.4011493037
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.2765795431
Short name	T386
Test name
Test status
Simulation time	11099700 ps
CPU time	22.3 seconds
Started	Jul 06 05:54:23 PM PDT 24
Finished	Jul 06 05:54:46 PM PDT 24
Peak memory	265528 kb
Host	smart-bd626940-50e0-44c3-9f08-b437dec90967
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765795431 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.2765795431
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1267676206
Short name	T799
Test name
Test status
Simulation time	3862684500 ps
CPU time	116.9 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:56:22 PM PDT 24
Peak memory	263208 kb
Host	smart-845d040c-ac96-4a3e-8b65-74a5b07f1af1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267676206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.1267676206
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.3181752810
Short name	T324
Test name
Test status
Simulation time	2888441100 ps
CPU time	151.5 seconds
Started	Jul 06 05:54:25 PM PDT 24
Finished	Jul 06 05:56:57 PM PDT 24
Peak memory	285360 kb
Host	smart-681bd707-caee-4717-af5e-59531b51cc40
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181752810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.3181752810
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3836945782
Short name	T491
Test name
Test status
Simulation time	40943099400 ps
CPU time	164.22 seconds
Started	Jul 06 05:54:23 PM PDT 24
Finished	Jul 06 05:57:08 PM PDT 24
Peak memory	293120 kb
Host	smart-bf2e6d36-c89b-46aa-9728-acc7ebfcfaee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836945782 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.3836945782
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.4262808629
Short name	T939
Test name
Test status
Simulation time	40060500 ps
CPU time	111.73 seconds
Started	Jul 06 05:54:25 PM PDT 24
Finished	Jul 06 05:56:17 PM PDT 24
Peak memory	261016 kb
Host	smart-bd66b9e3-22d7-45c0-b32d-f6689088e3ee
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262808629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o tp_reset.4262808629
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1709249291
Short name	T40
Test name
Test status
Simulation time	65537400 ps
CPU time	30.96 seconds
Started	Jul 06 05:54:25 PM PDT 24
Finished	Jul 06 05:54:56 PM PDT 24
Peak memory	275648 kb
Host	smart-a1715777-8166-4faa-88b8-a63483306aac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709249291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1709249291
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1963396098
Short name	T787
Test name
Test status
Simulation time	34555700 ps
CPU time	31.05 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:54:55 PM PDT 24
Peak memory	268516 kb
Host	smart-1a59f318-7794-4e79-80f0-9df79879cb4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963396098 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1963396098
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.4175111086
Short name	T858
Test name
Test status
Simulation time	1209843800 ps
CPU time	62.3 seconds
Started	Jul 06 05:54:23 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	264252 kb
Host	smart-fa7226dc-1355-46f8-83c1-5f918e1faa11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175111086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.4175111086
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.653626317
Short name	T584
Test name
Test status
Simulation time	155871500 ps
CPU time	153.05 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:56:58 PM PDT 24
Peak memory	277332 kb
Host	smart-7e538661-2a77-4d80-8d95-c7c4a1b79618
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=653626317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.653626317
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.3272475428
Short name	T20
Test name
Test status
Simulation time	97129800 ps
CPU time	13.55 seconds
Started	Jul 06 05:54:31 PM PDT 24
Finished	Jul 06 05:54:45 PM PDT 24
Peak memory	265184 kb
Host	smart-68d3c313-169c-4150-b52f-cfef10e886db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272475428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 3272475428
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.2638455726
Short name	T974
Test name
Test status
Simulation time	16104600 ps
CPU time	15.94 seconds
Started	Jul 06 05:54:31 PM PDT 24
Finished	Jul 06 05:54:47 PM PDT 24
Peak memory	284440 kb
Host	smart-296c16b9-8dd9-4412-bb82-b3615d866314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638455726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2638455726
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.2194010797
Short name	T83
Test name
Test status
Simulation time	40819600 ps
CPU time	20.11 seconds
Started	Jul 06 05:54:33 PM PDT 24
Finished	Jul 06 05:54:53 PM PDT 24
Peak memory	273628 kb
Host	smart-43336712-82a7-4f34-92cf-643e53dd7210
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194010797 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.2194010797
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.6768087
Short name	T1083
Test name
Test status
Simulation time	6786080100 ps
CPU time	60.21 seconds
Started	Jul 06 05:54:24 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	263240 kb
Host	smart-1d348d2d-6f4e-4088-8b50-dfcca4f7cd91
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6768087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_ sec_otp.6768087
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.3810439916
Short name	T927
Test name
Test status
Simulation time	6671753100 ps
CPU time	183.66 seconds
Started	Jul 06 05:54:28 PM PDT 24
Finished	Jul 06 05:57:32 PM PDT 24
Peak memory	291448 kb
Host	smart-c05d4573-c29a-4a3c-a724-a4c05bda6942
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810439916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.3810439916
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.236078503
Short name	T1002
Test name
Test status
Simulation time	33994024700 ps
CPU time	250.71 seconds
Started	Jul 06 05:54:28 PM PDT 24
Finished	Jul 06 05:58:39 PM PDT 24
Peak memory	291856 kb
Host	smart-d54e2827-8dc7-47e8-a6ae-12bb11c65dd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236078503 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.236078503
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.642996272
Short name	T195
Test name
Test status
Simulation time	73891800 ps
CPU time	132.09 seconds
Started	Jul 06 05:54:29 PM PDT 24
Finished	Jul 06 05:56:41 PM PDT 24
Peak memory	260148 kb
Host	smart-5c5258fd-64e2-47ac-8b7f-361bcad9846f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642996272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot p_reset.642996272
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.1050345105
Short name	T700
Test name
Test status
Simulation time	30618500 ps
CPU time	31.08 seconds
Started	Jul 06 05:54:28 PM PDT 24
Finished	Jul 06 05:54:59 PM PDT 24
Peak memory	275636 kb
Host	smart-7eecc0a9-5032-4403-9337-0ba3a72bfda0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050345105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.1050345105
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.419423101
Short name	T348
Test name
Test status
Simulation time	69554600 ps
CPU time	28.51 seconds
Started	Jul 06 05:54:34 PM PDT 24
Finished	Jul 06 05:55:03 PM PDT 24
Peak memory	267516 kb
Host	smart-5c4cf8b8-d64a-42a2-9481-2f3cab5e9070
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419423101 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.419423101
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.2911773649
Short name	T407
Test name
Test status
Simulation time	529738300 ps
CPU time	64.86 seconds
Started	Jul 06 05:54:31 PM PDT 24
Finished	Jul 06 05:55:36 PM PDT 24
Peak memory	263696 kb
Host	smart-cda83944-9a15-4f08-8c32-aa405cf5a74e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911773649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2911773649
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.111950269
Short name	T855
Test name
Test status
Simulation time	198027500 ps
CPU time	100.01 seconds
Started	Jul 06 05:54:25 PM PDT 24
Finished	Jul 06 05:56:05 PM PDT 24
Peak memory	277280 kb
Host	smart-50211a19-ee9f-4172-858d-4682f43624b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111950269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.111950269
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.2892886046
Short name	T766
Test name
Test status
Simulation time	57765000 ps
CPU time	13.89 seconds
Started	Jul 06 05:54:37 PM PDT 24
Finished	Jul 06 05:54:51 PM PDT 24
Peak memory	265236 kb
Host	smart-cb97c368-42ea-4b5b-a85a-b65d8a79f23f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892886046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 2892886046
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.3760491780
Short name	T461
Test name
Test status
Simulation time	50997500 ps
CPU time	15.87 seconds
Started	Jul 06 05:54:38 PM PDT 24
Finished	Jul 06 05:54:54 PM PDT 24
Peak memory	275096 kb
Host	smart-271397a0-c7b6-4e47-8635-e0801f7e284e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3760491780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3760491780
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.4206173524
Short name	T994
Test name
Test status
Simulation time	39733300 ps
CPU time	21.8 seconds
Started	Jul 06 05:54:40 PM PDT 24
Finished	Jul 06 05:55:02 PM PDT 24
Peak memory	273616 kb
Host	smart-f3464aeb-696a-4197-a8b4-237a59fd404d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206173524 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.4206173524
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2233994483
Short name	T105
Test name
Test status
Simulation time	2085660300 ps
CPU time	88.66 seconds
Started	Jul 06 05:54:32 PM PDT 24
Finished	Jul 06 05:56:01 PM PDT 24
Peak memory	262080 kb
Host	smart-4fc87881-75e2-40dc-b9ec-46b31b763ef6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233994483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ hw_sec_otp.2233994483
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.1213243504
Short name	T1116
Test name
Test status
Simulation time	3089030600 ps
CPU time	225.49 seconds
Started	Jul 06 05:54:34 PM PDT 24
Finished	Jul 06 05:58:20 PM PDT 24
Peak memory	291468 kb
Host	smart-32a3a5f8-0c14-44f1-95f5-2e3a6cc04ea5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213243504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.1213243504
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1387908971
Short name	T1006
Test name
Test status
Simulation time	11874817900 ps
CPU time	255.76 seconds
Started	Jul 06 05:54:32 PM PDT 24
Finished	Jul 06 05:58:48 PM PDT 24
Peak memory	291920 kb
Host	smart-908bbdc1-217b-4b50-ba11-2ccbbe9998ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387908971 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1387908971
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.1683866962
Short name	T815
Test name
Test status
Simulation time	371574200 ps
CPU time	131.8 seconds
Started	Jul 06 05:54:32 PM PDT 24
Finished	Jul 06 05:56:44 PM PDT 24
Peak memory	260312 kb
Host	smart-87932ec9-eb87-4e32-ad01-9e201e0eb328
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683866962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.1683866962
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3865658882
Short name	T608
Test name
Test status
Simulation time	124858100 ps
CPU time	30.62 seconds
Started	Jul 06 05:54:37 PM PDT 24
Finished	Jul 06 05:55:09 PM PDT 24
Peak memory	268512 kb
Host	smart-a647d91a-f6d1-4ed0-b309-fb32c8c60ac1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865658882 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.3865658882
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.3628861436
Short name	T818
Test name
Test status
Simulation time	5735064400 ps
CPU time	77.93 seconds
Started	Jul 06 05:54:39 PM PDT 24
Finished	Jul 06 05:55:57 PM PDT 24
Peak memory	264700 kb
Host	smart-0ae3550b-bb81-4386-b039-f9895d06393e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628861436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3628861436
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.3936550140
Short name	T704
Test name
Test status
Simulation time	37365800 ps
CPU time	175.33 seconds
Started	Jul 06 05:54:32 PM PDT 24
Finished	Jul 06 05:57:28 PM PDT 24
Peak memory	278700 kb
Host	smart-a333c116-c036-44ec-aa3e-4fc5337f4d5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936550140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3936550140
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.1125004590
Short name	T772
Test name
Test status
Simulation time	188934100 ps
CPU time	13.71 seconds
Started	Jul 06 05:54:39 PM PDT 24
Finished	Jul 06 05:54:53 PM PDT 24
Peak memory	265280 kb
Host	smart-a12adc15-fbbd-42d7-9512-2caa04af1563
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125004590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 1125004590
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.125260753
Short name	T703
Test name
Test status
Simulation time	98262600 ps
CPU time	16.25 seconds
Started	Jul 06 05:54:38 PM PDT 24
Finished	Jul 06 05:54:54 PM PDT 24
Peak memory	284248 kb
Host	smart-e33740a4-3cda-4bab-9830-77d5048c874e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125260753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.125260753
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.2383505858
Short name	T1080
Test name
Test status
Simulation time	13910000 ps
CPU time	22.07 seconds
Started	Jul 06 05:54:40 PM PDT 24
Finished	Jul 06 05:55:02 PM PDT 24
Peak memory	265564 kb
Host	smart-ba574886-4f54-49d4-b1dd-4a9c9c04832b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383505858 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.2383505858
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3612275339
Short name	T132
Test name
Test status
Simulation time	3500840900 ps
CPU time	129.33 seconds
Started	Jul 06 05:54:41 PM PDT 24
Finished	Jul 06 05:56:51 PM PDT 24
Peak memory	260972 kb
Host	smart-8f45cd7b-3809-449b-bd5a-d536f098e2a7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612275339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3612275339
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.3940734706
Short name	T745
Test name
Test status
Simulation time	638775100 ps
CPU time	138.91 seconds
Started	Jul 06 05:54:37 PM PDT 24
Finished	Jul 06 05:56:57 PM PDT 24
Peak memory	291612 kb
Host	smart-bb2737d0-f1e9-4ffd-b427-0176979800a8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940734706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.3940734706
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1977902581
Short name	T327
Test name
Test status
Simulation time	82052615100 ps
CPU time	209.62 seconds
Started	Jul 06 05:54:40 PM PDT 24
Finished	Jul 06 05:58:10 PM PDT 24
Peak memory	293308 kb
Host	smart-d5c86354-4f33-474a-9444-d06f0eb2ca3e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977902581 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1977902581
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.1864637270
Short name	T775
Test name
Test status
Simulation time	151792300 ps
CPU time	130.79 seconds
Started	Jul 06 05:54:36 PM PDT 24
Finished	Jul 06 05:56:48 PM PDT 24
Peak memory	260100 kb
Host	smart-5c46110b-7f85-4a7a-afa0-ec7f05df6ba8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864637270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.1864637270
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.3621631074
Short name	T1013
Test name
Test status
Simulation time	40463600 ps
CPU time	28.22 seconds
Started	Jul 06 05:54:37 PM PDT 24
Finished	Jul 06 05:55:05 PM PDT 24
Peak memory	275648 kb
Host	smart-a2d18f0d-e369-425e-80b2-b52f7eae5514
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621631074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.3621631074
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.5379720
Short name	T969
Test name
Test status
Simulation time	82174700 ps
CPU time	28.65 seconds
Started	Jul 06 05:54:36 PM PDT 24
Finished	Jul 06 05:55:05 PM PDT 24
Peak memory	268524 kb
Host	smart-6c3f7eee-97bc-4c01-af7d-d8e32be87f42
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5379720 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.5379720
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.2748974643
Short name	T408
Test name
Test status
Simulation time	2158720100 ps
CPU time	58.57 seconds
Started	Jul 06 05:54:37 PM PDT 24
Finished	Jul 06 05:55:35 PM PDT 24
Peak memory	263680 kb
Host	smart-925c9037-541c-4e96-a539-beac1a9645b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748974643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2748974643
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.1400079134
Short name	T457
Test name
Test status
Simulation time	71574700 ps
CPU time	100.1 seconds
Started	Jul 06 05:54:40 PM PDT 24
Finished	Jul 06 05:56:20 PM PDT 24
Peak memory	277204 kb
Host	smart-7c0d7a7e-74c9-4e65-a1c3-160727497dcc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400079134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1400079134
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.2705028522
Short name	T661
Test name
Test status
Simulation time	48001800 ps
CPU time	13.69 seconds
Started	Jul 06 05:54:45 PM PDT 24
Finished	Jul 06 05:54:59 PM PDT 24
Peak memory	265256 kb
Host	smart-acea6484-5291-4e1d-9fda-9767df74c076
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705028522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test. 2705028522
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.37260863
Short name	T685
Test name
Test status
Simulation time	24983200 ps
CPU time	13.79 seconds
Started	Jul 06 05:54:45 PM PDT 24
Finished	Jul 06 05:54:59 PM PDT 24
Peak memory	284400 kb
Host	smart-a51f7633-9a9f-4a41-b4d5-a9e8b4d26948
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37260863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.37260863
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.872575039
Short name	T84
Test name
Test status
Simulation time	14595400 ps
CPU time	22.04 seconds
Started	Jul 06 05:54:42 PM PDT 24
Finished	Jul 06 05:55:04 PM PDT 24
Peak memory	266452 kb
Host	smart-87d1ef0b-5307-409e-b6f5-324855f1845d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872575039 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.872575039
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.684984293
Short name	T887
Test name
Test status
Simulation time	1678202100 ps
CPU time	42.36 seconds
Started	Jul 06 05:54:43 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	261000 kb
Host	smart-51678817-39e8-4b4a-9158-7f1866548af2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684984293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h w_sec_otp.684984293
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.4281395197
Short name	T765
Test name
Test status
Simulation time	747017400 ps
CPU time	126.99 seconds
Started	Jul 06 05:54:41 PM PDT 24
Finished	Jul 06 05:56:48 PM PDT 24
Peak memory	293220 kb
Host	smart-7e600a13-9d29-4651-a470-275775f5d45c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281395197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.4281395197
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3760490221
Short name	T784
Test name
Test status
Simulation time	6614275400 ps
CPU time	151.4 seconds
Started	Jul 06 05:54:42 PM PDT 24
Finished	Jul 06 05:57:14 PM PDT 24
Peak memory	294588 kb
Host	smart-7435f5d0-37bf-40f3-b443-78b71e19c8a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760490221 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3760490221
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.1197272393
Short name	T1082
Test name
Test status
Simulation time	38488100 ps
CPU time	111.14 seconds
Started	Jul 06 05:54:41 PM PDT 24
Finished	Jul 06 05:56:32 PM PDT 24
Peak memory	265188 kb
Host	smart-62a670e3-5f9a-4efe-997a-a24cc1624d69
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197272393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.1197272393
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.2659024475
Short name	T1097
Test name
Test status
Simulation time	672492400 ps
CPU time	70.21 seconds
Started	Jul 06 05:54:41 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	263884 kb
Host	smart-bee34134-eae9-4364-9df0-052db3b8f487
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659024475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2659024475
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.1209814053
Short name	T868
Test name
Test status
Simulation time	22116700 ps
CPU time	52.22 seconds
Started	Jul 06 05:54:43 PM PDT 24
Finished	Jul 06 05:55:35 PM PDT 24
Peak memory	271408 kb
Host	smart-61d734c1-9360-444e-a294-d020ce3135d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209814053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1209814053
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.1153054286
Short name	T671
Test name
Test status
Simulation time	152544800 ps
CPU time	13.87 seconds
Started	Jul 06 05:54:50 PM PDT 24
Finished	Jul 06 05:55:04 PM PDT 24
Peak memory	258348 kb
Host	smart-d9320a88-713f-486b-8ad7-e3ad3c0abd38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153054286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 1153054286
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.3012555174
Short name	T837
Test name
Test status
Simulation time	26901400 ps
CPU time	13.55 seconds
Started	Jul 06 05:54:50 PM PDT 24
Finished	Jul 06 05:55:04 PM PDT 24
Peak memory	274992 kb
Host	smart-b83efd20-c094-480b-bae8-518e0082f73a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012555174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3012555174
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.4273119525
Short name	T106
Test name
Test status
Simulation time	39765900 ps
CPU time	22.22 seconds
Started	Jul 06 05:54:45 PM PDT 24
Finished	Jul 06 05:55:08 PM PDT 24
Peak memory	265588 kb
Host	smart-71ebaadc-d000-4bdf-a519-6100618ac560
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273119525 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.4273119525
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3477454608
Short name	T463
Test name
Test status
Simulation time	18282624600 ps
CPU time	53.4 seconds
Started	Jul 06 05:54:46 PM PDT 24
Finished	Jul 06 05:55:40 PM PDT 24
Peak memory	263236 kb
Host	smart-9ca7b200-d92a-4df2-821d-18b4d2b522e8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477454608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.3477454608
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.1431819479
Short name	T820
Test name
Test status
Simulation time	1508738700 ps
CPU time	227.05 seconds
Started	Jul 06 05:54:45 PM PDT 24
Finished	Jul 06 05:58:32 PM PDT 24
Peak memory	285100 kb
Host	smart-84c6f10d-9458-4c0e-984e-a740572d67e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431819479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.1431819479
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.438074088
Short name	T328
Test name
Test status
Simulation time	12687433500 ps
CPU time	281.87 seconds
Started	Jul 06 05:54:49 PM PDT 24
Finished	Jul 06 05:59:31 PM PDT 24
Peak memory	290932 kb
Host	smart-ecf00b17-aa1c-4f90-9b0c-cdbcf3d09133
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438074088 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.438074088
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.52654062
Short name	T488
Test name
Test status
Simulation time	149079100 ps
CPU time	132.31 seconds
Started	Jul 06 05:54:47 PM PDT 24
Finished	Jul 06 05:57:00 PM PDT 24
Peak memory	265196 kb
Host	smart-cdab5c56-9c46-440d-9b63-3f5bc20c2610
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52654062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp _reset.52654062
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.4169869294
Short name	T483
Test name
Test status
Simulation time	31963600 ps
CPU time	29.16 seconds
Started	Jul 06 05:54:49 PM PDT 24
Finished	Jul 06 05:55:18 PM PDT 24
Peak memory	273216 kb
Host	smart-00961c28-d88e-4be6-bf68-c4891a8255cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169869294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.4169869294
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3015517757
Short name	T1043
Test name
Test status
Simulation time	27328100 ps
CPU time	28.03 seconds
Started	Jul 06 05:54:45 PM PDT 24
Finished	Jul 06 05:55:14 PM PDT 24
Peak memory	275744 kb
Host	smart-c4417312-4c0f-4740-9fa7-f3afd8a934a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015517757 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3015517757
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.3653487705
Short name	T476
Test name
Test status
Simulation time	43724000 ps
CPU time	148.02 seconds
Started	Jul 06 05:54:46 PM PDT 24
Finished	Jul 06 05:57:15 PM PDT 24
Peak memory	276728 kb
Host	smart-f0058174-b301-47b5-a1cd-157746b7c6f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653487705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3653487705
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.1729167459
Short name	T618
Test name
Test status
Simulation time	116878700 ps
CPU time	13.55 seconds
Started	Jul 06 05:54:57 PM PDT 24
Finished	Jul 06 05:55:10 PM PDT 24
Peak memory	258324 kb
Host	smart-eefa509f-923e-46e9-9486-058cd106767f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729167459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 1729167459
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.2700829614
Short name	T521
Test name
Test status
Simulation time	39055400 ps
CPU time	13.12 seconds
Started	Jul 06 05:54:53 PM PDT 24
Finished	Jul 06 05:55:06 PM PDT 24
Peak memory	284552 kb
Host	smart-93b0bad0-4c59-487e-8892-b44caec61f77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700829614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2700829614
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.1504334351
Short name	T111
Test name
Test status
Simulation time	10547200 ps
CPU time	20.72 seconds
Started	Jul 06 05:54:55 PM PDT 24
Finished	Jul 06 05:55:16 PM PDT 24
Peak memory	273528 kb
Host	smart-fb3076d7-faa7-42a0-a2e0-ab26350b539a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504334351 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.1504334351
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4201379067
Short name	T876
Test name
Test status
Simulation time	679198300 ps
CPU time	30.52 seconds
Started	Jul 06 05:54:51 PM PDT 24
Finished	Jul 06 05:55:21 PM PDT 24
Peak memory	260960 kb
Host	smart-ed22d510-417b-42bd-adc8-3a2e83e34151
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201379067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.4201379067
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.2175045500
Short name	T473
Test name
Test status
Simulation time	1864954400 ps
CPU time	197.65 seconds
Started	Jul 06 05:54:56 PM PDT 24
Finished	Jul 06 05:58:14 PM PDT 24
Peak memory	291568 kb
Host	smart-8cc509af-9493-4f2a-83c4-ae1c173ab2f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175045500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.2175045500
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2533584351
Short name	T166
Test name
Test status
Simulation time	5815229700 ps
CPU time	135.43 seconds
Started	Jul 06 05:54:56 PM PDT 24
Finished	Jul 06 05:57:12 PM PDT 24
Peak memory	292720 kb
Host	smart-2f01bf88-9638-4353-8541-467da70cc125
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533584351 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2533584351
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.219538364
Short name	T197
Test name
Test status
Simulation time	39761600 ps
CPU time	133.42 seconds
Started	Jul 06 05:54:55 PM PDT 24
Finished	Jul 06 05:57:09 PM PDT 24
Peak memory	264888 kb
Host	smart-61866a43-65b2-4f95-a439-f694a12a16e8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219538364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot p_reset.219538364
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.4019458384
Short name	T341
Test name
Test status
Simulation time	49011100 ps
CPU time	29.12 seconds
Started	Jul 06 05:54:54 PM PDT 24
Finished	Jul 06 05:55:23 PM PDT 24
Peak memory	275728 kb
Host	smart-29bddd25-66f1-4b91-9c80-d7e2afe78ac6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019458384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl ash_ctrl_rw_evict.4019458384
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1248231860
Short name	T452
Test name
Test status
Simulation time	70069900 ps
CPU time	31.41 seconds
Started	Jul 06 05:54:53 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	275700 kb
Host	smart-b1650eba-03b0-4161-94cf-e874432151de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248231860 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1248231860
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.2218333893
Short name	T949
Test name
Test status
Simulation time	5293428800 ps
CPU time	74 seconds
Started	Jul 06 05:54:56 PM PDT 24
Finished	Jul 06 05:56:10 PM PDT 24
Peak memory	263716 kb
Host	smart-655e5223-a1e7-4523-9b9e-32c942006756
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218333893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2218333893
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.1370225988
Short name	T803
Test name
Test status
Simulation time	23205100 ps
CPU time	53.08 seconds
Started	Jul 06 05:54:51 PM PDT 24
Finished	Jul 06 05:55:44 PM PDT 24
Peak memory	271324 kb
Host	smart-8f3acbf5-b485-449f-9a2c-b8b811cd1489
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370225988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1370225988
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.4108016145
Short name	T794
Test name
Test status
Simulation time	58607200 ps
CPU time	13.62 seconds
Started	Jul 06 05:55:04 PM PDT 24
Finished	Jul 06 05:55:18 PM PDT 24
Peak memory	265140 kb
Host	smart-bdb2ae61-76f7-4e15-ae91-1281fd2cba5a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108016145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 4108016145
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.2137930751
Short name	T1045
Test name
Test status
Simulation time	38278200 ps
CPU time	16.35 seconds
Started	Jul 06 05:55:00 PM PDT 24
Finished	Jul 06 05:55:16 PM PDT 24
Peak memory	274924 kb
Host	smart-77955210-fd4c-4abf-acc5-4171212e8ff4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137930751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2137930751
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.1851664043
Short name	T373
Test name
Test status
Simulation time	20107500 ps
CPU time	22.02 seconds
Started	Jul 06 05:55:00 PM PDT 24
Finished	Jul 06 05:55:22 PM PDT 24
Peak memory	273736 kb
Host	smart-09706267-3993-4f8e-ab4d-179f3a22e210
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851664043 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.1851664043
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2210662475
Short name	T768
Test name
Test status
Simulation time	3580526400 ps
CPU time	129.7 seconds
Started	Jul 06 05:54:54 PM PDT 24
Finished	Jul 06 05:57:04 PM PDT 24
Peak memory	262756 kb
Host	smart-c068b87c-960a-4ae0-a205-4942bf141243
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210662475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.2210662475
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2632751666
Short name	T1039
Test name
Test status
Simulation time	14199528900 ps
CPU time	253.17 seconds
Started	Jul 06 05:54:59 PM PDT 24
Finished	Jul 06 05:59:12 PM PDT 24
Peak memory	289988 kb
Host	smart-3d11bdc7-6bdd-43d5-9c14-6be7c7b21696
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632751666 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2632751666
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.3719367261
Short name	T1069
Test name
Test status
Simulation time	42170200 ps
CPU time	133.62 seconds
Started	Jul 06 05:54:55 PM PDT 24
Finished	Jul 06 05:57:09 PM PDT 24
Peak memory	264232 kb
Host	smart-7033d877-ac01-4efd-a4ff-c6cdb16e2f84
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719367261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.3719367261
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.3866573128
Short name	T806
Test name
Test status
Simulation time	77545100 ps
CPU time	30.67 seconds
Started	Jul 06 05:54:59 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	275660 kb
Host	smart-efe379e7-868d-4d35-8e97-ab1d4d0c9360
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866573128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl ash_ctrl_rw_evict.3866573128
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3663490344
Short name	T842
Test name
Test status
Simulation time	57359500 ps
CPU time	30.84 seconds
Started	Jul 06 05:55:00 PM PDT 24
Finished	Jul 06 05:55:31 PM PDT 24
Peak memory	267684 kb
Host	smart-41ec9c9a-887e-467b-b0b8-a7a9f9e99466
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663490344 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.3663490344
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.4194212620
Short name	T525
Test name
Test status
Simulation time	7639842500 ps
CPU time	55.94 seconds
Started	Jul 06 05:55:00 PM PDT 24
Finished	Jul 06 05:55:56 PM PDT 24
Peak memory	265060 kb
Host	smart-02147a57-3350-48a2-9919-da327d908e3c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194212620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.4194212620
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.3154232520
Short name	T1052
Test name
Test status
Simulation time	59850200 ps
CPU time	98.47 seconds
Started	Jul 06 05:54:56 PM PDT 24
Finished	Jul 06 05:56:35 PM PDT 24
Peak memory	275852 kb
Host	smart-2fcc8bf2-17a0-409c-87ed-ec1ada2eb14c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154232520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3154232520
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.714067533
Short name	T875
Test name
Test status
Simulation time	158284300 ps
CPU time	14.08 seconds
Started	Jul 06 05:49:59 PM PDT 24
Finished	Jul 06 05:50:13 PM PDT 24
Peak memory	258356 kb
Host	smart-8d898cfa-221d-4d89-ba5d-e8e75984cbde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714067533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.714067533
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.3855888649
Short name	T368
Test name
Test status
Simulation time	54234600 ps
CPU time	14.05 seconds
Started	Jul 06 05:49:59 PM PDT 24
Finished	Jul 06 05:50:13 PM PDT 24
Peak memory	261824 kb
Host	smart-5c2ee069-8620-44d5-a719-df56f2f56cb5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855888649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.3855888649
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.3032535916
Short name	T758
Test name
Test status
Simulation time	17631900 ps
CPU time	16.38 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 05:50:16 PM PDT 24
Peak memory	284388 kb
Host	smart-0b92f7aa-c1bf-4a43-a2f8-22cadf3ea66d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3032535916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3032535916
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.294362089
Short name	T714
Test name
Test status
Simulation time	69906600 ps
CPU time	21.55 seconds
Started	Jul 06 05:49:54 PM PDT 24
Finished	Jul 06 05:50:16 PM PDT 24
Peak memory	273596 kb
Host	smart-4cbeb222-1425-46da-ac39-8738cf417d78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294362089 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.294362089
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.593179263
Short name	T664
Test name
Test status
Simulation time	8578150800 ps
CPU time	565.09 seconds
Started	Jul 06 05:49:36 PM PDT 24
Finished	Jul 06 05:59:01 PM PDT 24
Peak memory	263564 kb
Host	smart-f03008f4-29b6-42a0-ad0d-7a40c17f13b6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=593179263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.593179263
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.3026513866
Short name	T501
Test name
Test status
Simulation time	51215560600 ps
CPU time	2263.02 seconds
Started	Jul 06 05:49:40 PM PDT 24
Finished	Jul 06 06:27:23 PM PDT 24
Peak memory	264916 kb
Host	smart-d257854e-5082-4c5f-8d63-43f897e6909c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3026513866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.3026513866
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.914194872
Short name	T982
Test name
Test status
Simulation time	3657236000 ps
CPU time	3181.96 seconds
Started	Jul 06 05:49:40 PM PDT 24
Finished	Jul 06 06:42:42 PM PDT 24
Peak memory	263996 kb
Host	smart-9c88d761-23fb-4f9a-9bdb-71833d00f599
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914194872 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 4.flash_ctrl_error_prog_type.914194872
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.2416367172
Short name	T206
Test name
Test status
Simulation time	2373585400 ps
CPU time	832.21 seconds
Started	Jul 06 05:49:39 PM PDT 24
Finished	Jul 06 06:03:31 PM PDT 24
Peak memory	273128 kb
Host	smart-3fe76495-62df-489e-b0bf-2c334a2bb0a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416367172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2416367172
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.1229841949
Short name	T1078
Test name
Test status
Simulation time	204489700 ps
CPU time	20.3 seconds
Started	Jul 06 05:49:41 PM PDT 24
Finished	Jul 06 05:50:01 PM PDT 24
Peak memory	263652 kb
Host	smart-9a1b5380-713b-4307-abe8-7dc4935bfb9f
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229841949 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1229841949
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.3318818150
Short name	T918
Test name
Test status
Simulation time	335690800 ps
CPU time	34.87 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 05:50:35 PM PDT 24
Peak memory	262996 kb
Host	smart-fe5caf96-df2e-4c3d-a79d-d7b806044d8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318818150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.3318818150
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.4188037220
Short name	T1068
Test name
Test status
Simulation time	325285416900 ps
CPU time	2503.34 seconds
Started	Jul 06 05:49:40 PM PDT 24
Finished	Jul 06 06:31:24 PM PDT 24
Peak memory	264432 kb
Host	smart-09017184-91f3-4c80-95a1-2a891a1787eb
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188037220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.4188037220
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.2031488059
Short name	T522
Test name
Test status
Simulation time	58180400 ps
CPU time	48.98 seconds
Started	Jul 06 05:49:29 PM PDT 24
Finished	Jul 06 05:50:19 PM PDT 24
Peak memory	265192 kb
Host	smart-ff5a3225-9558-447b-b201-d54940c8155b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2031488059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2031488059
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3918012826
Short name	T944
Test name
Test status
Simulation time	10013652200 ps
CPU time	118.24 seconds
Started	Jul 06 05:49:58 PM PDT 24
Finished	Jul 06 05:51:57 PM PDT 24
Peak memory	345064 kb
Host	smart-df853496-dd38-41db-8ea5-a3d915ef07ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918012826 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3918012826
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3598180713
Short name	T823
Test name
Test status
Simulation time	47449800 ps
CPU time	13.35 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 05:50:13 PM PDT 24
Peak memory	265448 kb
Host	smart-12686a97-64e0-465d-ad19-1272aa6d143a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598180713 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3598180713
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.4248419257
Short name	T123
Test name
Test status
Simulation time	630363706900 ps
CPU time	945.34 seconds
Started	Jul 06 05:49:35 PM PDT 24
Finished	Jul 06 06:05:21 PM PDT 24
Peak memory	261188 kb
Host	smart-3b104cc5-094a-4d85-8611-255327e73a85
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248419257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.4248419257
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2421485596
Short name	T716
Test name
Test status
Simulation time	4025744800 ps
CPU time	68.93 seconds
Started	Jul 06 05:49:35 PM PDT 24
Finished	Jul 06 05:50:44 PM PDT 24
Peak memory	262856 kb
Host	smart-01f5998e-8e25-4b92-9dc5-85a81bf9f142
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421485596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.2421485596
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.1619572169
Short name	T254
Test name
Test status
Simulation time	6840670100 ps
CPU time	607.02 seconds
Started	Jul 06 05:49:57 PM PDT 24
Finished	Jul 06 06:00:05 PM PDT 24
Peak memory	329312 kb
Host	smart-92e89f7b-7f71-4481-84fe-2b24ce194136
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619572169 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.1619572169
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.1592997969
Short name	T915
Test name
Test status
Simulation time	1295486400 ps
CPU time	146.63 seconds
Started	Jul 06 05:49:57 PM PDT 24
Finished	Jul 06 05:52:23 PM PDT 24
Peak memory	294088 kb
Host	smart-01e97983-f330-4b8a-bfd3-c7f420b95ca7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592997969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_intr_rd.1592997969
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2838988140
Short name	T429
Test name
Test status
Simulation time	5890259300 ps
CPU time	136.04 seconds
Started	Jul 06 05:49:54 PM PDT 24
Finished	Jul 06 05:52:11 PM PDT 24
Peak memory	293008 kb
Host	smart-358dd0a7-2c18-4bc2-b1cb-72e2c89b324c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838988140 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2838988140
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.716687090
Short name	T566
Test name
Test status
Simulation time	2064842600 ps
CPU time	65.66 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:51:02 PM PDT 24
Peak memory	265108 kb
Host	smart-94ac95f4-4c4e-474d-89c9-b77cf2589840
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716687090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_intr_wr.716687090
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2640261130
Short name	T967
Test name
Test status
Simulation time	225955677700 ps
CPU time	366.49 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:56:03 PM PDT 24
Peak memory	265428 kb
Host	smart-1130278f-ed79-4214-9fd7-301aa84a9014
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264 0261130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2640261130
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.1557393384
Short name	T487
Test name
Test status
Simulation time	2383781500 ps
CPU time	87.49 seconds
Started	Jul 06 05:49:43 PM PDT 24
Finished	Jul 06 05:51:11 PM PDT 24
Peak memory	262544 kb
Host	smart-0deaf037-5dc9-4853-940d-a4055d988f55
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557393384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1557393384
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.940893026
Short name	T1085
Test name
Test status
Simulation time	15966200 ps
CPU time	13.41 seconds
Started	Jul 06 05:50:01 PM PDT 24
Finished	Jul 06 05:50:14 PM PDT 24
Peak memory	260884 kb
Host	smart-dbdca447-8dfc-4283-a622-3c309b5ff2db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940893026 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.940893026
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.3467456351
Short name	T172
Test name
Test status
Simulation time	935254700 ps
CPU time	67.89 seconds
Started	Jul 06 05:49:44 PM PDT 24
Finished	Jul 06 05:50:52 PM PDT 24
Peak memory	260600 kb
Host	smart-04ae3b94-cc23-4ad1-abb2-6c13533dee32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467456351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3467456351
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.3297819228
Short name	T906
Test name
Test status
Simulation time	1567834700 ps
CPU time	161.12 seconds
Started	Jul 06 05:49:39 PM PDT 24
Finished	Jul 06 05:52:21 PM PDT 24
Peak memory	265096 kb
Host	smart-6a207810-3f22-4db7-9079-7066aae0250d
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297819228 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.3297819228
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.3342591515
Short name	T312
Test name
Test status
Simulation time	717671300 ps
CPU time	110.93 seconds
Started	Jul 06 05:49:34 PM PDT 24
Finished	Jul 06 05:51:25 PM PDT 24
Peak memory	261044 kb
Host	smart-0e44245a-1649-4888-a3b0-3e7c5a294dbe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342591515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot p_reset.3342591515
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.2172821142
Short name	T807
Test name
Test status
Simulation time	22902253100 ps
CPU time	216.94 seconds
Started	Jul 06 05:49:57 PM PDT 24
Finished	Jul 06 05:53:34 PM PDT 24
Peak memory	281792 kb
Host	smart-4d1dd7b5-fe13-4ef9-b44d-17dbab046667
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172821142 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2172821142
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.398665326
Short name	T169
Test name
Test status
Simulation time	26192300 ps
CPU time	13.76 seconds
Started	Jul 06 05:49:58 PM PDT 24
Finished	Jul 06 05:50:12 PM PDT 24
Peak memory	261244 kb
Host	smart-25c2b88f-e1a7-4523-9469-090c6c1db5ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=398665326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.398665326
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.2988758546
Short name	T959
Test name
Test status
Simulation time	109096900 ps
CPU time	111.64 seconds
Started	Jul 06 05:49:35 PM PDT 24
Finished	Jul 06 05:51:27 PM PDT 24
Peak memory	263192 kb
Host	smart-56b01ed4-adba-46f2-b6ec-58296500861e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2988758546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2988758546
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1099021573
Short name	T79
Test name
Test status
Simulation time	655773500 ps
CPU time	17.65 seconds
Started	Jul 06 05:49:59 PM PDT 24
Finished	Jul 06 05:50:17 PM PDT 24
Peak memory	265412 kb
Host	smart-571e146f-4627-4850-9f2c-9eed9984868d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099021573 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1099021573
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.3522661045
Short name	T821
Test name
Test status
Simulation time	112322000 ps
CPU time	13.5 seconds
Started	Jul 06 05:49:55 PM PDT 24
Finished	Jul 06 05:50:09 PM PDT 24
Peak memory	259072 kb
Host	smart-a21d4392-8b88-4a3f-9e9e-650b946d3864
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522661045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.flash_ctrl_prog_reset.3522661045
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.3969652511
Short name	T550
Test name
Test status
Simulation time	354031900 ps
CPU time	272.94 seconds
Started	Jul 06 05:49:24 PM PDT 24
Finished	Jul 06 05:53:57 PM PDT 24
Peak memory	281104 kb
Host	smart-b4119c8f-dc93-4b62-aef8-488b385c764a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969652511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3969652511
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1096762001
Short name	T973
Test name
Test status
Simulation time	130970900 ps
CPU time	102.48 seconds
Started	Jul 06 05:49:34 PM PDT 24
Finished	Jul 06 05:51:17 PM PDT 24
Peak memory	262916 kb
Host	smart-e1f422fa-29e7-4f58-97a5-634f2933b4a3
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1096762001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1096762001
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.4086945117
Short name	T280
Test name
Test status
Simulation time	159114900 ps
CPU time	33.25 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:50:29 PM PDT 24
Peak memory	273600 kb
Host	smart-0b016ce2-075c-4ea3-983f-bff44e46f146
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086945117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.4086945117
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3442548351
Short name	T1095
Test name
Test status
Simulation time	19517200 ps
CPU time	22.38 seconds
Started	Jul 06 05:49:58 PM PDT 24
Finished	Jul 06 05:50:21 PM PDT 24
Peak memory	265408 kb
Host	smart-9f93a9aa-52a2-403a-9654-cfff4632c4fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442548351 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3442548351
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2204987075
Short name	T568
Test name
Test status
Simulation time	85831100 ps
CPU time	21.42 seconds
Started	Jul 06 05:49:45 PM PDT 24
Finished	Jul 06 05:50:07 PM PDT 24
Peak memory	265384 kb
Host	smart-7ceb18c2-fe11-436c-b63d-44fd9a93e835
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204987075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.2204987075
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.993869966
Short name	T981
Test name
Test status
Simulation time	1447448000 ps
CPU time	128.38 seconds
Started	Jul 06 05:49:45 PM PDT 24
Finished	Jul 06 05:51:54 PM PDT 24
Peak memory	289188 kb
Host	smart-ecbbb08b-19ac-4a14-856a-24f457883847
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993869966 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.flash_ctrl_ro.993869966
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.4269733810
Short name	T1046
Test name
Test status
Simulation time	506436000 ps
CPU time	133.95 seconds
Started	Jul 06 05:49:57 PM PDT 24
Finished	Jul 06 05:52:12 PM PDT 24
Peak memory	281752 kb
Host	smart-2308244d-771d-4746-b03a-cea6f1e6fab6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4269733810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.4269733810
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.3140773142
Short name	T610
Test name
Test status
Simulation time	676152600 ps
CPU time	158.32 seconds
Started	Jul 06 05:49:44 PM PDT 24
Finished	Jul 06 05:52:23 PM PDT 24
Peak memory	290020 kb
Host	smart-3618e6a4-00fa-482f-bb7d-26b5b71555fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140773142 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3140773142
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.3506592243
Short name	T517
Test name
Test status
Simulation time	16021069800 ps
CPU time	607.14 seconds
Started	Jul 06 05:49:46 PM PDT 24
Finished	Jul 06 05:59:53 PM PDT 24
Peak memory	314516 kb
Host	smart-83a09425-ac99-4c9f-afcc-46c80b03df98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506592243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.flash_ctrl_rw.3506592243
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.2056784825
Short name	T284
Test name
Test status
Simulation time	75581300 ps
CPU time	31.54 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:50:28 PM PDT 24
Peak memory	275668 kb
Host	smart-0b12c472-a7fe-4429-8666-c8a1464b8928
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056784825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_rw_evict.2056784825
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2867973745
Short name	T677
Test name
Test status
Simulation time	38085800 ps
CPU time	30.29 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:50:26 PM PDT 24
Peak memory	268484 kb
Host	smart-7a95064f-1176-4af4-9d92-e4a869e6ff16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867973745 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2867973745
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.3951790316
Short name	T127
Test name
Test status
Simulation time	5506180100 ps
CPU time	4750.48 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 07:09:11 PM PDT 24
Peak memory	283528 kb
Host	smart-ac731673-7c81-4b98-a1b9-7df40e213b05
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951790316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3951790316
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.4253692560
Short name	T403
Test name
Test status
Simulation time	445688500 ps
CPU time	63.37 seconds
Started	Jul 06 05:49:59 PM PDT 24
Finished	Jul 06 05:51:02 PM PDT 24
Peak memory	264808 kb
Host	smart-c81f6b00-f30a-4414-808a-8e92c4b798f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253692560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.4253692560
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.3340795717
Short name	T44
Test name
Test status
Simulation time	12790915000 ps
CPU time	99.35 seconds
Started	Jul 06 05:49:56 PM PDT 24
Finished	Jul 06 05:51:36 PM PDT 24
Peak memory	273628 kb
Host	smart-1ed2fda7-8676-4bac-9b49-e9501e9b3108
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340795717 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.3340795717
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.4092415765
Short name	T597
Test name
Test status
Simulation time	362972500 ps
CPU time	48.81 seconds
Started	Jul 06 05:50:01 PM PDT 24
Finished	Jul 06 05:50:50 PM PDT 24
Peak memory	273656 kb
Host	smart-d01a16cc-a469-485d-99c3-fef0b4e9c472
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092415765 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.4092415765
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.4025718189
Short name	T424
Test name
Test status
Simulation time	27467000 ps
CPU time	77.35 seconds
Started	Jul 06 05:49:25 PM PDT 24
Finished	Jul 06 05:50:42 PM PDT 24
Peak memory	275920 kb
Host	smart-1812c3ff-416b-424f-83c8-fb55513dea52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025718189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4025718189
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.3542255987
Short name	T893
Test name
Test status
Simulation time	28328200 ps
CPU time	26.02 seconds
Started	Jul 06 05:49:23 PM PDT 24
Finished	Jul 06 05:49:49 PM PDT 24
Peak memory	259756 kb
Host	smart-eaadca6e-b2dd-4ded-9bca-72877cd67fef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542255987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3542255987
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.1633933583
Short name	T1054
Test name
Test status
Simulation time	356008500 ps
CPU time	1494 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 06:14:55 PM PDT 24
Peak memory	288696 kb
Host	smart-10a8d243-236c-4efa-95ef-2b571763aa1c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633933583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.1633933583
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.3845350352
Short name	T306
Test name
Test status
Simulation time	40979500 ps
CPU time	27.24 seconds
Started	Jul 06 05:49:29 PM PDT 24
Finished	Jul 06 05:49:57 PM PDT 24
Peak memory	262456 kb
Host	smart-825e5aac-9bd8-4b42-92a8-26871567206d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845350352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3845350352
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.1449704557
Short name	T231
Test name
Test status
Simulation time	2359236500 ps
CPU time	203.15 seconds
Started	Jul 06 05:49:45 PM PDT 24
Finished	Jul 06 05:53:08 PM PDT 24
Peak memory	265340 kb
Host	smart-f6e9ea88-d634-4a4b-83aa-51283dce36bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449704557 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.1449704557
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.1346657085
Short name	T520
Test name
Test status
Simulation time	67251700 ps
CPU time	13.41 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:55:23 PM PDT 24
Peak memory	265316 kb
Host	smart-6f20747c-1657-4c2b-abe3-8b74b577fac6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346657085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 1346657085
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.3244886294
Short name	T1092
Test name
Test status
Simulation time	45019100 ps
CPU time	16.04 seconds
Started	Jul 06 05:55:08 PM PDT 24
Finished	Jul 06 05:55:24 PM PDT 24
Peak memory	274892 kb
Host	smart-4e034fa2-478f-4566-8ee3-5ea0a2455d50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244886294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3244886294
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.3201416964
Short name	T904
Test name
Test status
Simulation time	26914700 ps
CPU time	20.47 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	273696 kb
Host	smart-47f10009-70c2-4898-b96a-197084c4c7a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201416964 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.3201416964
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.4136247115
Short name	T792
Test name
Test status
Simulation time	4909997200 ps
CPU time	100.47 seconds
Started	Jul 06 05:55:04 PM PDT 24
Finished	Jul 06 05:56:45 PM PDT 24
Peak memory	262792 kb
Host	smart-1d3456bc-4210-468d-8c33-860baa08c8af
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136247115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ hw_sec_otp.4136247115
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.1189347509
Short name	T924
Test name
Test status
Simulation time	39422400 ps
CPU time	132.6 seconds
Started	Jul 06 05:55:04 PM PDT 24
Finished	Jul 06 05:57:16 PM PDT 24
Peak memory	260004 kb
Host	smart-fbdd0aa3-cb82-40c4-ae94-54c97bb93319
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189347509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o tp_reset.1189347509
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.1098272167
Short name	T405
Test name
Test status
Simulation time	1273898300 ps
CPU time	52.5 seconds
Started	Jul 06 05:55:03 PM PDT 24
Finished	Jul 06 05:55:56 PM PDT 24
Peak memory	263708 kb
Host	smart-893a940b-d2e7-47c2-838e-e70631bd922d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1098272167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1098272167
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.1184122966
Short name	T1101
Test name
Test status
Simulation time	44629900 ps
CPU time	49.75 seconds
Started	Jul 06 05:55:09 PM PDT 24
Finished	Jul 06 05:55:59 PM PDT 24
Peak memory	271416 kb
Host	smart-fba60576-ebd0-46b8-9adc-59d25cfc1fb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184122966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1184122966
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.4175969339
Short name	T474
Test name
Test status
Simulation time	51443700 ps
CPU time	13.54 seconds
Started	Jul 06 05:55:09 PM PDT 24
Finished	Jul 06 05:55:22 PM PDT 24
Peak memory	265268 kb
Host	smart-6b1c89f9-980f-43cd-a894-af4fbbd21ce8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175969339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 4175969339
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.2202247372
Short name	T596
Test name
Test status
Simulation time	29286800 ps
CPU time	15.98 seconds
Started	Jul 06 05:55:09 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	284348 kb
Host	smart-e5645be7-b7d6-4746-aef5-edfc0f1042c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202247372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2202247372
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.1322505580
Short name	T489
Test name
Test status
Simulation time	32220300 ps
CPU time	21.2 seconds
Started	Jul 06 05:55:09 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	273568 kb
Host	smart-dc2b690c-3379-49f7-9272-019c62440adb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322505580 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.1322505580
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3865016197
Short name	T609
Test name
Test status
Simulation time	6070790800 ps
CPU time	131.71 seconds
Started	Jul 06 05:55:04 PM PDT 24
Finished	Jul 06 05:57:16 PM PDT 24
Peak memory	260984 kb
Host	smart-d5d553ba-eb03-44b9-bc5a-d23f8aaa34d7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865016197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.3865016197
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.1733700807
Short name	T75
Test name
Test status
Simulation time	75498500 ps
CPU time	111.92 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:57:02 PM PDT 24
Peak memory	260012 kb
Host	smart-6a7075aa-6bc7-4d17-8d81-8f010c0ac08f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733700807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.1733700807
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.2504440606
Short name	T394
Test name
Test status
Simulation time	5980475100 ps
CPU time	76.41 seconds
Started	Jul 06 05:55:08 PM PDT 24
Finished	Jul 06 05:56:24 PM PDT 24
Peak memory	264616 kb
Host	smart-c06bc916-f5f2-4a4c-acb8-e7f3ad971eae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504440606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2504440606
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.2951377007
Short name	T498
Test name
Test status
Simulation time	19932200 ps
CPU time	97.88 seconds
Started	Jul 06 05:55:05 PM PDT 24
Finished	Jul 06 05:56:43 PM PDT 24
Peak memory	277080 kb
Host	smart-dd8ec1fb-5d37-471d-8706-c9c3265997a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951377007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2951377007
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.1822043736
Short name	T447
Test name
Test status
Simulation time	61592200 ps
CPU time	13.57 seconds
Started	Jul 06 05:55:15 PM PDT 24
Finished	Jul 06 05:55:29 PM PDT 24
Peak memory	258272 kb
Host	smart-c2cefe37-fe1f-4e07-bd2e-a681b6453ffd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822043736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 1822043736
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.1375426288
Short name	T1038
Test name
Test status
Simulation time	21654600 ps
CPU time	15.95 seconds
Started	Jul 06 05:55:08 PM PDT 24
Finished	Jul 06 05:55:25 PM PDT 24
Peak memory	274960 kb
Host	smart-8cf0c55c-eb5f-4559-8074-7e373235512c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1375426288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1375426288
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.38416178
Short name	T702
Test name
Test status
Simulation time	23009800 ps
CPU time	21.11 seconds
Started	Jul 06 05:55:09 PM PDT 24
Finished	Jul 06 05:55:31 PM PDT 24
Peak memory	273636 kb
Host	smart-f95d61b5-def2-4224-a587-99c3c142c0bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38416178 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 42.flash_ctrl_disable.38416178
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3374269554
Short name	T104
Test name
Test status
Simulation time	896056300 ps
CPU time	47.62 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:55:58 PM PDT 24
Peak memory	262840 kb
Host	smart-f553fcbb-f294-40ad-8081-d77044fb3f85
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374269554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ hw_sec_otp.3374269554
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.1484593630
Short name	T192
Test name
Test status
Simulation time	324962400 ps
CPU time	131.38 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:57:21 PM PDT 24
Peak memory	260100 kb
Host	smart-77b56199-7f4d-4531-95f2-93ba6af767ce
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484593630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.1484593630
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.3633979668
Short name	T920
Test name
Test status
Simulation time	63486800 ps
CPU time	100.04 seconds
Started	Jul 06 05:55:10 PM PDT 24
Finished	Jul 06 05:56:50 PM PDT 24
Peak memory	276184 kb
Host	smart-6367e906-89e6-4d8a-a77d-7d56c03ec0c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633979668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3633979668
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.4243035179
Short name	T1090
Test name
Test status
Simulation time	116392200 ps
CPU time	13.83 seconds
Started	Jul 06 05:55:14 PM PDT 24
Finished	Jul 06 05:55:28 PM PDT 24
Peak memory	258252 kb
Host	smart-fe792fa5-880e-4da4-b53c-659d0fa548b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243035179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 4243035179
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.651831505
Short name	T853
Test name
Test status
Simulation time	39792700 ps
CPU time	13.43 seconds
Started	Jul 06 05:55:16 PM PDT 24
Finished	Jul 06 05:55:30 PM PDT 24
Peak memory	284320 kb
Host	smart-9b6e898c-77c2-4090-9278-573e9f230de4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651831505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.651831505
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.2395178852
Short name	T107
Test name
Test status
Simulation time	28754200 ps
CPU time	22.03 seconds
Started	Jul 06 05:55:14 PM PDT 24
Finished	Jul 06 05:55:36 PM PDT 24
Peak memory	273628 kb
Host	smart-3540c279-d4c3-4fe8-b111-b04e76e9c9cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395178852 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.2395178852
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2165429718
Short name	T412
Test name
Test status
Simulation time	25159581800 ps
CPU time	132.54 seconds
Started	Jul 06 05:55:14 PM PDT 24
Finished	Jul 06 05:57:27 PM PDT 24
Peak memory	260956 kb
Host	smart-50d6f91f-118c-45a9-bf5a-4f5244de5b51
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165429718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.2165429718
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.2976571837
Short name	T395
Test name
Test status
Simulation time	476865900 ps
CPU time	60.29 seconds
Started	Jul 06 05:55:15 PM PDT 24
Finished	Jul 06 05:56:15 PM PDT 24
Peak memory	263712 kb
Host	smart-345dc16f-82e4-46bf-bdd7-4b78e02b4442
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976571837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2976571837
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.1104162578
Short name	T834
Test name
Test status
Simulation time	45291300 ps
CPU time	75.98 seconds
Started	Jul 06 05:55:16 PM PDT 24
Finished	Jul 06 05:56:32 PM PDT 24
Peak memory	275536 kb
Host	smart-91f8d984-69ef-4cc5-9655-b2bf26e4dd21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104162578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1104162578
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.490501076
Short name	T1019
Test name
Test status
Simulation time	86355800 ps
CPU time	13.68 seconds
Started	Jul 06 05:55:17 PM PDT 24
Finished	Jul 06 05:55:31 PM PDT 24
Peak memory	265296 kb
Host	smart-e7353ac5-9a1b-4350-9dee-65007b80ba21
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490501076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.490501076
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.1562531426
Short name	T486
Test name
Test status
Simulation time	15339900 ps
CPU time	14.1 seconds
Started	Jul 06 05:55:19 PM PDT 24
Finished	Jul 06 05:55:34 PM PDT 24
Peak memory	274932 kb
Host	smart-16a48cca-f860-4bbf-8313-78712da6e9a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562531426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1562531426
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.1697974154
Short name	T175
Test name
Test status
Simulation time	14585700 ps
CPU time	22.04 seconds
Started	Jul 06 05:55:14 PM PDT 24
Finished	Jul 06 05:55:37 PM PDT 24
Peak memory	273620 kb
Host	smart-364bb785-1e2b-4cb8-8751-549983add348
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697974154 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.1697974154
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1551229473
Short name	T1104
Test name
Test status
Simulation time	8605494500 ps
CPU time	131.14 seconds
Started	Jul 06 05:55:13 PM PDT 24
Finished	Jul 06 05:57:24 PM PDT 24
Peak memory	261972 kb
Host	smart-0609a82c-fcb7-4ff8-a883-0b6ba7ecd459
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551229473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.1551229473
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.4289728266
Short name	T198
Test name
Test status
Simulation time	154673400 ps
CPU time	130.78 seconds
Started	Jul 06 05:55:13 PM PDT 24
Finished	Jul 06 05:57:24 PM PDT 24
Peak memory	261060 kb
Host	smart-dec1d890-9830-4d73-94af-29b760f1ff5a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289728266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.4289728266
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.353310255
Short name	T681
Test name
Test status
Simulation time	5602102300 ps
CPU time	69.7 seconds
Started	Jul 06 05:55:14 PM PDT 24
Finished	Jul 06 05:56:23 PM PDT 24
Peak memory	264820 kb
Host	smart-6ec2804c-90f8-4b58-9e06-b5e045874b43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=353310255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.353310255
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.3138811302
Short name	T968
Test name
Test status
Simulation time	198039900 ps
CPU time	171.12 seconds
Started	Jul 06 05:55:13 PM PDT 24
Finished	Jul 06 05:58:04 PM PDT 24
Peak memory	277140 kb
Host	smart-b79802a2-b308-4bbb-a220-ccf2f819a020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138811302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3138811302
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.797231228
Short name	T1056
Test name
Test status
Simulation time	242181600 ps
CPU time	13.79 seconds
Started	Jul 06 05:55:19 PM PDT 24
Finished	Jul 06 05:55:33 PM PDT 24
Peak memory	265168 kb
Host	smart-f9219b1d-51e2-4925-a09f-e3dbc87d8b27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797231228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.797231228
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.1012792150
Short name	T537
Test name
Test status
Simulation time	65255300 ps
CPU time	13.21 seconds
Started	Jul 06 05:55:22 PM PDT 24
Finished	Jul 06 05:55:36 PM PDT 24
Peak memory	284412 kb
Host	smart-7929da16-8194-4aee-9c1c-1e6972991ae1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012792150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1012792150
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3961201448
Short name	T1014
Test name
Test status
Simulation time	3996461300 ps
CPU time	127.25 seconds
Started	Jul 06 05:55:17 PM PDT 24
Finished	Jul 06 05:57:25 PM PDT 24
Peak memory	260960 kb
Host	smart-4d689e35-ce52-4a1b-a1a5-4ee47375adc3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961201448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.3961201448
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.2510402882
Short name	T971
Test name
Test status
Simulation time	38949900 ps
CPU time	133.16 seconds
Started	Jul 06 05:55:16 PM PDT 24
Finished	Jul 06 05:57:30 PM PDT 24
Peak memory	261220 kb
Host	smart-ff7c5a92-239d-4838-8da1-e47edf79a377
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510402882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.2510402882
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.155654363
Short name	T1
Test name
Test status
Simulation time	1111123600 ps
CPU time	62.16 seconds
Started	Jul 06 05:55:18 PM PDT 24
Finished	Jul 06 05:56:20 PM PDT 24
Peak memory	263852 kb
Host	smart-ccc78ff7-a9c6-4574-a65c-9c9cf982f92f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155654363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.155654363
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.3366894376
Short name	T883
Test name
Test status
Simulation time	33986200 ps
CPU time	121.95 seconds
Started	Jul 06 05:55:18 PM PDT 24
Finished	Jul 06 05:57:20 PM PDT 24
Peak memory	276648 kb
Host	smart-d9f97ed9-869e-40fc-b61b-1fd8241fea69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366894376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3366894376
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.1478083805
Short name	T145
Test name
Test status
Simulation time	93470100 ps
CPU time	13.53 seconds
Started	Jul 06 05:55:24 PM PDT 24
Finished	Jul 06 05:55:37 PM PDT 24
Peak memory	258332 kb
Host	smart-cfd4e1f2-29cf-4200-aad3-948e98274621
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478083805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 1478083805
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.3105100266
Short name	T990
Test name
Test status
Simulation time	50471500 ps
CPU time	16.17 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:55:40 PM PDT 24
Peak memory	275028 kb
Host	smart-9af0630d-7a95-4a95-8fb5-0fe0f5212f22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3105100266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3105100266
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.841862118
Short name	T374
Test name
Test status
Simulation time	14890500 ps
CPU time	21.79 seconds
Started	Jul 06 05:55:20 PM PDT 24
Finished	Jul 06 05:55:42 PM PDT 24
Peak memory	274668 kb
Host	smart-a53b07ef-e212-4922-b51c-e7b7357bd537
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841862118 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.841862118
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1071637764
Short name	T762
Test name
Test status
Simulation time	14052782500 ps
CPU time	128.17 seconds
Started	Jul 06 05:55:19 PM PDT 24
Finished	Jul 06 05:57:28 PM PDT 24
Peak memory	263176 kb
Host	smart-c31e9d88-c3ca-44db-93e5-595dc3135eb2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071637764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.1071637764
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.2406006271
Short name	T1031
Test name
Test status
Simulation time	191158200 ps
CPU time	131.14 seconds
Started	Jul 06 05:55:21 PM PDT 24
Finished	Jul 06 05:57:33 PM PDT 24
Peak memory	261108 kb
Host	smart-fde9047d-a191-48fd-8893-0b25d51bd21e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406006271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.2406006271
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.837936990
Short name	T808
Test name
Test status
Simulation time	1685811900 ps
CPU time	52.66 seconds
Started	Jul 06 05:55:17 PM PDT 24
Finished	Jul 06 05:56:10 PM PDT 24
Peak memory	264748 kb
Host	smart-4837dd0d-05d5-4120-ba90-b9c114857b10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837936990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.837936990
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.3246424918
Short name	T976
Test name
Test status
Simulation time	39710700 ps
CPU time	176.24 seconds
Started	Jul 06 05:55:19 PM PDT 24
Finished	Jul 06 05:58:16 PM PDT 24
Peak memory	277132 kb
Host	smart-fe82d78f-1b11-418a-a1f8-76f8676ba940
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246424918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3246424918
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.280643252
Short name	T651
Test name
Test status
Simulation time	46036400 ps
CPU time	13.48 seconds
Started	Jul 06 05:55:29 PM PDT 24
Finished	Jul 06 05:55:43 PM PDT 24
Peak memory	265248 kb
Host	smart-ef6cb2dc-4d4b-4539-9506-81ac295abf17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280643252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.280643252
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.3770296159
Short name	T856
Test name
Test status
Simulation time	15651100 ps
CPU time	15.66 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:55:39 PM PDT 24
Peak memory	274968 kb
Host	smart-da1a77d0-f9b9-42c3-9791-176982772a84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770296159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3770296159
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.4271364575
Short name	T937
Test name
Test status
Simulation time	29503000 ps
CPU time	21.77 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:55:45 PM PDT 24
Peak memory	265664 kb
Host	smart-0d6e3c37-ec70-43f9-8791-a823b9ead0bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271364575 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.4271364575
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3412406758
Short name	T1055
Test name
Test status
Simulation time	5702840300 ps
CPU time	176.57 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:58:20 PM PDT 24
Peak memory	260980 kb
Host	smart-2da63e40-ad29-4e32-9414-f737fd3686b1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412406758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.3412406758
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.12017526
Short name	T182
Test name
Test status
Simulation time	51817100 ps
CPU time	111.69 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:57:15 PM PDT 24
Peak memory	264824 kb
Host	smart-77e6dd67-7b72-494c-b9f0-70b3ae31fd2e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12017526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp _reset.12017526
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.3965148357
Short name	T396
Test name
Test status
Simulation time	695350400 ps
CPU time	52.62 seconds
Started	Jul 06 05:55:22 PM PDT 24
Finished	Jul 06 05:56:15 PM PDT 24
Peak memory	263152 kb
Host	smart-a3b103ef-bf72-44cb-ae03-c4fd03588913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965148357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3965148357
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.3595066950
Short name	T724
Test name
Test status
Simulation time	22444800 ps
CPU time	97.81 seconds
Started	Jul 06 05:55:23 PM PDT 24
Finished	Jul 06 05:57:01 PM PDT 24
Peak memory	275988 kb
Host	smart-81d2e0d7-7b3d-4d3e-99c8-a6da3c18e585
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595066950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3595066950
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.1617875295
Short name	T872
Test name
Test status
Simulation time	38216300 ps
CPU time	13.72 seconds
Started	Jul 06 05:55:30 PM PDT 24
Finished	Jul 06 05:55:44 PM PDT 24
Peak memory	265196 kb
Host	smart-e6284536-be51-4ff0-8331-5e23a42059b6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617875295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 1617875295
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.192048891
Short name	T839
Test name
Test status
Simulation time	38878200 ps
CPU time	16.03 seconds
Started	Jul 06 05:55:30 PM PDT 24
Finished	Jul 06 05:55:46 PM PDT 24
Peak memory	274864 kb
Host	smart-905044ca-e943-4018-be15-d8f1276926b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192048891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.192048891
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.108632088
Short name	T1034
Test name
Test status
Simulation time	89331500 ps
CPU time	22.01 seconds
Started	Jul 06 05:55:29 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	273564 kb
Host	smart-156f83b1-7665-4eea-93eb-b4eb4befc9f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108632088 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.108632088
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.4148753522
Short name	T740
Test name
Test status
Simulation time	2810546700 ps
CPU time	91.21 seconds
Started	Jul 06 05:55:30 PM PDT 24
Finished	Jul 06 05:57:02 PM PDT 24
Peak memory	260888 kb
Host	smart-dc40767e-e5ea-4314-bf29-de4b33c7427c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148753522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ hw_sec_otp.4148753522
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.973246620
Short name	T1109
Test name
Test status
Simulation time	78281400 ps
CPU time	110.89 seconds
Started	Jul 06 05:55:28 PM PDT 24
Finished	Jul 06 05:57:19 PM PDT 24
Peak memory	265260 kb
Host	smart-fd456694-f8a7-4b80-838b-0344be22f40b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973246620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot p_reset.973246620
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.3003843275
Short name	T804
Test name
Test status
Simulation time	2103871900 ps
CPU time	72.76 seconds
Started	Jul 06 05:55:29 PM PDT 24
Finished	Jul 06 05:56:42 PM PDT 24
Peak memory	263584 kb
Host	smart-7ebaf5a3-d890-4e81-81bd-c41f828d3b5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003843275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3003843275
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.2332101687
Short name	T378
Test name
Test status
Simulation time	356492800 ps
CPU time	74.53 seconds
Started	Jul 06 05:55:30 PM PDT 24
Finished	Jul 06 05:56:45 PM PDT 24
Peak memory	275964 kb
Host	smart-eaed6e69-f647-47ec-b147-827781636fa2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2332101687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2332101687
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.1885321293
Short name	T438
Test name
Test status
Simulation time	64289300 ps
CPU time	13.94 seconds
Started	Jul 06 05:55:38 PM PDT 24
Finished	Jul 06 05:55:53 PM PDT 24
Peak memory	258372 kb
Host	smart-30347978-7748-487c-9981-4f766bbed9fe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885321293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 1885321293
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.114530876
Short name	T462
Test name
Test status
Simulation time	16818400 ps
CPU time	16.2 seconds
Started	Jul 06 05:55:34 PM PDT 24
Finished	Jul 06 05:55:51 PM PDT 24
Peak memory	274872 kb
Host	smart-4f54db69-d19f-40d0-8081-c036834e2bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114530876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.114530876
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.2904358263
Short name	T484
Test name
Test status
Simulation time	34775800 ps
CPU time	22.24 seconds
Started	Jul 06 05:55:33 PM PDT 24
Finished	Jul 06 05:55:56 PM PDT 24
Peak memory	273628 kb
Host	smart-b417cbb4-b1e9-4abe-8aad-1f4b0a530289
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904358263 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2904358263
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3147490106
Short name	T413
Test name
Test status
Simulation time	2477700000 ps
CPU time	97.49 seconds
Started	Jul 06 05:55:28 PM PDT 24
Finished	Jul 06 05:57:05 PM PDT 24
Peak memory	260820 kb
Host	smart-e1cd59d3-c51b-43ee-b823-d803b15c6b1d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147490106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.3147490106
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.1460478399
Short name	T1022
Test name
Test status
Simulation time	115584300 ps
CPU time	133.68 seconds
Started	Jul 06 05:55:29 PM PDT 24
Finished	Jul 06 05:57:43 PM PDT 24
Peak memory	260032 kb
Host	smart-10747202-4124-422d-a826-83d1849cfcd7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460478399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.1460478399
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.943807965
Short name	T847
Test name
Test status
Simulation time	511951600 ps
CPU time	62.11 seconds
Started	Jul 06 05:55:33 PM PDT 24
Finished	Jul 06 05:56:35 PM PDT 24
Peak memory	264652 kb
Host	smart-c92bfb70-b93d-4759-bd83-398bf1824fe3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943807965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.943807965
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.963322969
Short name	T975
Test name
Test status
Simulation time	87788200 ps
CPU time	146.32 seconds
Started	Jul 06 05:55:29 PM PDT 24
Finished	Jul 06 05:57:55 PM PDT 24
Peak memory	278140 kb
Host	smart-4c0e5a3f-e351-4228-9440-7b3fd95df86a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963322969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.963322969
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.2098945849
Short name	T986
Test name
Test status
Simulation time	39503900 ps
CPU time	13.68 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:50:23 PM PDT 24
Peak memory	265188 kb
Host	smart-a72cd666-ce4d-483b-9be9-3d5a4c829f24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098945849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2 098945849
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.2212855027
Short name	T682
Test name
Test status
Simulation time	39706500 ps
CPU time	16.2 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:50:26 PM PDT 24
Peak memory	284404 kb
Host	smart-e5172711-0313-4ab8-a194-463f0c56255f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2212855027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2212855027
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.2765050347
Short name	T81
Test name
Test status
Simulation time	30127500 ps
CPU time	20.33 seconds
Started	Jul 06 05:50:10 PM PDT 24
Finished	Jul 06 05:50:31 PM PDT 24
Peak memory	273880 kb
Host	smart-77955d5d-0b6d-41d7-874d-0ac996ae31ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765050347 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.2765050347
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.293201135
Short name	T722
Test name
Test status
Simulation time	4380834500 ps
CPU time	2108.68 seconds
Started	Jul 06 05:50:04 PM PDT 24
Finished	Jul 06 06:25:13 PM PDT 24
Peak memory	262796 kb
Host	smart-49ef5315-45c3-4dd2-a0b9-876371a44405
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=293201135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.293201135
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.1702250521
Short name	T948
Test name
Test status
Simulation time	1126618100 ps
CPU time	905.56 seconds
Started	Jul 06 05:50:02 PM PDT 24
Finished	Jul 06 06:05:08 PM PDT 24
Peak memory	273456 kb
Host	smart-ba9f5e6b-53de-4296-b0d6-96c99d61d345
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702250521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1702250521
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.1250256440
Short name	T625
Test name
Test status
Simulation time	262730300 ps
CPU time	23.41 seconds
Started	Jul 06 05:50:06 PM PDT 24
Finished	Jul 06 05:50:29 PM PDT 24
Peak memory	263736 kb
Host	smart-c9482272-7d4f-4ec3-ad39-691554e0abf3
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250256440 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1250256440
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1622713957
Short name	T15
Test name
Test status
Simulation time	10015330900 ps
CPU time	99.34 seconds
Started	Jul 06 05:50:10 PM PDT 24
Finished	Jul 06 05:51:50 PM PDT 24
Peak memory	322600 kb
Host	smart-372f0f1d-7dc0-428a-8c56-ceb79afe40d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622713957 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1622713957
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3267701278
Short name	T287
Test name
Test status
Simulation time	26645100 ps
CPU time	13.62 seconds
Started	Jul 06 05:50:08 PM PDT 24
Finished	Jul 06 05:50:22 PM PDT 24
Peak memory	265064 kb
Host	smart-e6b11029-eaa0-4181-9e9e-4361f799e39c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267701278 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3267701278
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.26463119
Short name	T188
Test name
Test status
Simulation time	40120725700 ps
CPU time	848.7 seconds
Started	Jul 06 05:50:02 PM PDT 24
Finished	Jul 06 06:04:11 PM PDT 24
Peak memory	264408 kb
Host	smart-a489501f-b164-42a2-8468-c53e91188f0d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26463119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 5.flash_ctrl_hw_rma_reset.26463119
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1316106144
Short name	T636
Test name
Test status
Simulation time	1655479400 ps
CPU time	75.91 seconds
Started	Jul 06 05:49:59 PM PDT 24
Finished	Jul 06 05:51:16 PM PDT 24
Peak memory	262772 kb
Host	smart-80e8f76d-f4b4-48c5-a02b-6b5205534cfd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316106144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h w_sec_otp.1316106144
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.3882851986
Short name	T741
Test name
Test status
Simulation time	2893424500 ps
CPU time	239.55 seconds
Started	Jul 06 05:50:05 PM PDT 24
Finished	Jul 06 05:54:04 PM PDT 24
Peak memory	291332 kb
Host	smart-57618c62-bd44-4f4f-b8f0-e4cef19249f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882851986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.3882851986
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3253091766
Short name	T149
Test name
Test status
Simulation time	22760174900 ps
CPU time	163.83 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:52:53 PM PDT 24
Peak memory	293032 kb
Host	smart-2f0f2eb9-fcb4-46cf-883f-60749d58ee08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253091766 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3253091766
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.3388836630
Short name	T575
Test name
Test status
Simulation time	9896819600 ps
CPU time	75.09 seconds
Started	Jul 06 05:50:06 PM PDT 24
Finished	Jul 06 05:51:21 PM PDT 24
Peak memory	260068 kb
Host	smart-a0d6fb9b-6c5b-4b4d-a954-1a3bb9847ebf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388836630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_wr.3388836630
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.807406450
Short name	T810
Test name
Test status
Simulation time	96316626200 ps
CPU time	263.38 seconds
Started	Jul 06 05:50:08 PM PDT 24
Finished	Jul 06 05:54:32 PM PDT 24
Peak memory	259956 kb
Host	smart-a019523d-57e6-4b45-a676-c9a70cd33184
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807 406450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.807406450
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.1421742668
Short name	T907
Test name
Test status
Simulation time	2180062500 ps
CPU time	67.3 seconds
Started	Jul 06 05:50:02 PM PDT 24
Finished	Jul 06 05:51:10 PM PDT 24
Peak memory	262660 kb
Host	smart-3effa9c2-0205-498d-b2cb-b6397bfbd251
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421742668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1421742668
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.4132601639
Short name	T512
Test name
Test status
Simulation time	45633900 ps
CPU time	13.56 seconds
Started	Jul 06 05:50:07 PM PDT 24
Finished	Jul 06 05:50:21 PM PDT 24
Peak memory	265000 kb
Host	smart-bc16f831-ae76-4f0f-8a6b-cf3aeb68af88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132601639 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.4132601639
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.87285844
Short name	T578
Test name
Test status
Simulation time	2287778300 ps
CPU time	172.41 seconds
Started	Jul 06 05:50:02 PM PDT 24
Finished	Jul 06 05:52:55 PM PDT 24
Peak memory	265132 kb
Host	smart-f025d6b2-3a69-44de-aa8e-3fed471ff071
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87285844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.87285844
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.1739979569
Short name	T423
Test name
Test status
Simulation time	42327700 ps
CPU time	130.58 seconds
Started	Jul 06 05:50:04 PM PDT 24
Finished	Jul 06 05:52:15 PM PDT 24
Peak memory	260944 kb
Host	smart-805409d9-8faf-4d97-b444-49ea6611d426
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739979569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot p_reset.1739979569
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.1733892958
Short name	T375
Test name
Test status
Simulation time	35258100 ps
CPU time	13.49 seconds
Started	Jul 06 05:50:10 PM PDT 24
Finished	Jul 06 05:50:23 PM PDT 24
Peak memory	265284 kb
Host	smart-123d01b5-1ee5-41dc-a3d3-5d65f2e8e6b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733892958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.1733892958
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.593774860
Short name	T543
Test name
Test status
Simulation time	50539500 ps
CPU time	149.3 seconds
Started	Jul 06 05:50:02 PM PDT 24
Finished	Jul 06 05:52:31 PM PDT 24
Peak memory	270444 kb
Host	smart-96a3b235-282c-4878-9c3b-face6bf34c31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593774860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.593774860
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.2198142524
Short name	T956
Test name
Test status
Simulation time	70438100 ps
CPU time	35.46 seconds
Started	Jul 06 05:50:10 PM PDT 24
Finished	Jul 06 05:50:45 PM PDT 24
Peak memory	275660 kb
Host	smart-bfb24bd7-a709-4aa1-a06f-8cc8e012ae33
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198142524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.2198142524
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.3348602913
Short name	T218
Test name
Test status
Simulation time	2134548000 ps
CPU time	119.83 seconds
Started	Jul 06 05:50:03 PM PDT 24
Finished	Jul 06 05:52:03 PM PDT 24
Peak memory	289308 kb
Host	smart-a8bd3d27-d30f-4f0a-98ae-be77d4571c82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348602913 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.3348602913
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.3542116588
Short name	T255
Test name
Test status
Simulation time	2373380700 ps
CPU time	145.62 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 05:52:39 PM PDT 24
Peak memory	281752 kb
Host	smart-d576bb20-8ab9-4675-8acc-8755bf501a7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3542116588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3542116588
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.1932890084
Short name	T1059
Test name
Test status
Simulation time	1292630000 ps
CPU time	141.51 seconds
Started	Jul 06 05:50:05 PM PDT 24
Finished	Jul 06 05:52:27 PM PDT 24
Peak memory	281828 kb
Host	smart-39f6c8dc-cc21-4ab9-91e4-f139797aa12e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932890084 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.1932890084
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.1959986111
Short name	T860
Test name
Test status
Simulation time	4289913000 ps
CPU time	705.71 seconds
Started	Jul 06 05:50:04 PM PDT 24
Finished	Jul 06 06:01:50 PM PDT 24
Peak memory	317004 kb
Host	smart-b8566055-ee6a-46f4-a7a0-14366519f7f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959986111 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_rw_derr.1959986111
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2470384518
Short name	T913
Test name
Test status
Simulation time	73619900 ps
CPU time	30.87 seconds
Started	Jul 06 05:50:07 PM PDT 24
Finished	Jul 06 05:50:38 PM PDT 24
Peak memory	275680 kb
Host	smart-dae508f0-bd3f-4814-9cb2-661e0f50ce1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470384518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2470384518
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.254013574
Short name	T723
Test name
Test status
Simulation time	27984200 ps
CPU time	31.31 seconds
Started	Jul 06 05:50:08 PM PDT 24
Finished	Jul 06 05:50:40 PM PDT 24
Peak memory	275700 kb
Host	smart-65ee31c2-974d-4226-852a-f25bc7ad33fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254013574 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.254013574
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.3447874214
Short name	T940
Test name
Test status
Simulation time	7934755200 ps
CPU time	525.82 seconds
Started	Jul 06 05:50:06 PM PDT 24
Finished	Jul 06 05:58:52 PM PDT 24
Peak memory	320860 kb
Host	smart-862f42f5-600f-4ed8-aa97-37ae8c19e0db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447874214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s err.3447874214
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.2326383536
Short name	T511
Test name
Test status
Simulation time	92026400 ps
CPU time	122.59 seconds
Started	Jul 06 05:50:00 PM PDT 24
Finished	Jul 06 05:52:03 PM PDT 24
Peak memory	278200 kb
Host	smart-a9ace619-d8fc-4d64-8f91-70b6d866a00e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2326383536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2326383536
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.3799116121
Short name	T730
Test name
Test status
Simulation time	6571275500 ps
CPU time	147.5 seconds
Started	Jul 06 05:50:06 PM PDT 24
Finished	Jul 06 05:52:34 PM PDT 24
Peak memory	259924 kb
Host	smart-4a224664-78be-4984-872b-acdb2f45be6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799116121 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.3799116121
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.933769147
Short name	T604
Test name
Test status
Simulation time	28327800 ps
CPU time	13.53 seconds
Started	Jul 06 05:55:34 PM PDT 24
Finished	Jul 06 05:55:48 PM PDT 24
Peak memory	275020 kb
Host	smart-110c29b0-44fd-48ce-b200-c7edcf871198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933769147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.933769147
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.1601677532
Short name	T749
Test name
Test status
Simulation time	75562100 ps
CPU time	132.37 seconds
Started	Jul 06 05:55:34 PM PDT 24
Finished	Jul 06 05:57:47 PM PDT 24
Peak memory	259984 kb
Host	smart-42ff1ab3-8996-4035-94ae-a53113279b65
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601677532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.1601677532
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.2478256341
Short name	T699
Test name
Test status
Simulation time	17019200 ps
CPU time	15.85 seconds
Started	Jul 06 05:55:36 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	274852 kb
Host	smart-608a39fd-75e5-40b1-8bfd-277d850f247f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478256341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2478256341
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.2722896458
Short name	T805
Test name
Test status
Simulation time	43857400 ps
CPU time	134.97 seconds
Started	Jul 06 05:55:34 PM PDT 24
Finished	Jul 06 05:57:49 PM PDT 24
Peak memory	261128 kb
Host	smart-7a3d8b2e-7cdf-49cf-a45f-16bf13acea86
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722896458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.2722896458
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.3958251007
Short name	T623
Test name
Test status
Simulation time	26248600 ps
CPU time	16.2 seconds
Started	Jul 06 05:55:35 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	275036 kb
Host	smart-fb34c276-5fad-4d58-ac78-6d27c003cf5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958251007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3958251007
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.1739287732
Short name	T659
Test name
Test status
Simulation time	137958400 ps
CPU time	110.63 seconds
Started	Jul 06 05:55:35 PM PDT 24
Finished	Jul 06 05:57:26 PM PDT 24
Peak memory	264976 kb
Host	smart-d13799c9-8e9e-4371-9d84-287e6e86e355
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739287732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.1739287732
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.4200680585
Short name	T1121
Test name
Test status
Simulation time	31115900 ps
CPU time	15.67 seconds
Started	Jul 06 05:55:36 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	284372 kb
Host	smart-a42ace5f-5711-4286-a950-51ef12f7de84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200680585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.4200680585
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.394147143
Short name	T668
Test name
Test status
Simulation time	155512100 ps
CPU time	132.18 seconds
Started	Jul 06 05:55:38 PM PDT 24
Finished	Jul 06 05:57:51 PM PDT 24
Peak memory	261208 kb
Host	smart-9efbaedd-8659-48cc-a145-259284a5abca
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394147143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot p_reset.394147143
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.2413373169
Short name	T126
Test name
Test status
Simulation time	115063600 ps
CPU time	15.94 seconds
Started	Jul 06 05:55:34 PM PDT 24
Finished	Jul 06 05:55:50 PM PDT 24
Peak memory	274852 kb
Host	smart-478f032b-b2b6-4bef-9ec5-c6f2b345cd2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413373169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2413373169
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.1990296986
Short name	T379
Test name
Test status
Simulation time	150379500 ps
CPU time	131.96 seconds
Started	Jul 06 05:55:38 PM PDT 24
Finished	Jul 06 05:57:51 PM PDT 24
Peak memory	265052 kb
Host	smart-16ccfc65-472a-4ec0-ad6c-dbb2b62653cd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990296986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.1990296986
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.2719444900
Short name	T774
Test name
Test status
Simulation time	137872200 ps
CPU time	132.66 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:57:50 PM PDT 24
Peak memory	260128 kb
Host	smart-fd37c448-b9f8-4b55-a880-27b84d59f283
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719444900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.2719444900
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.2012466710
Short name	T666
Test name
Test status
Simulation time	36992600 ps
CPU time	15.6 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:55:53 PM PDT 24
Peak memory	284460 kb
Host	smart-e4c2de6d-af54-41cf-a5c5-081ecf8f81b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012466710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2012466710
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.615705749
Short name	T1026
Test name
Test status
Simulation time	376612400 ps
CPU time	132.04 seconds
Started	Jul 06 05:55:38 PM PDT 24
Finished	Jul 06 05:57:50 PM PDT 24
Peak memory	260284 kb
Host	smart-899562bf-6b17-42f4-b824-4298b2833a67
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615705749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot p_reset.615705749
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.2075716893
Short name	T591
Test name
Test status
Simulation time	14528300 ps
CPU time	13.5 seconds
Started	Jul 06 05:55:38 PM PDT 24
Finished	Jul 06 05:55:52 PM PDT 24
Peak memory	274900 kb
Host	smart-edf59df4-8464-49a4-9aa4-c2eecfa3d2d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075716893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2075716893
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.1334719052
Short name	T73
Test name
Test status
Simulation time	69470100 ps
CPU time	108.88 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:57:26 PM PDT 24
Peak memory	261092 kb
Host	smart-71d3edea-9d23-44bd-b2ff-35526e6ed4ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334719052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o tp_reset.1334719052
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.1112431309
Short name	T678
Test name
Test status
Simulation time	17726400 ps
CPU time	13.16 seconds
Started	Jul 06 05:55:41 PM PDT 24
Finished	Jul 06 05:55:55 PM PDT 24
Peak memory	274956 kb
Host	smart-c12bb755-0cad-418a-bb0b-b6799b0e6c27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112431309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1112431309
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.3905014498
Short name	T449
Test name
Test status
Simulation time	84769700 ps
CPU time	13.43 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:55:50 PM PDT 24
Peak memory	284332 kb
Host	smart-7654dc08-cd54-403a-8b83-c76835367c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905014498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3905014498
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.3911668807
Short name	T755
Test name
Test status
Simulation time	151146800 ps
CPU time	130.4 seconds
Started	Jul 06 05:55:39 PM PDT 24
Finished	Jul 06 05:57:50 PM PDT 24
Peak memory	261232 kb
Host	smart-edbd33eb-fa1f-4610-bf20-cf3ed9f23768
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911668807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.3911668807
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.2769508347
Short name	T675
Test name
Test status
Simulation time	100150100 ps
CPU time	14.03 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 05:50:44 PM PDT 24
Peak memory	265296 kb
Host	smart-6a4ead31-b84a-47ed-a546-c6a8eeca5c45
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769508347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2 769508347
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.2086242320
Short name	T464
Test name
Test status
Simulation time	14319600 ps
CPU time	16.39 seconds
Started	Jul 06 05:50:16 PM PDT 24
Finished	Jul 06 05:50:33 PM PDT 24
Peak memory	274964 kb
Host	smart-2a5e6464-d5da-415d-84d8-3b7e1ade78a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086242320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2086242320
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.2389076391
Short name	T1067
Test name
Test status
Simulation time	37365600 ps
CPU time	20.61 seconds
Started	Jul 06 05:50:16 PM PDT 24
Finished	Jul 06 05:50:37 PM PDT 24
Peak memory	273492 kb
Host	smart-288e08f9-dcc3-4078-9649-48a47dcb04ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389076391 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.2389076391
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.170933030
Short name	T841
Test name
Test status
Simulation time	10947291100 ps
CPU time	2221.25 seconds
Started	Jul 06 05:50:12 PM PDT 24
Finished	Jul 06 06:27:14 PM PDT 24
Peak memory	262816 kb
Host	smart-1a397831-6eb3-47f2-bf79-a1dfc74fa1f1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=170933030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.170933030
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.412920457
Short name	T889
Test name
Test status
Simulation time	1392660900 ps
CPU time	816.29 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 06:03:50 PM PDT 24
Peak memory	270572 kb
Host	smart-7b3143d9-4f7e-426e-91d7-b046e2524dfa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412920457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.412920457
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.2778492619
Short name	T60
Test name
Test status
Simulation time	513229200 ps
CPU time	28.54 seconds
Started	Jul 06 05:50:12 PM PDT 24
Finished	Jul 06 05:50:41 PM PDT 24
Peak memory	262568 kb
Host	smart-9c799881-3438-4c0c-a8bf-0ff66ec53263
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778492619 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2778492619
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3722984039
Short name	T207
Test name
Test status
Simulation time	10012109300 ps
CPU time	129.28 seconds
Started	Jul 06 05:50:27 PM PDT 24
Finished	Jul 06 05:52:37 PM PDT 24
Peak memory	329188 kb
Host	smart-78683ecc-65c9-4cd8-879e-77ef6bf11af5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722984039 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3722984039
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3922867388
Short name	T1023
Test name
Test status
Simulation time	46396800 ps
CPU time	13.45 seconds
Started	Jul 06 05:50:27 PM PDT 24
Finished	Jul 06 05:50:41 PM PDT 24
Peak memory	258604 kb
Host	smart-91dda0fd-acab-4828-99d7-3785afe1f292
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922867388 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3922867388
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2299145639
Short name	T202
Test name
Test status
Simulation time	240218029800 ps
CPU time	941.74 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 06:05:51 PM PDT 24
Peak memory	263732 kb
Host	smart-64658bff-7683-47f0-95b7-fac1b93eaf48
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299145639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_hw_rma_reset.2299145639
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1098591288
Short name	T964
Test name
Test status
Simulation time	4454118100 ps
CPU time	86.94 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:51:36 PM PDT 24
Peak memory	262780 kb
Host	smart-ae5a4df7-65c5-4228-b423-c16d0f957e4f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098591288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.1098591288
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.1994010946
Short name	T37
Test name
Test status
Simulation time	676350200 ps
CPU time	122.89 seconds
Started	Jul 06 05:50:17 PM PDT 24
Finished	Jul 06 05:52:21 PM PDT 24
Peak memory	294164 kb
Host	smart-a52dfcd6-05d4-4daa-93a3-c9773214f998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994010946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_intr_rd.1994010946
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3973599789
Short name	T961
Test name
Test status
Simulation time	11964257300 ps
CPU time	126.13 seconds
Started	Jul 06 05:50:17 PM PDT 24
Finished	Jul 06 05:52:23 PM PDT 24
Peak memory	292548 kb
Host	smart-23f05191-472c-496b-a938-23f032960ddf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973599789 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3973599789
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.2865235582
Short name	T1004
Test name
Test status
Simulation time	10002864000 ps
CPU time	78.45 seconds
Started	Jul 06 05:50:15 PM PDT 24
Finished	Jul 06 05:51:34 PM PDT 24
Peak memory	265240 kb
Host	smart-7a009966-7cc9-4b62-9d35-d05045bf6d60
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865235582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.2865235582
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3088789868
Short name	T932
Test name
Test status
Simulation time	85025809700 ps
CPU time	220.06 seconds
Started	Jul 06 05:50:17 PM PDT 24
Finished	Jul 06 05:53:58 PM PDT 24
Peak memory	265212 kb
Host	smart-4496fc5e-3be3-4f93-b5e2-5bdaec284b65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308 8789868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3088789868
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.3932626149
Short name	T159
Test name
Test status
Simulation time	1988136500 ps
CPU time	58.9 seconds
Started	Jul 06 05:50:14 PM PDT 24
Finished	Jul 06 05:51:13 PM PDT 24
Peak memory	262728 kb
Host	smart-d0f46429-6521-4f33-a72d-74c4d521ceaa
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932626149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3932626149
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.1473289080
Short name	T831
Test name
Test status
Simulation time	31111300 ps
CPU time	13.52 seconds
Started	Jul 06 05:50:30 PM PDT 24
Finished	Jul 06 05:50:44 PM PDT 24
Peak memory	264956 kb
Host	smart-b294880d-5eb4-455d-9d7e-711a76c94230
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473289080 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.1473289080
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.3162500133
Short name	T140
Test name
Test status
Simulation time	34562090600 ps
CPU time	284.57 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 05:54:57 PM PDT 24
Peak memory	274620 kb
Host	smart-82a78d82-3fc4-4bc2-b682-968784f8290a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162500133 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3162500133
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.1465073359
Short name	T622
Test name
Test status
Simulation time	356696100 ps
CPU time	111.31 seconds
Started	Jul 06 05:50:08 PM PDT 24
Finished	Jul 06 05:51:59 PM PDT 24
Peak memory	260040 kb
Host	smart-92cde827-9d2d-4c99-9355-a85fa34b4163
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465073359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.1465073359
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.856125276
Short name	T801
Test name
Test status
Simulation time	3226963300 ps
CPU time	562.94 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:59:32 PM PDT 24
Peak memory	262540 kb
Host	smart-0ccd7bb2-78a2-4994-9a52-e227a5013c40
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=856125276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.856125276
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.3408647442
Short name	T150
Test name
Test status
Simulation time	68075400 ps
CPU time	13.76 seconds
Started	Jul 06 05:50:16 PM PDT 24
Finished	Jul 06 05:50:31 PM PDT 24
Peak memory	259120 kb
Host	smart-2575262b-ab62-4206-bbb7-881d814d58b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408647442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.3408647442
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.1028747780
Short name	T683
Test name
Test status
Simulation time	43684400 ps
CPU time	207.04 seconds
Started	Jul 06 05:50:09 PM PDT 24
Finished	Jul 06 05:53:37 PM PDT 24
Peak memory	281652 kb
Host	smart-b568ee3c-8785-48b5-bbe7-2ea7f16d6208
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028747780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1028747780
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.3410359139
Short name	T1076
Test name
Test status
Simulation time	153801300 ps
CPU time	33.8 seconds
Started	Jul 06 05:50:16 PM PDT 24
Finished	Jul 06 05:50:50 PM PDT 24
Peak memory	268436 kb
Host	smart-e13242c1-48fe-45a1-8060-62e3ee6a5c4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410359139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_re_evict.3410359139
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.3010523915
Short name	T844
Test name
Test status
Simulation time	1710124600 ps
CPU time	110.56 seconds
Started	Jul 06 05:50:11 PM PDT 24
Finished	Jul 06 05:52:02 PM PDT 24
Peak memory	289928 kb
Host	smart-30c9393b-8af8-46df-b274-985ec9950450
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010523915 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.3010523915
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.2764603657
Short name	T760
Test name
Test status
Simulation time	669271700 ps
CPU time	158.78 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 05:52:52 PM PDT 24
Peak memory	283200 kb
Host	smart-c32e0b3f-fa7c-44bd-9f1d-d2334e7b7b84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2764603657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2764603657
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.2459756418
Short name	T743
Test name
Test status
Simulation time	8715605900 ps
CPU time	164.41 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 05:52:58 PM PDT 24
Peak memory	281796 kb
Host	smart-ff36c5cd-f4f2-47dc-baba-46e4b62c3d7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459756418 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.2459756418
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.1542528231
Short name	T845
Test name
Test status
Simulation time	3524054100 ps
CPU time	602.09 seconds
Started	Jul 06 05:50:13 PM PDT 24
Finished	Jul 06 06:00:15 PM PDT 24
Peak memory	314588 kb
Host	smart-75066cf7-9dc6-48e9-965a-8f7520596063
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542528231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.flash_ctrl_rw.1542528231
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.3140931288
Short name	T562
Test name
Test status
Simulation time	17954495400 ps
CPU time	655.54 seconds
Started	Jul 06 05:50:12 PM PDT 24
Finished	Jul 06 06:01:08 PM PDT 24
Peak memory	336888 kb
Host	smart-d40791c8-98fa-4188-a6d2-9f8d772f81c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140931288 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_rw_derr.3140931288
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.4279761573
Short name	T729
Test name
Test status
Simulation time	42765300 ps
CPU time	30.73 seconds
Started	Jul 06 05:50:16 PM PDT 24
Finished	Jul 06 05:50:47 PM PDT 24
Peak memory	275716 kb
Host	smart-986351eb-e698-44b7-975e-9671481f289b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279761573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.4279761573
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3829864753
Short name	T630
Test name
Test status
Simulation time	211264500 ps
CPU time	28.02 seconds
Started	Jul 06 05:50:17 PM PDT 24
Finished	Jul 06 05:50:45 PM PDT 24
Peak memory	275688 kb
Host	smart-4301f42b-2972-46f4-8398-492172dfe6ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829864753 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3829864753
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.1615092520
Short name	T388
Test name
Test status
Simulation time	1357291900 ps
CPU time	66.15 seconds
Started	Jul 06 05:50:15 PM PDT 24
Finished	Jul 06 05:51:22 PM PDT 24
Peak memory	263732 kb
Host	smart-5a471246-c3f5-4e03-b48c-7d008f9b2951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615092520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1615092520
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.3652052338
Short name	T629
Test name
Test status
Simulation time	175165200 ps
CPU time	170.96 seconds
Started	Jul 06 05:50:07 PM PDT 24
Finished	Jul 06 05:52:58 PM PDT 24
Peak memory	279216 kb
Host	smart-a63c9a76-09dc-4603-9137-d5e20f17af05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3652052338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3652052338
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.2757102127
Short name	T796
Test name
Test status
Simulation time	1557972000 ps
CPU time	145.27 seconds
Started	Jul 06 05:50:12 PM PDT 24
Finished	Jul 06 05:52:38 PM PDT 24
Peak memory	265272 kb
Host	smart-bfb95f44-6424-434b-b4bc-8648f5423c8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757102127 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 6.flash_ctrl_wo.2757102127
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.3300766665
Short name	T549
Test name
Test status
Simulation time	149285200 ps
CPU time	15.74 seconds
Started	Jul 06 05:55:41 PM PDT 24
Finished	Jul 06 05:55:57 PM PDT 24
Peak memory	274964 kb
Host	smart-2ef9e3c1-e100-4dd7-bd1d-38dac3ac9092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300766665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3300766665
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.3416742950
Short name	T648
Test name
Test status
Simulation time	141919000 ps
CPU time	109.84 seconds
Started	Jul 06 05:55:39 PM PDT 24
Finished	Jul 06 05:57:29 PM PDT 24
Peak memory	260280 kb
Host	smart-ebfd6fba-819b-4bc0-9389-ae5d73ba5ff8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416742950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.3416742950
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.1599706290
Short name	T430
Test name
Test status
Simulation time	45489000 ps
CPU time	15.87 seconds
Started	Jul 06 05:55:37 PM PDT 24
Finished	Jul 06 05:55:54 PM PDT 24
Peak memory	284460 kb
Host	smart-13bee079-bc62-4ec1-8e0b-1114b8d260fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599706290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1599706290
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.1249857737
Short name	T983
Test name
Test status
Simulation time	214173600 ps
CPU time	131.43 seconds
Started	Jul 06 05:55:41 PM PDT 24
Finished	Jul 06 05:57:53 PM PDT 24
Peak memory	260304 kb
Host	smart-2d0e6156-c304-413a-aaec-26c66bbea3e4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249857737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.1249857737
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.3462105215
Short name	T701
Test name
Test status
Simulation time	42890000 ps
CPU time	16.16 seconds
Started	Jul 06 05:55:40 PM PDT 24
Finished	Jul 06 05:55:56 PM PDT 24
Peak memory	274996 kb
Host	smart-f998adde-a819-42fb-8404-ed70f5e47513
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3462105215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3462105215
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.2829867173
Short name	T384
Test name
Test status
Simulation time	40690500 ps
CPU time	109.16 seconds
Started	Jul 06 05:55:41 PM PDT 24
Finished	Jul 06 05:57:31 PM PDT 24
Peak memory	261172 kb
Host	smart-06a95119-5bae-4681-85b8-e5b5d9e7416b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829867173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.2829867173
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.4046981342
Short name	T492
Test name
Test status
Simulation time	13539200 ps
CPU time	16.19 seconds
Started	Jul 06 05:55:44 PM PDT 24
Finished	Jul 06 05:56:01 PM PDT 24
Peak memory	284368 kb
Host	smart-d2cc411e-2063-48fd-a467-6b6bbd4c1e8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046981342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.4046981342
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.818238509
Short name	T788
Test name
Test status
Simulation time	188724900 ps
CPU time	128.73 seconds
Started	Jul 06 05:55:48 PM PDT 24
Finished	Jul 06 05:57:57 PM PDT 24
Peak memory	260080 kb
Host	smart-b8321556-2850-47f3-892b-2411c3bf19bd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818238509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot p_reset.818238509
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.1781359714
Short name	T1041
Test name
Test status
Simulation time	27282900 ps
CPU time	15.95 seconds
Started	Jul 06 05:55:46 PM PDT 24
Finished	Jul 06 05:56:02 PM PDT 24
Peak memory	274784 kb
Host	smart-32d145fa-1e59-4025-b24a-3b6ac6f774f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781359714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1781359714
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.2868668649
Short name	T746
Test name
Test status
Simulation time	27115500 ps
CPU time	15.96 seconds
Started	Jul 06 05:55:43 PM PDT 24
Finished	Jul 06 05:55:59 PM PDT 24
Peak memory	284240 kb
Host	smart-6c91e76a-91c4-4233-9751-f159ca71d88b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868668649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2868668649
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.3094871518
Short name	T567
Test name
Test status
Simulation time	43212800 ps
CPU time	131.28 seconds
Started	Jul 06 05:55:45 PM PDT 24
Finished	Jul 06 05:57:56 PM PDT 24
Peak memory	262728 kb
Host	smart-95dd47c2-bf94-466a-b7f4-aa6f42b9f063
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094871518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o tp_reset.3094871518
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.1385315834
Short name	T850
Test name
Test status
Simulation time	16897300 ps
CPU time	16.57 seconds
Started	Jul 06 05:55:45 PM PDT 24
Finished	Jul 06 05:56:01 PM PDT 24
Peak memory	284352 kb
Host	smart-9dadc14a-7c0d-473c-9dd2-6917e05b30d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385315834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1385315834
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.806486499
Short name	T540
Test name
Test status
Simulation time	37900400 ps
CPU time	131.31 seconds
Started	Jul 06 05:55:44 PM PDT 24
Finished	Jul 06 05:57:56 PM PDT 24
Peak memory	263988 kb
Host	smart-c5cfdb6e-f3b8-4b38-adb4-f82770d5e1e2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806486499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot p_reset.806486499
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.2047340764
Short name	T688
Test name
Test status
Simulation time	23876200 ps
CPU time	13.28 seconds
Started	Jul 06 05:55:44 PM PDT 24
Finished	Jul 06 05:55:58 PM PDT 24
Peak memory	275016 kb
Host	smart-10db40af-419c-4b48-9727-3e89c79beba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047340764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2047340764
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.2426816807
Short name	T756
Test name
Test status
Simulation time	67759600 ps
CPU time	131.96 seconds
Started	Jul 06 05:55:43 PM PDT 24
Finished	Jul 06 05:57:55 PM PDT 24
Peak memory	259924 kb
Host	smart-57c5128b-25cb-4a7a-a13d-96a57bd406c8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426816807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.2426816807
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.737141534
Short name	T754
Test name
Test status
Simulation time	25042400 ps
CPU time	17.27 seconds
Started	Jul 06 05:55:46 PM PDT 24
Finished	Jul 06 05:56:04 PM PDT 24
Peak memory	274732 kb
Host	smart-83c899db-1e3f-45bb-80fc-1c0e8390a5ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=737141534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.737141534
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.641654567
Short name	T690
Test name
Test status
Simulation time	642561400 ps
CPU time	133.75 seconds
Started	Jul 06 05:55:44 PM PDT 24
Finished	Jul 06 05:57:58 PM PDT 24
Peak memory	260152 kb
Host	smart-5f5527f5-c11b-4a72-af21-fee5a24eaef1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641654567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_ot p_reset.641654567
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.3667291285
Short name	T433
Test name
Test status
Simulation time	15203800 ps
CPU time	16.48 seconds
Started	Jul 06 05:55:48 PM PDT 24
Finished	Jul 06 05:56:05 PM PDT 24
Peak memory	284388 kb
Host	smart-62fe0a52-58d2-408f-b357-5569f8057177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667291285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3667291285
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.151512093
Short name	T459
Test name
Test status
Simulation time	72922300 ps
CPU time	113.1 seconds
Started	Jul 06 05:55:49 PM PDT 24
Finished	Jul 06 05:57:42 PM PDT 24
Peak memory	264864 kb
Host	smart-fbaa7d93-564d-4495-b04d-d29c06ff905f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151512093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot p_reset.151512093
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.1002644829
Short name	T22
Test name
Test status
Simulation time	37485500 ps
CPU time	14.02 seconds
Started	Jul 06 05:50:41 PM PDT 24
Finished	Jul 06 05:50:55 PM PDT 24
Peak memory	258196 kb
Host	smart-2d4288a3-d7b7-4824-9c35-b120c8fdc2c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002644829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1 002644829
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.1325664446
Short name	T440
Test name
Test status
Simulation time	17199700 ps
CPU time	13.55 seconds
Started	Jul 06 05:50:42 PM PDT 24
Finished	Jul 06 05:50:56 PM PDT 24
Peak memory	275044 kb
Host	smart-7560c559-eabb-4add-a2f4-92c7767834ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325664446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.1325664446
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1138352977
Short name	T1021
Test name
Test status
Simulation time	12442700 ps
CPU time	21.94 seconds
Started	Jul 06 05:50:36 PM PDT 24
Finished	Jul 06 05:50:58 PM PDT 24
Peak memory	273584 kb
Host	smart-73b2bba4-2b1a-48a3-9030-6f490b9ae83a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138352977 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1138352977
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.1689478715
Short name	T235
Test name
Test status
Simulation time	20657194800 ps
CPU time	2368.92 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 06:29:58 PM PDT 24
Peak memory	265080 kb
Host	smart-617ae03e-ab01-48e5-8609-74ba04b54307
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1689478715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1689478715
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.3082394496
Short name	T205
Test name
Test status
Simulation time	899317700 ps
CPU time	925.2 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 06:05:54 PM PDT 24
Peak memory	273456 kb
Host	smart-fa5e930c-021e-4f51-b456-f243f652e0dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082394496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3082394496
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.974997809
Short name	T53
Test name
Test status
Simulation time	149901300 ps
CPU time	27.93 seconds
Started	Jul 06 05:50:30 PM PDT 24
Finished	Jul 06 05:50:58 PM PDT 24
Peak memory	263672 kb
Host	smart-6375d3ca-6ca8-4b8c-bb4a-c9538ed94b61
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974997809 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.974997809
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.715651900
Short name	T288
Test name
Test status
Simulation time	10018816800 ps
CPU time	79 seconds
Started	Jul 06 05:50:41 PM PDT 24
Finished	Jul 06 05:52:01 PM PDT 24
Peak memory	276568 kb
Host	smart-39e5c2ec-75f4-413e-9700-4723eb18b59c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715651900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.715651900
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.941235885
Short name	T957
Test name
Test status
Simulation time	131804300 ps
CPU time	13.46 seconds
Started	Jul 06 05:50:41 PM PDT 24
Finished	Jul 06 05:50:55 PM PDT 24
Peak memory	258444 kb
Host	smart-cbdba571-c3ed-43ca-88cf-4f4fdbe4e1e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941235885 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.941235885
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.808660705
Short name	T601
Test name
Test status
Simulation time	160187259100 ps
CPU time	845.19 seconds
Started	Jul 06 05:50:28 PM PDT 24
Finished	Jul 06 06:04:34 PM PDT 24
Peak memory	261012 kb
Host	smart-73b6ec6a-c9b1-43a6-bff0-f093d08197bf
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808660705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.flash_ctrl_hw_rma_reset.808660705
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.4159258125
Short name	T497
Test name
Test status
Simulation time	1929501500 ps
CPU time	49.6 seconds
Started	Jul 06 05:50:30 PM PDT 24
Finished	Jul 06 05:51:20 PM PDT 24
Peak memory	260960 kb
Host	smart-f5324065-a7f1-45ef-98e3-ea36ed9884c0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159258125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.4159258125
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.2181836992
Short name	T330
Test name
Test status
Simulation time	3185963100 ps
CPU time	174.64 seconds
Started	Jul 06 05:50:34 PM PDT 24
Finished	Jul 06 05:53:28 PM PDT 24
Peak memory	292860 kb
Host	smart-c0902e29-8347-4586-a6e9-edf5ae733e2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181836992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.2181836992
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2484909043
Short name	T410
Test name
Test status
Simulation time	8408468900 ps
CPU time	228.58 seconds
Started	Jul 06 05:50:34 PM PDT 24
Finished	Jul 06 05:54:23 PM PDT 24
Peak memory	285048 kb
Host	smart-2ceb44a9-6bfb-48d4-bb3a-40b01e4531d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484909043 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.2484909043
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.2139006549
Short name	T606
Test name
Test status
Simulation time	8411393400 ps
CPU time	73.07 seconds
Started	Jul 06 05:50:34 PM PDT 24
Finished	Jul 06 05:51:47 PM PDT 24
Peak memory	260700 kb
Host	smart-1342006d-3174-450c-87dc-ab5542db848d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139006549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.2139006549
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2198233748
Short name	T896
Test name
Test status
Simulation time	29005324800 ps
CPU time	155.81 seconds
Started	Jul 06 05:50:31 PM PDT 24
Finished	Jul 06 05:53:07 PM PDT 24
Peak memory	265192 kb
Host	smart-9449c37b-e795-47b1-870a-08980c09816e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219 8233748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2198233748
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.219893854
Short name	T154
Test name
Test status
Simulation time	2187405600 ps
CPU time	72.34 seconds
Started	Jul 06 05:50:30 PM PDT 24
Finished	Jul 06 05:51:43 PM PDT 24
Peak memory	263464 kb
Host	smart-e6b020b0-00a8-4b24-9f7d-43edbca38618
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219893854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.219893854
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3538398967
Short name	T709
Test name
Test status
Simulation time	47197600 ps
CPU time	13.68 seconds
Started	Jul 06 05:50:43 PM PDT 24
Finished	Jul 06 05:50:57 PM PDT 24
Peak memory	265076 kb
Host	smart-ad3408e6-da43-4e55-903e-72b042455df5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538398967 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3538398967
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.575156454
Short name	T138
Test name
Test status
Simulation time	92997583800 ps
CPU time	464.36 seconds
Started	Jul 06 05:50:32 PM PDT 24
Finished	Jul 06 05:58:17 PM PDT 24
Peak memory	275332 kb
Host	smart-5043272c-642b-4193-adb4-a58ba171df17
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575156454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.575156454
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.2886202377
Short name	T445
Test name
Test status
Simulation time	36468400 ps
CPU time	130.5 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 05:52:40 PM PDT 24
Peak memory	260044 kb
Host	smart-7a5bb515-c16b-43e4-afa2-701eec82403d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886202377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.2886202377
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.3655049647
Short name	T475
Test name
Test status
Simulation time	30909400 ps
CPU time	70.97 seconds
Started	Jul 06 05:50:32 PM PDT 24
Finished	Jul 06 05:51:43 PM PDT 24
Peak memory	263288 kb
Host	smart-3ed297e0-ed81-4f92-88ea-2bb13c619f67
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3655049647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3655049647
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.627828977
Short name	T1064
Test name
Test status
Simulation time	19619500 ps
CPU time	13.75 seconds
Started	Jul 06 05:50:35 PM PDT 24
Finished	Jul 06 05:50:49 PM PDT 24
Peak memory	265248 kb
Host	smart-e74d4d20-7fd0-4916-95f2-6d2ef85ae53c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627828977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.flash_ctrl_prog_reset.627828977
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.183318904
Short name	T3
Test name
Test status
Simulation time	458787400 ps
CPU time	787.12 seconds
Started	Jul 06 05:50:31 PM PDT 24
Finished	Jul 06 06:03:38 PM PDT 24
Peak memory	285892 kb
Host	smart-b328463f-11af-4b28-9852-257a7738d43a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183318904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.183318904
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.835512560
Short name	T133
Test name
Test status
Simulation time	117129600 ps
CPU time	34.99 seconds
Started	Jul 06 05:50:36 PM PDT 24
Finished	Jul 06 05:51:11 PM PDT 24
Peak memory	268516 kb
Host	smart-6a5e9d09-69d6-4585-9948-366d7c4b1626
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835512560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_re_evict.835512560
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.2156159430
Short name	T57
Test name
Test status
Simulation time	561491800 ps
CPU time	116.59 seconds
Started	Jul 06 05:50:29 PM PDT 24
Finished	Jul 06 05:52:26 PM PDT 24
Peak memory	290480 kb
Host	smart-515c1a88-2806-4e8c-bd70-38b78e5ad697
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156159430 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.2156159430
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.1830047627
Short name	T674
Test name
Test status
Simulation time	613210600 ps
CPU time	133.63 seconds
Started	Jul 06 05:50:28 PM PDT 24
Finished	Jul 06 05:52:42 PM PDT 24
Peak memory	281756 kb
Host	smart-17b3f0e1-cb84-43a6-a003-b5fff91d4c7c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830047627 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1830047627
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.2253010218
Short name	T933
Test name
Test status
Simulation time	5116673900 ps
CPU time	556.68 seconds
Started	Jul 06 05:50:32 PM PDT 24
Finished	Jul 06 05:59:49 PM PDT 24
Peak memory	309832 kb
Host	smart-61fdc3c3-9095-4975-8a8b-95a4ccee97bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253010218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.flash_ctrl_rw.2253010218
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.2925792783
Short name	T777
Test name
Test status
Simulation time	3526634800 ps
CPU time	622.04 seconds
Started	Jul 06 05:50:28 PM PDT 24
Finished	Jul 06 06:00:51 PM PDT 24
Peak memory	326460 kb
Host	smart-11d0ec97-ce0c-4c1d-b7db-90c7a7b3b327
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925792783 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.2925792783
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.1220133941
Short name	T347
Test name
Test status
Simulation time	109311100 ps
CPU time	32.08 seconds
Started	Jul 06 05:50:34 PM PDT 24
Finished	Jul 06 05:51:07 PM PDT 24
Peak memory	268480 kb
Host	smart-ffc89a89-d66c-432a-9dd9-f9f671f7bad7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220133941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.1220133941
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.1627482003
Short name	T283
Test name
Test status
Simulation time	33328451700 ps
CPU time	653.03 seconds
Started	Jul 06 05:50:28 PM PDT 24
Finished	Jul 06 06:01:22 PM PDT 24
Peak memory	312696 kb
Host	smart-56409006-a3a6-489e-8396-2a3d1f3a08e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627482003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s err.1627482003
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.3296021822
Short name	T909
Test name
Test status
Simulation time	23540900 ps
CPU time	124.91 seconds
Started	Jul 06 05:50:32 PM PDT 24
Finished	Jul 06 05:52:38 PM PDT 24
Peak memory	277568 kb
Host	smart-b94eec95-7df8-446b-97ee-c44c9455b9e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296021822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3296021822
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.1541743047
Short name	T1024
Test name
Test status
Simulation time	8889326300 ps
CPU time	157.53 seconds
Started	Jul 06 05:50:28 PM PDT 24
Finished	Jul 06 05:53:06 PM PDT 24
Peak memory	260048 kb
Host	smart-901f95bc-04fa-4b8f-b9f5-e400541ce9e3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541743047 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.1541743047
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.4033926484
Short name	T707
Test name
Test status
Simulation time	32430900 ps
CPU time	13.28 seconds
Started	Jul 06 05:55:55 PM PDT 24
Finished	Jul 06 05:56:08 PM PDT 24
Peak memory	275036 kb
Host	smart-3b515eb3-5b24-4edd-92c2-7fb606d22374
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033926484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4033926484
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.1226329461
Short name	T1030
Test name
Test status
Simulation time	71388000 ps
CPU time	131.78 seconds
Started	Jul 06 05:55:54 PM PDT 24
Finished	Jul 06 05:58:07 PM PDT 24
Peak memory	265020 kb
Host	smart-33d200fd-95a5-43b8-a7f4-5a25c150f860
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226329461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o tp_reset.1226329461
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.3011578907
Short name	T1060
Test name
Test status
Simulation time	15107300 ps
CPU time	15.71 seconds
Started	Jul 06 05:55:52 PM PDT 24
Finished	Jul 06 05:56:09 PM PDT 24
Peak memory	274948 kb
Host	smart-240d9b09-bb63-49af-9425-fe0d0ed0a2a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011578907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3011578907
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.3901438165
Short name	T1010
Test name
Test status
Simulation time	273870800 ps
CPU time	134.37 seconds
Started	Jul 06 05:55:49 PM PDT 24
Finished	Jul 06 05:58:03 PM PDT 24
Peak memory	265048 kb
Host	smart-95343b06-0bee-4b58-99bf-ed143952f940
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901438165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.3901438165
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.4005826718
Short name	T1088
Test name
Test status
Simulation time	27826200 ps
CPU time	16.12 seconds
Started	Jul 06 05:55:50 PM PDT 24
Finished	Jul 06 05:56:06 PM PDT 24
Peak memory	274904 kb
Host	smart-68f12895-64a6-4a7c-bb64-d7737755aaa5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005826718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.4005826718
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.3930825850
Short name	T196
Test name
Test status
Simulation time	151165700 ps
CPU time	127.97 seconds
Started	Jul 06 05:55:49 PM PDT 24
Finished	Jul 06 05:57:57 PM PDT 24
Peak memory	259920 kb
Host	smart-ee37250f-c69f-4cf4-b3b7-a054fc002e06
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930825850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.3930825850
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.1664526821
Short name	T558
Test name
Test status
Simulation time	27228300 ps
CPU time	15.98 seconds
Started	Jul 06 05:55:49 PM PDT 24
Finished	Jul 06 05:56:05 PM PDT 24
Peak memory	274792 kb
Host	smart-1f95328a-d441-4a38-b747-f84a3cfbc89d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664526821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1664526821
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.1926548498
Short name	T984
Test name
Test status
Simulation time	403684100 ps
CPU time	111.83 seconds
Started	Jul 06 05:55:54 PM PDT 24
Finished	Jul 06 05:57:46 PM PDT 24
Peak memory	260060 kb
Host	smart-dc811c70-0432-4ffe-ba83-d962f46f3635
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926548498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.1926548498
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.2735638671
Short name	T1122
Test name
Test status
Simulation time	28239400 ps
CPU time	16.01 seconds
Started	Jul 06 05:55:50 PM PDT 24
Finished	Jul 06 05:56:06 PM PDT 24
Peak memory	274884 kb
Host	smart-521367d3-f3e9-406b-a53c-19fee797ff40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735638671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2735638671
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.3355883133
Short name	T951
Test name
Test status
Simulation time	41853100 ps
CPU time	128.48 seconds
Started	Jul 06 05:55:49 PM PDT 24
Finished	Jul 06 05:57:58 PM PDT 24
Peak memory	261100 kb
Host	smart-e147d8b8-18a9-46ef-bf8e-352f92ee5e19
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355883133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.3355883133
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.4094972398
Short name	T963
Test name
Test status
Simulation time	20583000 ps
CPU time	15.7 seconds
Started	Jul 06 05:55:52 PM PDT 24
Finished	Jul 06 05:56:09 PM PDT 24
Peak memory	274992 kb
Host	smart-71af125d-e4c7-40c9-a354-279735c738f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094972398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.4094972398
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.961783665
Short name	T600
Test name
Test status
Simulation time	55452900 ps
CPU time	109.84 seconds
Started	Jul 06 05:55:54 PM PDT 24
Finished	Jul 06 05:57:44 PM PDT 24
Peak memory	260008 kb
Host	smart-c182d35c-3cf9-43f6-a3ad-2d4df15d3220
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961783665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot p_reset.961783665
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.3322892963
Short name	T644
Test name
Test status
Simulation time	59299100 ps
CPU time	16.09 seconds
Started	Jul 06 05:55:55 PM PDT 24
Finished	Jul 06 05:56:12 PM PDT 24
Peak memory	274884 kb
Host	smart-8839ace8-0b14-4191-a702-fcd421f7812a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322892963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3322892963
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.375704471
Short name	T899
Test name
Test status
Simulation time	239086700 ps
CPU time	109.72 seconds
Started	Jul 06 05:55:50 PM PDT 24
Finished	Jul 06 05:57:40 PM PDT 24
Peak memory	260252 kb
Host	smart-d1084a15-2ac8-4f76-9e05-c8cd057cfcae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375704471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot p_reset.375704471
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.2430865673
Short name	T453
Test name
Test status
Simulation time	22891700 ps
CPU time	15.97 seconds
Started	Jul 06 05:55:52 PM PDT 24
Finished	Jul 06 05:56:09 PM PDT 24
Peak memory	274796 kb
Host	smart-444be23c-3c74-4b34-8a4b-5f5c69ebe6c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2430865673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2430865673
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.1714272454
Short name	T422
Test name
Test status
Simulation time	145687800 ps
CPU time	134.49 seconds
Started	Jul 06 05:55:52 PM PDT 24
Finished	Jul 06 05:58:08 PM PDT 24
Peak memory	261164 kb
Host	smart-24a9ae10-499e-4d99-ae9b-357089d64816
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714272454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.1714272454
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.2031615384
Short name	T1074
Test name
Test status
Simulation time	22467400 ps
CPU time	16.27 seconds
Started	Jul 06 05:55:53 PM PDT 24
Finished	Jul 06 05:56:10 PM PDT 24
Peak memory	274736 kb
Host	smart-010d41b0-ec5c-486f-b8c7-92c0c1fa1d9c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031615384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2031615384
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.3511483964
Short name	T1072
Test name
Test status
Simulation time	81248900 ps
CPU time	111.32 seconds
Started	Jul 06 05:55:53 PM PDT 24
Finished	Jul 06 05:57:45 PM PDT 24
Peak memory	260008 kb
Host	smart-6dda2f1f-6743-4cef-9812-d607b6be85aa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511483964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o tp_reset.3511483964
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.3367788955
Short name	T1040
Test name
Test status
Simulation time	53961500 ps
CPU time	13.55 seconds
Started	Jul 06 05:55:53 PM PDT 24
Finished	Jul 06 05:56:08 PM PDT 24
Peak memory	284288 kb
Host	smart-0cf47137-3c25-48eb-9c18-42e81587770f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367788955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3367788955
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.2973911370
Short name	T880
Test name
Test status
Simulation time	42801700 ps
CPU time	132.38 seconds
Started	Jul 06 05:55:53 PM PDT 24
Finished	Jul 06 05:58:06 PM PDT 24
Peak memory	260172 kb
Host	smart-5fb75a40-c405-47a5-a972-85b445a7ce65
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973911370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.2973911370
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.3426403191
Short name	T442
Test name
Test status
Simulation time	101085800 ps
CPU time	13.67 seconds
Started	Jul 06 05:50:57 PM PDT 24
Finished	Jul 06 05:51:11 PM PDT 24
Peak memory	258256 kb
Host	smart-e7d7c92a-4187-48c8-b904-bdb115cec21b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426403191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3 426403191
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.819429776
Short name	T621
Test name
Test status
Simulation time	15217300 ps
CPU time	16.15 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:51:12 PM PDT 24
Peak memory	274868 kb
Host	smart-6fae2e75-3375-4666-8f35-76f5563aa480
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819429776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.819429776
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.2493322362
Short name	T563
Test name
Test status
Simulation time	72639000 ps
CPU time	21.02 seconds
Started	Jul 06 05:50:54 PM PDT 24
Finished	Jul 06 05:51:16 PM PDT 24
Peak memory	273508 kb
Host	smart-d4f42439-f913-4890-9aa4-6c78104ff31e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493322362 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.2493322362
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.2221128694
Short name	T142
Test name
Test status
Simulation time	33675784800 ps
CPU time	2313.2 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 06:29:20 PM PDT 24
Peak memory	264160 kb
Host	smart-0cfcfa66-0b4a-48d8-afd8-c82b9af79668
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2221128694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.2221128694
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.982197611
Short name	T607
Test name
Test status
Simulation time	3183259000 ps
CPU time	798.29 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 06:04:05 PM PDT 24
Peak memory	273480 kb
Host	smart-ce0aa068-78b8-4bbc-a3ce-0c70c71c7f1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982197611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.982197611
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.2069349138
Short name	T988
Test name
Test status
Simulation time	312108500 ps
CPU time	24.77 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 05:51:11 PM PDT 24
Peak memory	263664 kb
Host	smart-f39399ff-ca14-47ba-9a03-ba9bf1675b3d
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069349138 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2069349138
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2534137337
Short name	T840
Test name
Test status
Simulation time	10034258400 ps
CPU time	57.47 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:51:53 PM PDT 24
Peak memory	290364 kb
Host	smart-fb197fcc-1cfb-469d-b915-044d242d6dbc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534137337 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2534137337
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3623415335
Short name	T797
Test name
Test status
Simulation time	32219800 ps
CPU time	13.48 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:51:09 PM PDT 24
Peak memory	258540 kb
Host	smart-7d49b037-4176-4ecf-97a3-b45302890c5c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623415335 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3623415335
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1599984084
Short name	T380
Test name
Test status
Simulation time	160169612100 ps
CPU time	945.47 seconds
Started	Jul 06 05:50:45 PM PDT 24
Finished	Jul 06 06:06:31 PM PDT 24
Peak memory	264896 kb
Host	smart-763e40b3-4947-4bea-a0da-ef1f08918046
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599984084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.1599984084
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.708680451
Short name	T583
Test name
Test status
Simulation time	7371927600 ps
CPU time	78.37 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 05:52:04 PM PDT 24
Peak memory	260632 kb
Host	smart-c09a0ad7-f853-4713-ace4-c43712dbf3d2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708680451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw _sec_otp.708680451
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.531638764
Short name	T225
Test name
Test status
Simulation time	1531918600 ps
CPU time	137.6 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:53:09 PM PDT 24
Peak memory	293912 kb
Host	smart-e9463e70-fe10-437b-954d-73c3163597ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531638764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_intr_rd.531638764
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2291474164
Short name	T849
Test name
Test status
Simulation time	21153789100 ps
CPU time	149.42 seconds
Started	Jul 06 05:50:50 PM PDT 24
Finished	Jul 06 05:53:20 PM PDT 24
Peak memory	292760 kb
Host	smart-13764dd9-b4d0-4654-8e8d-f1f12c1a9df9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291474164 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2291474164
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.992476753
Short name	T773
Test name
Test status
Simulation time	4315033500 ps
CPU time	65.47 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:51:57 PM PDT 24
Peak memory	260316 kb
Host	smart-937676b6-687b-4f07-97dd-32c95ea811dd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992476753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.flash_ctrl_intr_wr.992476753
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.1042327840
Short name	T965
Test name
Test status
Simulation time	3828831500 ps
CPU time	66.01 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 05:51:52 PM PDT 24
Peak memory	263528 kb
Host	smart-d1d4ff1e-91fa-4a3c-bb2a-4646e698020f
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042327840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1042327840
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.462316270
Short name	T1032
Test name
Test status
Simulation time	15318400 ps
CPU time	13.64 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:51:09 PM PDT 24
Peak memory	260872 kb
Host	smart-38df6446-b57f-4acb-b452-ca7eca614a13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462316270 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.462316270
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.4065404165
Short name	T748
Test name
Test status
Simulation time	7144658600 ps
CPU time	556.74 seconds
Started	Jul 06 05:50:47 PM PDT 24
Finished	Jul 06 06:00:04 PM PDT 24
Peak memory	274444 kb
Host	smart-aa743f43-a115-4520-8887-da11db50c32f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065404165 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.4065404165
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.1739288958
Short name	T538
Test name
Test status
Simulation time	69935800 ps
CPU time	130.59 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 05:52:57 PM PDT 24
Peak memory	260048 kb
Host	smart-06d501d8-5e7c-416c-88dd-73cc032a3d92
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739288958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.1739288958
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.2847940158
Short name	T894
Test name
Test status
Simulation time	58601000 ps
CPU time	109.68 seconds
Started	Jul 06 05:50:41 PM PDT 24
Finished	Jul 06 05:52:31 PM PDT 24
Peak memory	263280 kb
Host	smart-f28cad8a-92f4-499d-a304-1aaa9e661255
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2847940158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2847940158
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.4099438515
Short name	T838
Test name
Test status
Simulation time	36253200 ps
CPU time	13.8 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:51:05 PM PDT 24
Peak memory	258992 kb
Host	smart-a3701f83-2015-4af3-b4ca-3f22af85aa92
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099438515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.4099438515
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.1825387017
Short name	T152
Test name
Test status
Simulation time	15875111500 ps
CPU time	659 seconds
Started	Jul 06 05:50:43 PM PDT 24
Finished	Jul 06 06:01:43 PM PDT 24
Peak memory	285204 kb
Host	smart-b065dbbb-8776-4490-b749-4529ba55d001
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825387017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1825387017
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.87758816
Short name	T161
Test name
Test status
Simulation time	62973300 ps
CPU time	33.94 seconds
Started	Jul 06 05:50:50 PM PDT 24
Finished	Jul 06 05:51:24 PM PDT 24
Peak memory	275628 kb
Host	smart-efe8e784-8314-4a21-9625-ad532f27b5fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87758816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_re_evict.87758816
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.1810904090
Short name	T64
Test name
Test status
Simulation time	496225300 ps
CPU time	122.41 seconds
Started	Jul 06 05:50:45 PM PDT 24
Finished	Jul 06 05:52:48 PM PDT 24
Peak memory	281840 kb
Host	smart-88af0aa8-29ea-4f8c-b653-5a1c6f68a380
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810904090 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.1810904090
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.3286899183
Short name	T256
Test name
Test status
Simulation time	2946141400 ps
CPU time	201.71 seconds
Started	Jul 06 05:50:50 PM PDT 24
Finished	Jul 06 05:54:12 PM PDT 24
Peak memory	283904 kb
Host	smart-17277f9b-7908-406b-8546-c381c14a009b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3286899183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.3286899183
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.3002635168
Short name	T102
Test name
Test status
Simulation time	708591000 ps
CPU time	152.48 seconds
Started	Jul 06 05:50:50 PM PDT 24
Finished	Jul 06 05:53:23 PM PDT 24
Peak memory	281804 kb
Host	smart-c3a5b908-cdfc-4dcb-8dd7-017cf9e2969b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002635168 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3002635168
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.1559719717
Short name	T219
Test name
Test status
Simulation time	16584148200 ps
CPU time	607.89 seconds
Started	Jul 06 05:50:46 PM PDT 24
Finished	Jul 06 06:00:54 PM PDT 24
Peak memory	309560 kb
Host	smart-a23a43d5-b19c-4cff-b21b-f2842c3104e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559719717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.flash_ctrl_rw.1559719717
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.2511173728
Short name	T814
Test name
Test status
Simulation time	17357652200 ps
CPU time	603.55 seconds
Started	Jul 06 05:50:50 PM PDT 24
Finished	Jul 06 06:00:54 PM PDT 24
Peak memory	341780 kb
Host	smart-994406d2-70f6-4bc9-a136-f66f4e52396c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511173728 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.2511173728
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.764836921
Short name	T466
Test name
Test status
Simulation time	34290400 ps
CPU time	30.99 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:51:22 PM PDT 24
Peak memory	268524 kb
Host	smart-c927f638-80a8-44d6-bfc0-eef690447a5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764836921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_rw_evict.764836921
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.4232482953
Short name	T353
Test name
Test status
Simulation time	29334900 ps
CPU time	30.69 seconds
Started	Jul 06 05:50:51 PM PDT 24
Finished	Jul 06 05:51:22 PM PDT 24
Peak memory	268532 kb
Host	smart-90638f53-d508-44f3-aa1f-658d7ee324ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232482953 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.4232482953
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.470179623
Short name	T770
Test name
Test status
Simulation time	4441254000 ps
CPU time	631.59 seconds
Started	Jul 06 05:50:52 PM PDT 24
Finished	Jul 06 06:01:24 PM PDT 24
Peak memory	320780 kb
Host	smart-3f75e566-3176-4310-b96a-028b9bb47b1d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470179623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_se rr.470179623
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.2127169821
Short name	T941
Test name
Test status
Simulation time	1672315800 ps
CPU time	65.55 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:52:01 PM PDT 24
Peak memory	259840 kb
Host	smart-67548a37-c381-4950-b599-db7f6056a965
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127169821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2127169821
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.1595522822
Short name	T848
Test name
Test status
Simulation time	113734000 ps
CPU time	169.4 seconds
Started	Jul 06 05:50:42 PM PDT 24
Finished	Jul 06 05:53:32 PM PDT 24
Peak memory	277180 kb
Host	smart-36e0f9d3-baa5-4daa-ac02-3834284e2608
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595522822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1595522822
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.3934919110
Short name	T128
Test name
Test status
Simulation time	4581323100 ps
CPU time	170.03 seconds
Started	Jul 06 05:50:45 PM PDT 24
Finished	Jul 06 05:53:36 PM PDT 24
Peak memory	260048 kb
Host	smart-9ac79aa3-3262-4c25-8a78-5e66da6b4a37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934919110 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.3934919110
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.1702309639
Short name	T898
Test name
Test status
Simulation time	29904800 ps
CPU time	14.21 seconds
Started	Jul 06 05:51:15 PM PDT 24
Finished	Jul 06 05:51:30 PM PDT 24
Peak memory	258124 kb
Host	smart-cbbbf6f7-4916-49c9-aed6-553c8158816a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702309639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1 702309639
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.3065204429
Short name	T458
Test name
Test status
Simulation time	13640400 ps
CPU time	16.25 seconds
Started	Jul 06 05:51:16 PM PDT 24
Finished	Jul 06 05:51:32 PM PDT 24
Peak memory	274916 kb
Host	smart-792c6e4e-7ed0-42e8-873a-bb72fe369f5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065204429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3065204429
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.2984394112
Short name	T109
Test name
Test status
Simulation time	20974800 ps
CPU time	22.22 seconds
Started	Jul 06 05:51:09 PM PDT 24
Finished	Jul 06 05:51:31 PM PDT 24
Peak memory	273576 kb
Host	smart-331d562c-6688-42b2-8a48-e0809d6ce958
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984394112 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.2984394112
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.337864947
Short name	T1042
Test name
Test status
Simulation time	5434106200 ps
CPU time	2204 seconds
Started	Jul 06 05:51:00 PM PDT 24
Finished	Jul 06 06:27:45 PM PDT 24
Peak memory	264708 kb
Host	smart-385387c4-80c1-47d5-bcb1-425ebbde762b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=337864947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.337864947
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.1475817853
Short name	T798
Test name
Test status
Simulation time	1344286600 ps
CPU time	876.1 seconds
Started	Jul 06 05:51:01 PM PDT 24
Finished	Jul 06 06:05:38 PM PDT 24
Peak memory	272956 kb
Host	smart-43e53e08-9c49-4e97-8674-1013b2a9bdf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475817853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1475817853
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.1417763932
Short name	T7
Test name
Test status
Simulation time	937360100 ps
CPU time	19.92 seconds
Started	Jul 06 05:51:01 PM PDT 24
Finished	Jul 06 05:51:21 PM PDT 24
Peak memory	263592 kb
Host	smart-4d9681ee-1786-4245-8985-986daf89c293
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417763932 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.1417763932
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3767789018
Short name	T598
Test name
Test status
Simulation time	10012244500 ps
CPU time	115.53 seconds
Started	Jul 06 05:51:16 PM PDT 24
Finished	Jul 06 05:53:12 PM PDT 24
Peak memory	333728 kb
Host	smart-1a66b5c9-63fc-4b7e-831d-06a142adf27f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767789018 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3767789018
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2450161977
Short name	T1124
Test name
Test status
Simulation time	85111800 ps
CPU time	13.33 seconds
Started	Jul 06 05:51:16 PM PDT 24
Finished	Jul 06 05:51:29 PM PDT 24
Peak memory	265508 kb
Host	smart-23aaabf1-d345-4bb1-b38b-25ba421e0936
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450161977 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2450161977
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2746967034
Short name	T902
Test name
Test status
Simulation time	350255708900 ps
CPU time	1072.38 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 06:08:47 PM PDT 24
Peak memory	261032 kb
Host	smart-24eb5901-754a-491b-8318-f2ff5a9cd51e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746967034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.2746967034
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.650878080
Short name	T467
Test name
Test status
Simulation time	11600876100 ps
CPU time	229.35 seconds
Started	Jul 06 05:50:57 PM PDT 24
Finished	Jul 06 05:54:47 PM PDT 24
Peak memory	262820 kb
Host	smart-c82c1db9-0fcb-4380-9271-fb205682ff10
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650878080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw _sec_otp.650878080
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.378884610
Short name	T953
Test name
Test status
Simulation time	5722321200 ps
CPU time	233.77 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 05:54:59 PM PDT 24
Peak memory	291536 kb
Host	smart-2a273792-15da-4a7b-b1de-83b3d256df90
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378884610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash _ctrl_intr_rd.378884610
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.4103471795
Short name	T95
Test name
Test status
Simulation time	11828436500 ps
CPU time	291.37 seconds
Started	Jul 06 05:51:09 PM PDT 24
Finished	Jul 06 05:56:01 PM PDT 24
Peak memory	294284 kb
Host	smart-2cdad36a-7de3-42dc-b01c-62d1d8ad2538
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103471795 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.4103471795
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.4204777443
Short name	T32
Test name
Test status
Simulation time	15168096600 ps
CPU time	68.31 seconds
Started	Jul 06 05:51:06 PM PDT 24
Finished	Jul 06 05:52:14 PM PDT 24
Peak memory	261632 kb
Host	smart-c2c2fc6d-b9ce-40c0-b722-da38363bf234
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204777443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.4204777443
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3213413870
Short name	T706
Test name
Test status
Simulation time	37442834200 ps
CPU time	159.58 seconds
Started	Jul 06 05:51:09 PM PDT 24
Finished	Jul 06 05:53:49 PM PDT 24
Peak memory	260620 kb
Host	smart-ef4d0223-89b7-4835-bfe5-6fc05dd9528e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321 3413870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3213413870
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.653068931
Short name	T736
Test name
Test status
Simulation time	1688082400 ps
CPU time	61.16 seconds
Started	Jul 06 05:50:58 PM PDT 24
Finished	Jul 06 05:52:00 PM PDT 24
Peak memory	263276 kb
Host	smart-5ecedfc1-5836-4843-afdb-4e8bcd350e13
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653068931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.653068931
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1955845357
Short name	T528
Test name
Test status
Simulation time	15709200 ps
CPU time	13.79 seconds
Started	Jul 06 05:51:15 PM PDT 24
Finished	Jul 06 05:51:29 PM PDT 24
Peak memory	264964 kb
Host	smart-d9e176f4-9062-49a6-bbee-fbe6e31212c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955845357 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1955845357
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.3837392301
Short name	T156
Test name
Test status
Simulation time	13390499100 ps
CPU time	221.36 seconds
Started	Jul 06 05:51:00 PM PDT 24
Finished	Jul 06 05:54:42 PM PDT 24
Peak memory	274724 kb
Host	smart-cd54c0a2-e89e-4938-ba55-366af4c8ab66
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837392301 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.3837392301
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.523934429
Short name	T595
Test name
Test status
Simulation time	68470000 ps
CPU time	112.59 seconds
Started	Jul 06 05:50:56 PM PDT 24
Finished	Jul 06 05:52:49 PM PDT 24
Peak memory	265156 kb
Host	smart-ff3900ef-2757-4dac-9471-c26a77ef8362
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523934429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp _reset.523934429
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.437965046
Short name	T131
Test name
Test status
Simulation time	1466449300 ps
CPU time	372.82 seconds
Started	Jul 06 05:50:54 PM PDT 24
Finished	Jul 06 05:57:07 PM PDT 24
Peak memory	263160 kb
Host	smart-e59b87e6-0e73-45a4-bd4c-43fbf38a2e7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=437965046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.437965046
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.2102821755
Short name	T479
Test name
Test status
Simulation time	57710900 ps
CPU time	13.92 seconds
Started	Jul 06 05:51:10 PM PDT 24
Finished	Jul 06 05:51:24 PM PDT 24
Peak memory	265324 kb
Host	smart-5a4a97e5-760b-44cb-806e-23f7fef325c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102821755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.2102821755
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.1696084408
Short name	T436
Test name
Test status
Simulation time	38332400 ps
CPU time	171.86 seconds
Started	Jul 06 05:50:55 PM PDT 24
Finished	Jul 06 05:53:48 PM PDT 24
Peak memory	279568 kb
Host	smart-02dd656a-add4-4bf3-94a8-68f3553576f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696084408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1696084408
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.392092994
Short name	T344
Test name
Test status
Simulation time	307814600 ps
CPU time	34.9 seconds
Started	Jul 06 05:51:10 PM PDT 24
Finished	Jul 06 05:51:45 PM PDT 24
Peak memory	276740 kb
Host	smart-ff1435a4-5f98-4973-b6e8-8e9bded81bf7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392092994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_re_evict.392092994
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.3347702735
Short name	T992
Test name
Test status
Simulation time	546026400 ps
CPU time	127.92 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 05:53:13 PM PDT 24
Peak memory	281692 kb
Host	smart-5a32c4d5-827a-4f3e-b01b-e2d25a794a96
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347702735 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.3347702735
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.4190819616
Short name	T545
Test name
Test status
Simulation time	649800300 ps
CPU time	140.44 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 05:53:26 PM PDT 24
Peak memory	281784 kb
Host	smart-33c83ae5-2966-4404-824f-607046e71e8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4190819616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.4190819616
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.3721807712
Short name	T1108
Test name
Test status
Simulation time	2755414500 ps
CPU time	163.11 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 05:53:48 PM PDT 24
Peak memory	281796 kb
Host	smart-34720407-35d9-49e5-b0a8-715c07da9816
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721807712 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3721807712
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.4111316201
Short name	T212
Test name
Test status
Simulation time	3437422400 ps
CPU time	590.37 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 06:00:56 PM PDT 24
Peak memory	309608 kb
Host	smart-68cdaba9-f495-4f44-a9a2-6297b10de49c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111316201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.4111316201
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.3234618513
Short name	T548
Test name
Test status
Simulation time	69533300 ps
CPU time	31.44 seconds
Started	Jul 06 05:51:11 PM PDT 24
Finished	Jul 06 05:51:43 PM PDT 24
Peak memory	268512 kb
Host	smart-d08454bf-05c9-49f3-9e51-dcfee1a6c257
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234618513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.3234618513
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1090865038
Short name	T769
Test name
Test status
Simulation time	98071700 ps
CPU time	31.26 seconds
Started	Jul 06 05:51:13 PM PDT 24
Finished	Jul 06 05:51:45 PM PDT 24
Peak memory	275704 kb
Host	smart-1f32b9a6-aad9-40fd-bbbf-96c4b7c136f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090865038 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1090865038
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.393851332
Short name	T911
Test name
Test status
Simulation time	40141887200 ps
CPU time	694.62 seconds
Started	Jul 06 05:51:05 PM PDT 24
Finished	Jul 06 06:02:41 PM PDT 24
Peak memory	312972 kb
Host	smart-16ee7d7d-f22a-46ac-af94-38b34219c12d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393851332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se rr.393851332
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.1505188910
Short name	T208
Test name
Test status
Simulation time	6599808300 ps
CPU time	83.5 seconds
Started	Jul 06 05:51:16 PM PDT 24
Finished	Jul 06 05:52:39 PM PDT 24
Peak memory	263736 kb
Host	smart-b9497d01-35c4-45f9-949b-6fa0e9dba2b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505188910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1505188910
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.3653179633
Short name	T421
Test name
Test status
Simulation time	25582100 ps
CPU time	73.63 seconds
Started	Jul 06 05:50:57 PM PDT 24
Finished	Jul 06 05:52:11 PM PDT 24
Peak memory	275676 kb
Host	smart-5a472493-9d26-4959-9b89-f37ddbc642af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653179633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3653179633
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.3887344963
Short name	T495
Test name
Test status
Simulation time	2284179700 ps
CPU time	202.14 seconds
Started	Jul 06 05:51:00 PM PDT 24
Finished	Jul 06 05:54:22 PM PDT 24
Peak memory	261056 kb
Host	smart-e5883681-135a-404a-8df6-25672092d58a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887344963 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.3887344963
Directory	/workspace/9.flash_ctrl_wo/latest

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