SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.22 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 91.67 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
91.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 2 | 12 | 91.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 80139 | 0 | T68 | 4101 | T69 | 495 | T70 | 4101 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 79932 | 1 | T68 | 4101 | T69 | 495 | T70 | 4101 | |||
values[1] | 21 | 1 | T234 | 1 | T241 | 1 | T352 | 2 | |||
values[3] | 104 | 1 | T99 | 2 | T198 | 4 | T234 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 79927 | 1 | T68 | 4101 | T69 | 495 | T70 | 4101 | |||
values[1] | 20 | 1 | T234 | 3 | T240 | 2 | T352 | 1 | |||
values[2] | 9 | 1 | T234 | 1 | T272 | 1 | T255 | 1 | |||
values[3] | 107 | 1 | T99 | 6 | T198 | 7 | T234 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 79829 | 1 | T68 | 4101 | T69 | 495 | T70 | 4101 | |||
auto[TlIntgErrCmd] | 98 | 1 | T99 | 2 | T198 | 2 | T234 | 3 | |||
auto[TlIntgErrData] | 103 | 1 | T99 | 6 | T198 | 4 | T234 | 6 | |||
auto[TlIntgErrBoth] | 109 | 1 | T99 | 2 | T198 | 4 | T234 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 25331844 | 1 | T1 | 278 | T2 | 166742 | T3 | 444 | |||
auto[1] | 5267691 | 1 | T1 | 2 | T2 | 18650 | T3 | 88 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30599339 | 1 | T1 | 280 | T2 | 185392 | T3 | 532 | |||
values[1] | 20 | 1 | T99 | 1 | T241 | 1 | T352 | 3 | |||
values[2] | 6 | 1 | T353 | 1 | T274 | 1 | T255 | 1 | |||
values[3] | 84 | 1 | T99 | 6 | T198 | 3 | T234 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 30599310 | 1 | T1 | 280 | T2 | 185392 | T3 | 532 | |||
values[1] | 17 | 1 | T99 | 1 | T198 | 1 | T234 | 1 | |||
values[2] | 9 | 1 | T99 | 1 | T198 | 1 | T241 | 1 | |||
values[3] | 124 | 1 | T99 | 3 | T198 | 7 | T234 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 30599225 | 1 | T1 | 280 | T2 | 185392 | T3 | 532 | |||
auto[TlIntgErrCmd] | 85 | 1 | T99 | 3 | T234 | 5 | T241 | 3 | |||
auto[TlIntgErrData] | 114 | 1 | T99 | 3 | T198 | 5 | T234 | 6 | |||
auto[TlIntgErrBoth] | 111 | 1 | T99 | 4 | T198 | 5 | T234 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4222511 | 0 | T2 | 41389 | T3 | 4 | T4 | 16637 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4222316 | 1 | T2 | 41389 | T3 | 4 | T4 | 16637 | |||
values[1] | 15 | 1 | T198 | 1 | T240 | 1 | T352 | 2 | |||
values[2] | 2 | 1 | T274 | 1 | T354 | 1 | - | - | |||
values[3] | 99 | 1 | T99 | 3 | T198 | 4 | T234 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4222323 | 1 | T2 | 41389 | T3 | 4 | T4 | 16637 | |||
values[1] | 20 | 1 | T198 | 1 | T234 | 1 | T241 | 1 | |||
values[2] | 9 | 1 | T99 | 1 | T198 | 1 | T241 | 1 | |||
values[3] | 94 | 1 | T99 | 4 | T198 | 2 | T234 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4222220 | 1 | T2 | 41389 | T3 | 4 | T4 | 16637 | |||
auto[TlIntgErrCmd] | 103 | 1 | T99 | 4 | T198 | 3 | T234 | 8 | |||
auto[TlIntgErrData] | 96 | 1 | T99 | 4 | T198 | 2 | T234 | 4 | |||
auto[TlIntgErrBoth] | 92 | 1 | T99 | 2 | T198 | 5 | T234 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |