Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22746314	1		T1	230		T2	156930		T3	358
full_word	7853221	1		T1	50		T2	28462		T3	174

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30599225	1		T1	280		T2	185392		T3	532
auto[TlIntgErrCmd]	85	1		T99	3		T234	5		T241	3
auto[TlIntgErrData]	114	1		T99	3		T198	5		T234	6
auto[TlIntgErrBoth]	111	1		T99	4		T198	5		T234	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26029968	1		T1	226		T2	163892		T3	442
auto[1]	4569567	1		T1	54		T2	21500		T3	90

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22019043	1		T1	224		T2	154158		T3	345
auto[TlIntgErrNone]	partial	auto[1]	726984	1		T1	6		T2	2772		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	4010792	1		T1	2		T2	9734		T3	97
auto[TlIntgErrNone]	full_word	auto[1]	3842406	1		T1	48		T2	18728		T3	77
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T99	1		T234	1		T241	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T99	1		T234	4		T241	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T99	1		T353	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T241	1		T352	1		T355	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T99	1		T234	3		T241	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T99	2		T198	3		T234	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T198	1		T352	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T198	1		T274	1		T255	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T99	3		T198	2		T234	3
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T99	1		T198	3		T234	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T352	1		T272	1		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T240	1		T272	1		T356	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19251	1		T69	313		T99	8		T100	16
full_word	4203260	1		T2	41389		T3	4		T4	16637

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4222220	1		T2	41389		T3	4		T4	16637
auto[TlIntgErrCmd]	103	1		T99	4		T198	3		T234	8
auto[TlIntgErrData]	96	1		T99	4		T198	2		T234	4
auto[TlIntgErrBoth]	92	1		T99	2		T198	5		T234	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4198130	1		T2	41389		T3	4		T4	16637
auto[1]	24381	1		T69	388		T99	8		T100	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1084	1		T69	7		T100	2		T197	62
auto[TlIntgErrNone]	partial	auto[1]	17893	1		T69	306		T100	14		T197	929
auto[TlIntgErrNone]	full_word	auto[0]	4196939	1		T2	41389		T3	4		T4	16637
auto[TlIntgErrNone]	full_word	auto[1]	6304	1		T69	82		T100	4		T197	577
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T99	1		T234	3		T240	4
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T99	1		T198	3		T234	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T234	1		T355	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T99	2		T272	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	35	1		T198	2		T234	1		T241	2
auto[TlIntgErrData]	partial	auto[1]	56	1		T99	4		T234	2		T241	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T234	1		T356	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T274	1		T356	1		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T99	1		T198	3		T234	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T99	1		T198	2		T234	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T241	1		T359	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T240	1		T352	1		T274	1