Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 98.41 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

315 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.num 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.op 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.start 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr10.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr11.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr12.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0 100.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.num
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.op
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.start
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1089 1 T68 129 T69 1 T70 185


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 863 1 T253 8 T360 7 T361 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1127 1 T253 8 T360 8 T361 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1205 1 T253 8 T360 8 T361 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1220 1 T253 7 T360 7 T361 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 909 1 T253 5 T360 8 T361 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 907 1 T253 4 T360 5 T361 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 35 1 T253 7 T360 7 T361 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 822 1 T78 6 T79 4 T80 3


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 831 1 T78 5 T79 7 T80 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 249 1 T68 28 T198 1 T234 7
auto[1] 700 1 T68 206 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 371 1 T68 28 T198 1 T234 7
auto[1] 775 1 T68 206 T99 9 T100 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298 1 T68 28 T198 1 T234 7
auto[1] 738 1 T68 206 T69 1 T99 10


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 228 1 T68 28 T198 1 T234 7
auto[1] 682 1 T68 206 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322 1 T68 28 T198 1 T234 6
auto[1] 746 1 T68 206 T69 1 T99 10


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 348 1 T68 28 T198 1 T234 7
auto[1] 770 1 T68 206 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 247 1 T198 1 T234 6 T302 1
auto[1] 739 1 T68 234 T69 1 T99 10


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 253 1 T68 69 T99 4 T198 4
auto[1] 1064 1 T68 74 T70 228 T99 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 416 1 T68 69 T99 4 T198 4
auto[1] 1109 1 T68 74 T69 1 T70 228


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319 1 T68 69 T99 4 T198 4
auto[1] 1088 1 T68 74 T69 1 T70 228


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 225 1 T68 69 T99 4 T198 4
auto[1] 1062 1 T68 74 T69 1 T70 228


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 345 1 T68 69 T99 3 T198 2
auto[1] 1096 1 T68 74 T69 1 T70 228


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 383 1 T68 69 T99 4 T198 3
auto[1] 1093 1 T68 74 T69 1 T70 228


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 220 1 T99 4 T198 4 T234 1
auto[1] 1001 1 T69 1 T70 228 T99 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 411 1 T70 116 T99 1 T100 1
auto[1] 807 1 T68 193 T69 1 T70 41


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 536 1 T70 116 T99 1 T100 1
auto[1] 850 1 T68 193 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 464 1 T70 116 T99 1 T198 3
auto[1] 842 1 T68 193 T69 1 T70 41


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 395 1 T70 116 T100 1 T198 3
auto[1] 798 1 T68 193 T69 1 T70 41


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 491 1 T70 116 T99 1 T100 1
auto[1] 855 1 T68 193 T69 1 T70 41


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 515 1 T70 116 T99 1 T100 1
auto[1] 803 1 T68 122 T69 1 T70 41


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 241 1 T99 1 T100 1 T198 3
auto[1] 942 1 T68 193 T69 1 T70 157


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 349 1 T68 76 T100 1 T198 3
auto[1] 797 1 T68 167 T69 1 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 431 1 T100 1 T198 3 T234 4
auto[1] 913 1 T68 243 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 417 1 T68 76 T99 1 T100 1
auto[1] 815 1 T68 167 T69 1 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313 1 T68 76 T99 1 T100 1
auto[1] 682 1 T68 167 T69 1 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 447 1 T68 76 T99 1 T100 1
auto[1] 823 1 T68 167 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 481 1 T68 76 T99 1 T100 1
auto[1] 828 1 T68 167 T69 1 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 382 1 T68 76 T99 1 T100 1
auto[1] 807 1 T68 167 T69 1 T99 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 340 1 T68 123 T99 2 T198 2
auto[1] 782 1 T69 1 T70 219 T99 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 416 1 T68 123 T99 2 T198 2
auto[1] 904 1 T69 1 T70 219 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 374 1 T68 123 T99 2 T198 2
auto[1] 828 1 T69 1 T70 219 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 321 1 T68 123 T99 2 T198 2
auto[1] 762 1 T69 1 T70 219 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 387 1 T68 123 T99 2 T198 2
auto[1] 858 1 T69 1 T70 219 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 401 1 T68 123 T99 2 T198 2
auto[1] 883 1 T69 1 T70 219 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 354 1 T68 123 T99 2 T198 2
auto[1] 805 1 T69 1 T70 219 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 408 1 T99 2 T198 4 T234 6
auto[1] 524 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 447 1 T99 2 T198 4 T234 6
auto[1] 689 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 422 1 T99 2 T198 4 T234 5
auto[1] 587 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 400 1 T99 2 T198 3 T234 5
auto[1] 499 1 T68 15 T70 129 T99 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 429 1 T99 2 T198 4 T234 6
auto[1] 621 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 440 1 T99 2 T198 4 T234 6
auto[1] 661 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 413 1 T99 2 T198 4 T234 6
auto[1] 565 1 T68 15 T69 1 T70 129


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 467 1 T68 91 T99 2 T198 4
auto[1] 748 1 T69 1 T70 199 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 545 1 T68 91 T99 2 T198 4
auto[1] 869 1 T69 1 T70 199 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 409 1 T99 2 T198 4 T234 6
auto[1] 804 1 T69 1 T70 199 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 452 1 T68 91 T99 2 T198 5
auto[1] 725 1 T69 1 T70 199 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 512 1 T68 91 T99 2 T198 5
auto[1] 822 1 T69 1 T70 199 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 530 1 T68 91 T99 2 T198 5
auto[1] 850 1 T69 1 T70 199 T99 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 480 1 T68 91 T99 1 T198 5
auto[1] 771 1 T69 1 T70 199 T99 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 547 1 T68 22 T69 1 T70 174
auto[1] 590 1 T68 207 T99 6 T100 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 628 1 T68 22 T69 1 T70 174
auto[1] 746 1 T68 207 T99 5 T100 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 581 1 T68 22 T69 1 T70 174
auto[1] 680 1 T68 207 T99 5 T198 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 532 1 T68 22 T69 1 T70 174
auto[1] 398 1 T99 6 T100 1 T198 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 596 1 T68 22 T69 1 T70 174
auto[1] 700 1 T68 207 T99 6 T100 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%