Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1558006364	1554746404	0	0
CheckNGreaterZero_A	4200	4200	0	0
GntImpliesReady_A	1558006364	391869465	0	0
GntImpliesValid_A	1558006364	391869465	0	0
GrantKnown_A	1558006364	1554746404	0	0
IdxKnown_A	1558006364	1554746404	0	0
IndexIsCorrect_A	1558006364	391869465	0	0
NoReadyValidNoGrant_A	1558006364	172708052	0	0
Priority_A	1558006364	416220263	0	0
ReadyAndValidImplyGrant_A	1558006364	391869465	0	0
ReqAndReadyImplyGrant_A	1558006364	391869465	0	0
ReqImpliesValid_A	1558006364	416220263	0	0
ValidKnown_A	1558006364	1554746404	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	1554746404	0	0
T1	4320	3968	0	0
T2	1521856	1521472	0	0
T3	9304	8636	0	0
T4	452904	452852	0	0
T6	754976	754292	0	0
T10	721460	721452	0	0
T17	4732	4488	0	0
T18	14912	12360	0	0
T19	8908	8708	0	0
T20	4424	3436	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4200	4200	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	391869465	0	0
T1	2160	716	0	0
T2	1521856	515914	0	0
T3	9304	426	0	0
T4	452904	81502	0	0
T5	0	65750	0	0
T6	754976	84678	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	19828	0	0
T38	0	20062	0	0
T58	0	15318	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	391869465	0	0
T1	2160	716	0	0
T2	1521856	515914	0	0
T3	9304	426	0	0
T4	452904	81502	0	0
T5	0	65750	0	0
T6	754976	84678	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	19828	0	0
T38	0	20062	0	0
T58	0	15318	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	1554746404	0	0
T1	4320	3968	0	0
T2	1521856	1521472	0	0
T3	9304	8636	0	0
T4	452904	452852	0	0
T6	754976	754292	0	0
T10	721460	721452	0	0
T17	4732	4488	0	0
T18	14912	12360	0	0
T19	8908	8708	0	0
T20	4424	3436	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	1554746404	0	0
T1	4320	3968	0	0
T2	1521856	1521472	0	0
T3	9304	8636	0	0
T4	452904	452852	0	0
T6	754976	754292	0	0
T10	721460	721452	0	0
T17	4732	4488	0	0
T18	14912	12360	0	0
T19	8908	8708	0	0
T20	4424	3436	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	391869465	0	0
T1	2160	716	0	0
T2	1521856	515914	0	0
T3	9304	426	0	0
T4	452904	81502	0	0
T5	0	65750	0	0
T6	754976	84678	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	19828	0	0
T38	0	20062	0	0
T58	0	15318	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	172708052	0	0
T1	2160	256	0	0
T2	1521856	181688	0	0
T3	9304	890	0	0
T4	452904	2560962	0	0
T5	0	3086	0	0
T6	754976	225086	0	0
T10	721460	2110362	0	0
T17	4732	256	0	0
T18	14912	1376	0	0
T19	8908	256	0	0
T20	4424	528	0	0
T21	0	9458	0	0
T30	1562992	696798	0	0
T38	0	57338	0	0
T58	0	580848	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	416220263	0	0
T1	2160	716	0	0
T2	1521856	616472	0	0
T3	9304	426	0	0
T4	452904	522410	0	0
T5	0	65750	0	0
T6	754976	87818	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	234206	0	0
T38	0	21290	0	0
T58	0	209596	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	391869465	0	0
T1	2160	716	0	0
T2	1521856	515914	0	0
T3	9304	426	0	0
T4	452904	81502	0	0
T5	0	65750	0	0
T6	754976	84678	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	19828	0	0
T38	0	20062	0	0
T58	0	15318	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	391869465	0	0
T1	2160	716	0	0
T2	1521856	515914	0	0
T3	9304	426	0	0
T4	452904	81502	0	0
T5	0	65750	0	0
T6	754976	84678	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	19828	0	0
T38	0	20062	0	0
T58	0	15318	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	416220263	0	0
T1	2160	716	0	0
T2	1521856	616472	0	0
T3	9304	426	0	0
T4	452904	522410	0	0
T5	0	65750	0	0
T6	754976	87818	0	0
T10	721460	1676672	0	0
T17	4732	64	0	0
T18	14912	346	0	0
T19	8908	64	0	0
T20	4424	132	0	0
T21	0	1376522	0	0
T30	1562992	234206	0	0
T38	0	21290	0	0
T58	0	209596	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1558006364	1554746404	0	0
T1	4320	3968	0	0
T2	1521856	1521472	0	0
T3	9304	8636	0	0
T4	452904	452852	0	0
T6	754976	754292	0	0
T10	721460	721452	0	0
T17	4732	4488	0	0
T18	14912	12360	0	0
T19	8908	8708	0	0
T20	4424	3436	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389501591	388686601	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	389501591	103891184	0	0
GntImpliesValid_A	389501591	103891184	0	0
GrantKnown_A	389501591	388686601	0	0
IdxKnown_A	389501591	388686601	0	0
IndexIsCorrect_A	389501591	103891184	0	0
NoReadyValidNoGrant_A	389501591	45055115	0	0
Priority_A	389501591	110037659	0	0
ReadyAndValidImplyGrant_A	389501591	103891184	0	0
ReqAndReadyImplyGrant_A	389501591	103891184	0	0
ReqImpliesValid_A	389501591	110037659	0	0
ValidKnown_A	389501591	388686601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891184	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891184	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891184	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	45055115	0	0
T1	1080	128	0	0
T2	380464	52820	0	0
T3	2326	437	0	0
T4	113226	613157	0	0
T6	188744	54872	0	0
T10	180365	530841	0	0
T17	1183	128	0	0
T18	3728	688	0	0
T19	2227	128	0	0
T20	1106	264	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	110037659	0	0
T1	1080	358	0	0
T2	380464	167048	0	0
T3	2326	211	0	0
T4	113226	137148	0	0
T6	188744	21626	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891184	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891184	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	110037659	0	0
T1	1080	358	0	0
T2	380464	167048	0	0
T3	2326	211	0	0
T4	113226	137148	0	0
T6	188744	21626	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389501591	388686601	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	389501591	103891241	0	0
GntImpliesValid_A	389501591	103891241	0	0
GrantKnown_A	389501591	388686601	0	0
IdxKnown_A	389501591	388686601	0	0
IndexIsCorrect_A	389501591	103891241	0	0
NoReadyValidNoGrant_A	389501591	45055089	0	0
Priority_A	389501591	110037742	0	0
ReadyAndValidImplyGrant_A	389501591	103891241	0	0
ReqAndReadyImplyGrant_A	389501591	103891241	0	0
ReqImpliesValid_A	389501591	110037742	0	0
ValidKnown_A	389501591	388686601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891241	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891241	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891241	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	45055089	0	0
T1	1080	128	0	0
T2	380464	52820	0	0
T3	2326	437	0	0
T4	113226	613157	0	0
T6	188744	54872	0	0
T10	180365	530841	0	0
T17	1183	128	0	0
T18	3728	688	0	0
T19	2227	128	0	0
T20	1106	264	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	110037742	0	0
T1	1080	358	0	0
T2	380464	167048	0	0
T3	2326	211	0	0
T4	113226	137148	0	0
T6	188744	21626	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891241	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	103891241	0	0
T1	1080	358	0	0
T2	380464	139067	0	0
T3	2326	211	0	0
T4	113226	19467	0	0
T6	188744	20656	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	110037742	0	0
T1	1080	358	0	0
T2	380464	167048	0	0
T3	2326	211	0	0
T4	113226	137148	0	0
T6	188744	21626	0	0
T10	180365	424868	0	0
T17	1183	32	0	0
T18	3728	173	0	0
T19	2227	32	0	0
T20	1106	66	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T10
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T10
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389501591	388686601	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	389501591	92043520	0	0
GntImpliesValid_A	389501591	92043520	0	0
GrantKnown_A	389501591	388686601	0	0
IdxKnown_A	389501591	388686601	0	0
IndexIsCorrect_A	389501591	92043520	0	0
NoReadyValidNoGrant_A	389501591	41298924	0	0
Priority_A	389501591	98072431	0	0
ReadyAndValidImplyGrant_A	389501591	92043520	0	0
ReqAndReadyImplyGrant_A	389501591	92043520	0	0
ReqImpliesValid_A	389501591	98072431	0	0
ValidKnown_A	389501591	388686601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	41298924	0	0
T2	380464	38024	0	0
T3	2326	8	0	0
T4	113226	667324	0	0
T5	0	1543	0	0
T6	188744	57671	0	0
T10	180365	524340	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	4729	0	0
T30	781496	348399	0	0
T38	0	28669	0	0
T58	0	290424	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	98072431	0	0
T2	380464	141188	0	0
T3	2326	2	0	0
T4	113226	124057	0	0
T5	0	32875	0	0
T6	188744	22283	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	117103	0	0
T38	0	10645	0	0
T58	0	104798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	98072431	0	0
T2	380464	141188	0	0
T3	2326	2	0	0
T4	113226	124057	0	0
T5	0	32875	0	0
T6	188744	22283	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	117103	0	0
T38	0	10645	0	0
T58	0	104798	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T10
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T10
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389501591	388686601	0	0
CheckNGreaterZero_A	1050	1050	0	0
GntImpliesReady_A	389501591	92043520	0	0
GntImpliesValid_A	389501591	92043520	0	0
GrantKnown_A	389501591	388686601	0	0
IdxKnown_A	389501591	388686601	0	0
IndexIsCorrect_A	389501591	92043520	0	0
NoReadyValidNoGrant_A	389501591	41298924	0	0
Priority_A	389501591	98072431	0	0
ReadyAndValidImplyGrant_A	389501591	92043520	0	0
ReqAndReadyImplyGrant_A	389501591	92043520	0	0
ReqImpliesValid_A	389501591	98072431	0	0
ValidKnown_A	389501591	388686601	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1050	1050	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	41298924	0	0
T2	380464	38024	0	0
T3	2326	8	0	0
T4	113226	667324	0	0
T5	0	1543	0	0
T6	188744	57671	0	0
T10	180365	524340	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	4729	0	0
T30	781496	348399	0	0
T38	0	28669	0	0
T58	0	290424	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	98072431	0	0
T2	380464	141188	0	0
T3	2326	2	0	0
T4	113226	124057	0	0
T5	0	32875	0	0
T6	188744	22283	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	117103	0	0
T38	0	10645	0	0
T58	0	104798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	92043520	0	0
T2	380464	118890	0	0
T3	2326	2	0	0
T4	113226	21284	0	0
T5	0	32875	0	0
T6	188744	21683	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	9914	0	0
T38	0	10031	0	0
T58	0	7659	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	98072431	0	0
T2	380464	141188	0	0
T3	2326	2	0	0
T4	113226	124057	0	0
T5	0	32875	0	0
T6	188744	22283	0	0
T10	180365	413468	0	0
T17	1183	0	0	0
T18	3728	0	0	0
T19	2227	0	0	0
T20	1106	0	0	0
T21	0	688261	0	0
T30	781496	117103	0	0
T38	0	10645	0	0
T58	0	104798	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389501591	388686601	0	0
T1	1080	992	0	0
T2	380464	380368	0	0
T3	2326	2159	0	0
T4	113226	113213	0	0
T6	188744	188573	0	0
T10	180365	180363	0	0
T17	1183	1122	0	0
T18	3728	3090	0	0
T19	2227	2177	0	0
T20	1106	859	0	0