Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.93 100.00 91.70 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.50 92.31 97.69 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.76 100.00 91.05 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 100.00 86.27 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_op


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 100.00 97.67 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 100.00 40.00 100.00 u_prim_arbiter_tree_calc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :
SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORELINE
92.50 92.31
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :
SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORELINE
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORELINE
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
97.86 97.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT2,T3,T10
111UnreachableT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T6,T38
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :
SCORECOND
95.01 86.27
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORECOND
95.01 86.27
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT2,T3,T10
111CoveredT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :
SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORECOND
92.50 97.69
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT38,T54,T55
11CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T6,T38

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCOREBRANCH
92.50 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
97.86 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCOREBRANCH
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCOREBRANCH
95.01 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_arbiter_tree
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 2147483647 2147483647 0 0
CheckNGreaterZero_A 6300 6300 0 0
GntImpliesReady_A 2147483647 71181797 0 0
GntImpliesValid_A 2147483647 71181797 0 0
GrantKnown_A 2147483647 2147483647 0 0
IdxKnown_A 2147483647 2147483647 0 0
IndexIsCorrect_A 2147483647 71181797 0 0
LockArbDecision_A 2147483647 65929100 0 0
NoReadyValidNoGrant_A 2147483647 1975391832 0 0
ReadyAndValidImplyGrant_A 2147483647 71181797 0 0
ReqAndReadyImplyGrant_A 2147483647 71181797 0 0
ReqImpliesValid_A 2147483647 346913289 0 0
ReqStaysHighUntilGranted0_M 2147483647 65929100 0 0
RoundRobin_A 2147483647 0 0 6270
ValidKnown_A 2147483647 2147483647 0 0
gen_data_port_assertion.DataFlow_A 1558006364 65929096 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6480 5952 0 0
T2 2282784 2282208 0 0
T3 13956 12954 0 0
T4 679356 679278 0 0
T6 1132464 1131438 0 0
T10 1082190 1082178 0 0
T17 7098 6732 0 0
T18 22368 18540 0 0
T19 13362 13062 0 0
T20 6636 5154 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6300 6300 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T6 6 6 0 0
T10 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0
T20 6 6 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 71181797 0 0
T1 4320 132 0 0
T2 2282784 153263 0 0
T3 13956 421 0 0
T4 679356 29427 0 0
T5 0 705 0 0
T6 1132464 148447 0 0
T10 1082190 1582313 0 0
T17 7098 128 0 0
T18 22368 688 0 0
T19 13362 128 0 0
T20 6636 264 0 0
T21 0 2073 0 0
T22 0 120 0 0
T30 1562992 22673 0 0
T38 0 6615 0 0
T57 0 460 0 0
T58 0 16303 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 71181797 0 0
T1 4320 132 0 0
T2 2282784 153263 0 0
T3 13956 421 0 0
T4 679356 29427 0 0
T5 0 705 0 0
T6 1132464 148447 0 0
T10 1082190 1582313 0 0
T17 7098 128 0 0
T18 22368 688 0 0
T19 13362 128 0 0
T20 6636 264 0 0
T21 0 2073 0 0
T22 0 120 0 0
T30 1562992 22673 0 0
T38 0 6615 0 0
T57 0 460 0 0
T58 0 16303 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6480 5952 0 0
T2 2282784 2282208 0 0
T3 13956 12954 0 0
T4 679356 679278 0 0
T6 1132464 1131438 0 0
T10 1082190 1082178 0 0
T17 7098 6732 0 0
T18 22368 18540 0 0
T19 13362 13062 0 0
T20 6636 5154 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6480 5952 0 0
T2 2282784 2282208 0 0
T3 13956 12954 0 0
T4 679356 679278 0 0
T6 1132464 1131438 0 0
T10 1082190 1082178 0 0
T17 7098 6732 0 0
T18 22368 18540 0 0
T19 13362 13062 0 0
T20 6636 5154 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 71181797 0 0
T1 4320 132 0 0
T2 2282784 153263 0 0
T3 13956 421 0 0
T4 679356 29427 0 0
T5 0 705 0 0
T6 1132464 148447 0 0
T10 1082190 1582313 0 0
T17 7098 128 0 0
T18 22368 688 0 0
T19 13362 128 0 0
T20 6636 264 0 0
T21 0 2073 0 0
T22 0 120 0 0
T30 1562992 22673 0 0
T38 0 6615 0 0
T57 0 460 0 0
T58 0 16303 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 65929100 0 0
T1 4320 132 0 0
T2 1521856 108180 0 0
T3 9304 384 0 0
T4 452904 134 0 0
T6 754976 118476 0 0
T10 721460 1582208 0 0
T17 4732 128 0 0
T18 14912 688 0 0
T19 8908 128 0 0
T20 4424 264 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1975391832 0 0
T1 6480 5656 0 0
T2 2282784 1305887 0 0
T3 13956 11632 0 0
T4 679356 457301 0 0
T6 1132464 519149 0 0
T10 1082190 954642 0 0
T17 7098 6444 0 0
T18 22368 16991 0 0
T19 13362 12774 0 0
T20 6636 4560 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 71181797 0 0
T1 4320 132 0 0
T2 2282784 153263 0 0
T3 13956 421 0 0
T4 679356 29427 0 0
T5 0 705 0 0
T6 1132464 148447 0 0
T10 1082190 1582313 0 0
T17 7098 128 0 0
T18 22368 688 0 0
T19 13362 128 0 0
T20 6636 264 0 0
T21 0 2073 0 0
T22 0 120 0 0
T30 1562992 22673 0 0
T38 0 6615 0 0
T57 0 460 0 0
T58 0 16303 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 71181797 0 0
T1 4320 132 0 0
T2 2282784 153263 0 0
T3 13956 421 0 0
T4 679356 29427 0 0
T5 0 705 0 0
T6 1132464 148447 0 0
T10 1082190 1582313 0 0
T17 7098 128 0 0
T18 22368 688 0 0
T19 13362 128 0 0
T20 6636 264 0 0
T21 0 2073 0 0
T22 0 120 0 0
T30 1562992 22673 0 0
T38 0 6615 0 0
T57 0 460 0 0
T58 0 16303 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 346913289 0 0
T1 4320 264 0 0
T2 2282784 976281 0 0
T3 13956 1251 0 0
T4 679356 226244 0 0
T5 0 148983 0 0
T6 1132464 612217 0 0
T10 1082190 4096972 0 0
T17 7098 256 0 0
T18 22368 1376 0 0
T19 13362 256 0 0
T20 6636 528 0 0
T21 0 591678 0 0
T22 0 72067 0 0
T30 1562992 1557873 0 0
T38 0 43896 0 0
T57 0 28965 0 0
T58 0 1129791 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 65929100 0 0
T1 4320 132 0 0
T2 1521856 108180 0 0
T3 9304 384 0 0
T4 452904 134 0 0
T6 754976 118476 0 0
T10 721460 1582208 0 0
T17 4732 128 0 0
T18 14912 688 0 0
T19 8908 128 0 0
T20 4424 264 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 6270

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 6480 5952 0 0
T2 2282784 2282208 0 0
T3 13956 12954 0 0
T4 679356 679278 0 0
T6 1132464 1131438 0 0
T10 1082190 1082178 0 0
T17 7098 6732 0 0
T18 22368 18540 0 0
T19 13362 13062 0 0
T20 6636 5154 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1558006364 65929096 0 0
T1 4320 132 0 0
T2 1521856 108180 0 0
T3 9304 384 0 0
T4 452904 134 0 0
T6 754976 118476 0 0
T10 721460 1582208 0 0
T17 4732 128 0 0
T18 14912 688 0 0
T19 8908 128 0 0
T20 4424 264 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT38,T54,T55
11CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T3,T4
110CoveredT2,T3,T4
111CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T6,T38

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10CoveredT2,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T3,T4
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT2,T3,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T3,T4


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 2778745 0 0
GntImpliesValid_A 389501591 2778745 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 2778745 0 0
LockArbDecision_A 389501591 0 0 0
NoReadyValidNoGrant_A 389501591 271235263 0 0
ReadyAndValidImplyGrant_A 389501591 2778745 0 0
ReqAndReadyImplyGrant_A 389501591 2778745 0 0
ReqImpliesValid_A 389501591 112222316 0 0
ReqStaysHighUntilGranted0_M 389501591 0 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2778745 0 0
T2 380464 22662 0 0
T3 2326 37 0 0
T4 113226 14260 0 0
T5 0 399 0 0
T6 188744 14572 0 0
T10 180365 90 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 518 0 0
T30 781496 13691 0 0
T57 0 460 0 0
T58 0 8649 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2778745 0 0
T2 380464 22662 0 0
T3 2326 37 0 0
T4 113226 14260 0 0
T5 0 399 0 0
T6 188744 14572 0 0
T10 180365 90 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 518 0 0
T30 781496 13691 0 0
T57 0 460 0 0
T58 0 8649 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2778745 0 0
T2 380464 22662 0 0
T3 2326 37 0 0
T4 113226 14260 0 0
T5 0 399 0 0
T6 188744 14572 0 0
T10 180365 90 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 518 0 0
T30 781496 13691 0 0
T57 0 460 0 0
T58 0 8649 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 271235263 0 0
T1 1080 960 0 0
T2 380464 368 0 0
T3 2326 1607 0 0
T4 113226 2219 0 0
T6 188744 869 0 0
T10 180365 125841 0 0
T17 1183 1090 0 0
T18 3728 2917 0 0
T19 2227 2145 0 0
T20 1106 793 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2778745 0 0
T2 380464 22662 0 0
T3 2326 37 0 0
T4 113226 14260 0 0
T5 0 399 0 0
T6 188744 14572 0 0
T10 180365 90 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 518 0 0
T30 781496 13691 0 0
T57 0 460 0 0
T58 0 8649 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2778745 0 0
T2 380464 22662 0 0
T3 2326 37 0 0
T4 113226 14260 0 0
T5 0 399 0 0
T6 188744 14572 0 0
T10 180365 90 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 518 0 0
T30 781496 13691 0 0
T57 0 460 0 0
T58 0 8649 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 112222316 0 0
T2 380464 379964 0 0
T3 2326 483 0 0
T4 113226 112988 0 0
T5 0 74609 0 0
T6 188744 187636 0 0
T10 180365 531960 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 63392 0 0
T30 781496 778930 0 0
T57 0 28965 0 0
T58 0 565024 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
TOTAL524892.31
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16300
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 4 4
118 4 4
122 0 4
126 4 4
128 4 4
148 3 3
150 3 3
151 3 3
155 3 3
156 3 3
160 3 3
161 3 3
163 1 1(2 unreachable)
164 3 3
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalCoveredPercent
Conditions13012797.69
Logical13012797.69
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT38,T54,T55
11CoveredT2,T4,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T10
110CoveredT2,T4,T10
111CoveredT2,T4,T10

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T10
110CoveredT2,T4,T10
111CoveredT2,T4,T10

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T4,T10
110CoveredT2,T4,T10
111CoveredT2,T4,T10

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT2,T4,T10
110CoveredT2,T4,T10
111CoveredT2,T4,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT1,T2,T3
11CoveredT2,T4,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT1,T2,T3
11CoveredT2,T4,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))
-1--2-StatusTests
00CoveredT2,T4,T10
01CoveredT2,T4,T10
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT1,T2,T3
11CoveredT2,T4,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T6,T38

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT2,T4,T10

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T6
10CoveredT2,T4,T10

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT2,T4,T10
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT2,T4,T10

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT2,T4,T10
10CoveredT1,T2,T3
11CoveredT2,T4,T10

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT2,T4,T10
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT2,T4,T6
10CoveredT2,T4,T10
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10CoveredT2,T4,T10

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
Line No.TotalCoveredPercent
Branches 22 22 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T4,T10


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T10
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 12 80.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 12 80.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 2473956 0 0
GntImpliesValid_A 389501591 2473956 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 2473956 0 0
LockArbDecision_A 389501591 0 0 0
NoReadyValidNoGrant_A 389501591 281268399 0 0
ReadyAndValidImplyGrant_A 389501591 2473956 0 0
ReqAndReadyImplyGrant_A 389501591 2473956 0 0
ReqImpliesValid_A 389501591 102832739 0 0
ReqStaysHighUntilGranted0_M 389501591 0 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2473956 0 0
T2 380464 22421 0 0
T3 2326 0 0 0
T4 113226 15033 0 0
T5 0 306 0 0
T6 188744 15399 0 0
T10 180365 15 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 1555 0 0
T22 0 120 0 0
T30 781496 8982 0 0
T38 0 6615 0 0
T58 0 7654 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2473956 0 0
T2 380464 22421 0 0
T3 2326 0 0 0
T4 113226 15033 0 0
T5 0 306 0 0
T6 188744 15399 0 0
T10 180365 15 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 1555 0 0
T22 0 120 0 0
T30 781496 8982 0 0
T38 0 6615 0 0
T58 0 7654 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2473956 0 0
T2 380464 22421 0 0
T3 2326 0 0 0
T4 113226 15033 0 0
T5 0 306 0 0
T6 188744 15399 0 0
T10 180365 15 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 1555 0 0
T22 0 120 0 0
T30 781496 8982 0 0
T38 0 6615 0 0
T58 0 7654 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 281268399 0 0
T1 1080 992 0 0
T2 380464 407 0 0
T3 2326 2157 0 0
T4 113226 2254 0 0
T6 188744 940 0 0
T10 180365 138993 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2473956 0 0
T2 380464 22421 0 0
T3 2326 0 0 0
T4 113226 15033 0 0
T5 0 306 0 0
T6 188744 15399 0 0
T10 180365 15 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 1555 0 0
T22 0 120 0 0
T30 781496 8982 0 0
T38 0 6615 0 0
T58 0 7654 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 2473956 0 0
T2 380464 22421 0 0
T3 2326 0 0 0
T4 113226 15033 0 0
T5 0 306 0 0
T6 188744 15399 0 0
T10 180365 15 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 1555 0 0
T22 0 120 0 0
T30 781496 8982 0 0
T38 0 6615 0 0
T58 0 7654 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 102832739 0 0
T2 380464 379957 0 0
T3 2326 0 0 0
T4 113226 112988 0 0
T5 0 74374 0 0
T6 188744 187629 0 0
T10 180365 400596 0 0
T17 1183 0 0 0
T18 3728 0 0 0
T19 2227 0 0 0
T20 1106 0 0 0
T21 0 528286 0 0
T22 0 72067 0 0
T30 781496 778943 0 0
T38 0 43896 0 0
T58 0 564767 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT2,T3,T10
111CoveredT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 15886704 0 0
GntImpliesValid_A 389501591 15886704 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 15886704 0 0
LockArbDecision_A 389501591 15886704 0 0
NoReadyValidNoGrant_A 389501591 356913188 0 0
ReadyAndValidImplyGrant_A 389501591 15886704 0 0
ReqAndReadyImplyGrant_A 389501591 15886704 0 0
ReqImpliesValid_A 389501591 31773413 0 0
ReqStaysHighUntilGranted0_M 389501591 15886704 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0
gen_data_port_assertion.DataFlow_A 389501591 15886704 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 356913188 0 0
T1 1080 926 0 0
T2 380464 370876 0 0
T3 2326 1967 0 0
T4 113226 113207 0 0
T6 188744 129335 0 0
T10 180365 172452 0 0
T17 1183 1058 0 0
T18 3728 2748 0 0
T19 2227 2113 0 0
T20 1106 727 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 31773413 0 0
T1 1080 66 0 0
T2 380464 9492 0 0
T3 2326 192 0 0
T4 113226 66 0 0
T6 188744 59238 0 0
T10 180365 791104 0 0
T17 1183 64 0 0
T18 3728 342 0 0
T19 2227 64 0 0
T20 1106 132 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions514486.27
Logical514486.27
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT2,T3,T10
111CoveredT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 15886704 0 0
GntImpliesValid_A 389501591 15886704 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 15886704 0 0
LockArbDecision_A 389501591 15886704 0 0
NoReadyValidNoGrant_A 389501591 356913188 0 0
ReadyAndValidImplyGrant_A 389501591 15886704 0 0
ReqAndReadyImplyGrant_A 389501591 15886704 0 0
ReqImpliesValid_A 389501591 31773413 0 0
ReqStaysHighUntilGranted0_M 389501591 15886704 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0
gen_data_port_assertion.DataFlow_A 389501591 15886704 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 356913188 0 0
T1 1080 926 0 0
T2 380464 370876 0 0
T3 2326 1967 0 0
T4 113226 113207 0 0
T6 188744 129335 0 0
T10 180365 172452 0 0
T17 1183 1058 0 0
T18 3728 2748 0 0
T19 2227 2113 0 0
T20 1106 727 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 31773413 0 0
T1 1080 66 0 0
T2 380464 9492 0 0
T3 2326 192 0 0
T4 113226 66 0 0
T6 188744 59238 0 0
T10 180365 791104 0 0
T17 1183 64 0 0
T18 3728 342 0 0
T19 2227 64 0 0
T20 1106 132 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 15886704 0 0
T1 1080 33 0 0
T2 380464 4746 0 0
T3 2326 96 0 0
T4 113226 33 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 171 0 0
T19 2227 32 0 0
T20 1106 66 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT2,T3,T10
111UnreachableT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T6,T38
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 17077844 0 0
GntImpliesValid_A 389501591 17077844 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 17077844 0 0
LockArbDecision_A 389501592 17077846 0 0
NoReadyValidNoGrant_A 389501591 354530897 0 0
ReadyAndValidImplyGrant_A 389501591 17077844 0 0
ReqAndReadyImplyGrant_A 389501591 17077844 0 0
ReqImpliesValid_A 389501591 34155704 0 0
ReqStaysHighUntilGranted0_M 389501592 17077846 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0
gen_data_port_assertion.DataFlow_A 389501591 17077844 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501592 17077846 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 354530897 0 0
T1 1080 926 0 0
T2 380464 281680 0 0
T3 2326 1967 0 0
T4 113226 113207 0 0
T6 188744 129335 0 0
T10 180365 172452 0 0
T17 1183 1058 0 0
T18 3728 2744 0 0
T19 2227 2113 0 0
T20 1106 727 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 34155704 0 0
T1 1080 66 0 0
T2 380464 98688 0 0
T3 2326 192 0 0
T4 113226 68 0 0
T6 188744 59238 0 0
T10 180365 791104 0 0
T17 1183 64 0 0
T18 3728 346 0 0
T19 2227 64 0 0
T20 1106 132 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501592 17077846 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN6200
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12600
CONT_ASSIGN12600
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 unreachable
112 2 2
118 2 2
122 2 2
126 unreachable
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
171 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalCoveredPercent
Conditions434297.67
Logical434297.67
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T6
11CoveredT2,T3,T10

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT1,T2,T3
111UnreachableT1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Unreachable
101UnreachableT2,T6,T38
110CoveredT2,T3,T10
111UnreachableT2,T3,T10

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T10
10UnreachableT1,T2,T3
11CoveredT1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT2,T3,T10
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10UnreachableT2,T3,T10
11CoveredT2,T3,T10

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T6,T38
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01CoveredT2,T6,T38
10CoveredT1,T2,T3
11CoveredT2,T3,T10

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T10
10CoveredT1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T10

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Unreachable

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 389501591 388686601 0 0
CheckNGreaterZero_A 1050 1050 0 0
GntImpliesReady_A 389501591 17077844 0 0
GntImpliesValid_A 389501591 17077844 0 0
GrantKnown_A 389501591 388686601 0 0
IdxKnown_A 389501591 388686601 0 0
IndexIsCorrect_A 389501591 17077844 0 0
LockArbDecision_A 389501592 17077846 0 0
NoReadyValidNoGrant_A 389501591 354530897 0 0
ReadyAndValidImplyGrant_A 389501591 17077844 0 0
ReqAndReadyImplyGrant_A 389501591 17077844 0 0
ReqImpliesValid_A 389501591 34155704 0 0
ReqStaysHighUntilGranted0_M 389501592 17077846 0 0
RoundRobin_A 389501591 0 0 1045
ValidKnown_A 389501591 388686601 0 0
gen_data_port_assertion.DataFlow_A 389501591 17077844 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501592 17077846 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 354530897 0 0
T1 1080 926 0 0
T2 380464 281680 0 0
T3 2326 1967 0 0
T4 113226 113207 0 0
T6 188744 129335 0 0
T10 180365 172452 0 0
T17 1183 1058 0 0
T18 3728 2744 0 0
T19 2227 2113 0 0
T20 1106 727 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 34155704 0 0
T1 1080 66 0 0
T2 380464 98688 0 0
T3 2326 192 0 0
T4 113226 68 0 0
T6 188744 59238 0 0
T10 180365 791104 0 0
T17 1183 64 0 0
T18 3728 346 0 0
T19 2227 64 0 0
T20 1106 132 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501592 17077846 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 0 0 1045

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 388686601 0 0
T1 1080 992 0 0
T2 380464 380368 0 0
T3 2326 2159 0 0
T4 113226 113213 0 0
T6 188744 188573 0 0
T10 180365 180363 0 0
T17 1183 1122 0 0
T18 3728 3090 0 0
T19 2227 2177 0 0
T20 1106 859 0 0

gen_data_port_assertion.DataFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 389501591 17077844 0 0
T1 1080 33 0 0
T2 380464 49344 0 0
T3 2326 96 0 0
T4 113226 34 0 0
T6 188744 29619 0 0
T10 180365 395552 0 0
T17 1183 32 0 0
T18 3728 173 0 0
T19 2227 32 0 0
T20 1106 66 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%