SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.96 | 100.00 | 93.75 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.22 | 97.67 | 88.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10500 | 10500 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21810 |
gen_no_flops.OutputDelay_A | 766529812 | 764899832 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10500 | 10500 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T10 | 10 | 10 | 0 | 0 |
T17 | 10 | 10 | 0 | 0 |
T18 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
T20 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 10194 | 9314 | 0 | 0 |
T2 | 3804640 | 3803680 | 0 | 0 |
T3 | 23260 | 21590 | 0 | 0 |
T4 | 1132260 | 1132130 | 0 | 0 |
T6 | 1887440 | 1885730 | 0 | 0 |
T10 | 1803650 | 1803630 | 0 | 0 |
T17 | 3600 | 2990 | 0 | 0 |
T18 | 37280 | 30900 | 0 | 0 |
T19 | 22270 | 21770 | 0 | 0 |
T20 | 11060 | 8590 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21810 |
T1 | 8034 | 7309 | 0 | 21 |
T2 | 3043712 | 3042920 | 0 | 24 |
T3 | 18608 | 17224 | 0 | 24 |
T4 | 905808 | 905704 | 0 | 24 |
T6 | 1509952 | 1508536 | 0 | 24 |
T10 | 1442920 | 1442904 | 0 | 24 |
T17 | 2880 | 2392 | 0 | 0 |
T18 | 29824 | 24504 | 0 | 24 |
T19 | 17816 | 17392 | 0 | 24 |
T20 | 8848 | 6800 | 0 | 24 |
T30 | 0 | 0 | 0 | 24 |
T84 | 0 | 0 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 766529812 | 764899832 | 0 | 0 |
T1 | 2160 | 1984 | 0 | 0 |
T2 | 760928 | 760736 | 0 | 0 |
T3 | 4652 | 4318 | 0 | 0 |
T4 | 226452 | 226426 | 0 | 0 |
T6 | 377488 | 377146 | 0 | 0 |
T10 | 360730 | 360726 | 0 | 0 |
T17 | 720 | 598 | 0 | 0 |
T18 | 7456 | 6180 | 0 | 0 |
T19 | 4454 | 4354 | 0 | 0 |
T20 | 2212 | 1718 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264970 | 382449980 | 0 | 0 |
gen_flops.OutputDelay_A | 383264970 | 382417889 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382449980 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264970 | 382417889 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264906 | 382449916 | 0 | 0 |
gen_no_flops.OutputDelay_A | 383264906 | 382449916 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382449916 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382449916 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383240654 | 382425664 | 0 | 0 |
gen_flops.OutputDelay_A | 383240654 | 382393723 | 0 | 2595 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383240654 | 382425664 | 0 | 0 |
T1 | 474 | 386 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383240654 | 382393723 | 0 | 2595 |
T1 | 474 | 386 | 0 | 0 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
T84 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264906 | 382449916 | 0 | 0 |
gen_no_flops.OutputDelay_A | 383264906 | 382449916 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382449916 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382449916 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1050 | 1050 | 0 | 0 |
OutputsKnown_A | 383264906 | 382449916 | 0 | 0 |
gen_flops.OutputDelay_A | 383264906 | 382417840 | 0 | 2745 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1050 | 1050 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382449916 | 0 | 0 |
T1 | 1080 | 992 | 0 | 0 |
T2 | 380464 | 380368 | 0 | 0 |
T3 | 2326 | 2159 | 0 | 0 |
T4 | 113226 | 113213 | 0 | 0 |
T6 | 188744 | 188573 | 0 | 0 |
T10 | 180365 | 180363 | 0 | 0 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3090 | 0 | 0 |
T19 | 2227 | 2177 | 0 | 0 |
T20 | 1106 | 859 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 383264906 | 382417840 | 0 | 2745 |
T1 | 1080 | 989 | 0 | 3 |
T2 | 380464 | 380365 | 0 | 3 |
T3 | 2326 | 2153 | 0 | 3 |
T4 | 113226 | 113213 | 0 | 3 |
T6 | 188744 | 188567 | 0 | 3 |
T10 | 180365 | 180363 | 0 | 3 |
T17 | 360 | 299 | 0 | 0 |
T18 | 3728 | 3063 | 0 | 3 |
T19 | 2227 | 2174 | 0 | 3 |
T20 | 1106 | 850 | 0 | 3 |
T30 | 0 | 0 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |