Line Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
TOTAL | | 44 | 44 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 60 | 5 | 5 | 100.00 |
ALWAYS | 97 | 4 | 4 | 100.00 |
CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
ALWAYS | 113 | 24 | 24 | 100.00 |
CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
65 |
1 |
1 |
97 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
|
|
|
MISSING_ELSE |
104 |
1 |
1 |
105 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
119 |
1 |
1 |
121 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
145 |
1 |
1 |
|
|
|
MISSING_ELSE |
151 |
1 |
1 |
153 |
1 |
1 |
154 |
1 |
1 |
155 |
1 |
1 |
|
|
|
MISSING_ELSE |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
167 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
Cond Coverage for Module :
flash_ctrl_rd
| Total | Covered | Percent |
Conditions | 33 | 31 | 93.94 |
Logical | 33 | 31 | 93.94 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 99
EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
-------1------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T20 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T20 |
LINE 104
EXPRESSION (flash_req_o & flash_done_i)
-----1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T5,T21 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 133
EXPRESSION (op_start_i & data_rdy_i)
-----1---- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T96,T158,T107 |
1 | 0 | Covered | T42,T196,T43 |
1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T20 |
LINE 153
EXPRESSION (data_rdy_i && cnt_hit)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T32,T42 |
1 | 0 | Covered | T2,T3,T20 |
1 | 1 | Covered | T2,T3,T20 |
LINE 167
EXPRESSION (data_wr_o & ((|op_err_o)))
----1---- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T32,T42 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T20 |
LINE 180
EXPRESSION ((((~err_sel)) | (err_sel & op_err_o.rd_err)) ? flash_data_i : inv_data_integ)
----------------------1---------------------
-1- | Status | Tests |
0 | Covered | T2,T30,T5 |
1 | Covered | T1,T2,T3 |
LINE 180
SUB-EXPRESSION (((~err_sel)) | (err_sel & op_err_o.rd_err))
------1----- -------------2-------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T30,T5 |
0 | 1 | Covered | T3,T20,T38 |
1 | 0 | Covered | T1,T2,T3 |
LINE 180
SUB-EXPRESSION (err_sel & op_err_o.rd_err)
---1--- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T30,T5 |
1 | 1 | Covered | T3,T20,T38 |
FSM Coverage for Module :
flash_ctrl_rd
Summary for FSM :: st_q
| Total | Covered | Percent | |
States |
3 |
3 |
100.00 |
(Not included in score) |
Transitions |
5 |
5 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
states | Line No. | Covered | Tests |
StErr |
123 |
Covered |
T2,T3,T20 |
StIdle |
143 |
Covered |
T1,T2,T3 |
StNorm |
126 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
StErr->StIdle |
154 |
Covered |
T2,T3,T20 |
StIdle->StErr |
123 |
Covered |
T14,T15,T16 |
StIdle->StNorm |
126 |
Covered |
T1,T2,T3 |
StNorm->StErr |
145 |
Covered |
T2,T3,T20 |
StNorm->StIdle |
143 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
IF |
60 |
3 |
3 |
100.00 |
IF |
97 |
3 |
3 |
100.00 |
CASE |
119 |
11 |
10 |
90.91 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 180 (((~err_sel) | (err_sel & op_err_o.rd_err))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T30,T5 |
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 if ((!rst_ni))
-2-: 62 if ((op_start_i && op_done_o))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 97 if ((!rst_ni))
-2-: 99 if (((~|op_err_q) && (|op_err_d)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T20 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 119 case (st_q)
-2-: 121 if (cnt_err_o)
-3-: 124 if (op_start_i)
-4-: 126 ((|op_err_d)) ?
-5-: 135 if (txn_done)
-6-: 141 if (cnt_hit)
-7-: 145 ((|op_err_d)) ?
-8-: 153 if ((data_rdy_i && cnt_hit))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
StIdle |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T15,T16 |
StIdle |
0 |
1 |
1 |
- |
- |
- |
- |
Not Covered |
|
StIdle |
0 |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
- |
1 |
0 |
1 |
- |
Covered |
T2,T3,T20 |
StNorm |
- |
- |
- |
1 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
StNorm |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
StErr |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T3,T20 |
StErr |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T3,T20 |
default |
- |
- |
- |
- |
- |
- |
- |
Covered |
T9,T13 |