Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22378268	1		T1	99713		T2	85913		T3	7236
full_word	7867890	1		T1	1055		T2	10613		T3	4793

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30245868	1		T1	100768		T2	96526		T3	12029
auto[TlIntgErrCmd]	94	1		T67	3		T69	5		T212	7
auto[TlIntgErrData]	83	1		T67	3		T69	3		T212	8
auto[TlIntgErrBoth]	113	1		T67	4		T69	2		T212	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25768690	1		T1	99754		T2	85602		T3	8376
auto[1]	4477468	1		T1	1014		T2	10924		T3	3653

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21672367	1		T1	99655		T2	84946		T3	6753
auto[TlIntgErrNone]	partial	auto[1]	705636	1		T1	58		T2	967		T3	483
auto[TlIntgErrNone]	full_word	auto[0]	4096202	1		T1	99		T2	656		T3	1623
auto[TlIntgErrNone]	full_word	auto[1]	3771663	1		T1	956		T2	9957		T3	3170
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T67	2		T69	3		T212	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T69	2		T212	4		T213	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T340	1		T338	1		T342	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T67	1		T229	1		T249	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T67	2		T69	2		T212	4
auto[TlIntgErrData]	partial	auto[1]	40	1		T67	1		T212	3		T213	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T212	1		T341	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T69	1		T249	2		T340	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T67	1		T69	1		T212	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T67	3		T69	1		T212	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T212	1		T339	1		T343	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T249	1		T337	2		T344	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20180	1		T110	511		T67	9		T68	30
full_word	3999846	1		T1	257		T5	17193		T20	23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4019754	1		T1	257		T5	17193		T20	23
auto[TlIntgErrCmd]	91	1		T67	6		T69	5		T212	7
auto[TlIntgErrData]	99	1		T67	2		T69	3		T212	6
auto[TlIntgErrBoth]	82	1		T67	2		T69	1		T212	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3995095	1		T1	257		T5	17193		T20	23
auto[1]	24931	1		T110	508		T67	8		T68	38

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1044	1		T110	73		T68	4		T211	47
auto[TlIntgErrNone]	partial	auto[1]	18896	1		T110	438		T68	26		T211	1380
auto[TlIntgErrNone]	full_word	auto[0]	3993951	1		T1	257		T5	17193		T20	23
auto[TlIntgErrNone]	full_word	auto[1]	5863	1		T110	70		T68	12		T211	454
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T67	1		T69	1		T212	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T67	4		T69	3		T212	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T213	1		T249	1		T339	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T67	1		T69	1		T249	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T67	1		T69	2		T212	3
auto[TlIntgErrData]	partial	auto[1]	53	1		T67	1		T69	1		T212	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T213	2		T229	2		T336	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T229	2		T341	2		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T212	1		T213	2		T229	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T67	2		T69	1		T212	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T286	1		T254	1		T345	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T212	2		T229	1		T344	1