Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1513118388	1509896332	0	0
CheckNGreaterZero_A	4180	4180	0	0
GntImpliesReady_A	1513118388	403700166	0	0
GntImpliesValid_A	1513118388	403700166	0	0
GrantKnown_A	1513118388	1509896332	0	0
IdxKnown_A	1513118388	1509896332	0	0
IndexIsCorrect_A	1513118388	403700166	0	0
NoReadyValidNoGrant_A	1513118388	177859724	0	0
Priority_A	1513118388	428126372	0	0
ReadyAndValidImplyGrant_A	1513118388	403700166	0	0
ReqAndReadyImplyGrant_A	1513118388	403700166	0	0
ReqImpliesValid_A	1513118388	428126372	0	0
ValidKnown_A	1513118388	1509896332	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	1509896332	0	0
T1	814192	813960	0	0
T2	775612	775240	0	0
T3	476648	457908	0	0
T4	7292	7048	0	0
T5	480284	480224	0	0
T6	480368	480296	0	0
T18	4856	4456	0	0
T19	5072	4200	0	0
T20	32696	32096	0	0
T21	465388	465328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4180	4180	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	403700166	0	0
T1	814192	399474	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	84968	0	0
T6	480368	85788	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	82718	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	403700166	0	0
T1	814192	399474	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	84968	0	0
T6	480368	85788	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	82718	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	1509896332	0	0
T1	814192	813960	0	0
T2	775612	775240	0	0
T3	476648	457908	0	0
T4	7292	7048	0	0
T5	480284	480224	0	0
T6	480368	480296	0	0
T18	4856	4456	0	0
T19	5072	4200	0	0
T20	32696	32096	0	0
T21	465388	465328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	1509896332	0	0
T1	814192	813960	0	0
T2	775612	775240	0	0
T3	476648	457908	0	0
T4	7292	7048	0	0
T5	480284	480224	0	0
T6	480368	480296	0	0
T18	4856	4456	0	0
T19	5072	4200	0	0
T20	32696	32096	0	0
T21	465388	465328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	403700166	0	0
T1	814192	399474	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	84968	0	0
T6	480368	85788	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	82718	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	177859724	0	0
T1	814192	1584	0	0
T2	775612	256	0	0
T3	476648	23504	0	0
T4	7292	290	0	0
T5	480284	2567942	0	0
T6	480368	2567870	0	0
T18	4856	256	0	0
T19	5072	528	0	0
T20	32696	1180	0	0
T21	465388	2506888	0	0
T22	0	1078	0	0
T26	0	116	0	0
T42	0	22478	0	0
T46	0	24	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	428126372	0	0
T1	814192	399580	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	649000	0	0
T6	480368	639860	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	585906	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	403700166	0	0
T1	814192	399474	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	84968	0	0
T6	480368	85788	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	82718	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	403700166	0	0
T1	814192	399474	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	84968	0	0
T6	480368	85788	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	82718	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	428126372	0	0
T1	814192	399580	0	0
T2	775612	342412	0	0
T3	476648	86974	0	0
T4	7292	718	0	0
T5	480284	649000	0	0
T6	480368	639860	0	0
T18	4856	64	0	0
T19	5072	132	0	0
T20	32696	9798	0	0
T21	465388	585906	0	0
T22	0	61486	0	0
T26	0	434	0	0
T46	0	818	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1513118388	1509896332	0	0
T1	814192	813960	0	0
T2	775612	775240	0	0
T3	476648	457908	0	0
T4	7292	7048	0	0
T5	480284	480224	0	0
T6	480368	480296	0	0
T18	4856	4456	0	0
T19	5072	4200	0	0
T20	32696	32096	0	0
T21	465388	465328	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378279597	377474083	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	378279597	108152782	0	0
GntImpliesValid_A	378279597	108152782	0	0
GrantKnown_A	378279597	377474083	0	0
IdxKnown_A	378279597	377474083	0	0
IndexIsCorrect_A	378279597	108152782	0	0
NoReadyValidNoGrant_A	378279597	46078917	0	0
Priority_A	378279597	114255750	0	0
ReadyAndValidImplyGrant_A	378279597	108152782	0	0
ReqAndReadyImplyGrant_A	378279597	108152782	0	0
ReqImpliesValid_A	378279597	114255750	0	0
ValidKnown_A	378279597	377474083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152782	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152782	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152782	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	46078917	0	0
T1	203548	549	0	0
T2	193903	128	0	0
T3	119162	11752	0	0
T4	1823	138	0	0
T5	120071	595033	0	0
T6	120092	566819	0	0
T18	1214	128	0	0
T19	1268	264	0	0
T20	8174	537	0	0
T21	116347	662443	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	114255750	0	0
T1	203548	68551	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	174379	0	0
T6	120092	171669	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	145624	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152782	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152782	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	114255750	0	0
T1	203548	68551	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	174379	0	0
T6	120092	171669	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	145624	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378279597	377474083	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	378279597	108152699	0	0
GntImpliesValid_A	378279597	108152699	0	0
GrantKnown_A	378279597	377474083	0	0
IdxKnown_A	378279597	377474083	0	0
IndexIsCorrect_A	378279597	108152699	0	0
NoReadyValidNoGrant_A	378279597	46078917	0	0
Priority_A	378279597	114255667	0	0
ReadyAndValidImplyGrant_A	378279597	108152699	0	0
ReqAndReadyImplyGrant_A	378279597	108152699	0	0
ReqImpliesValid_A	378279597	114255667	0	0
ValidKnown_A	378279597	377474083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152699	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152699	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152699	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	46078917	0	0
T1	203548	549	0	0
T2	193903	128	0	0
T3	119162	11752	0	0
T4	1823	138	0	0
T5	120071	595033	0	0
T6	120092	566819	0	0
T18	1214	128	0	0
T19	1268	264	0	0
T20	8174	537	0	0
T21	116347	662443	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	114255667	0	0
T1	203548	68551	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	174379	0	0
T6	120092	171669	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	145624	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152699	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	108152699	0	0
T1	203548	68498	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	19729	0	0
T6	120092	19027	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	21722	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	114255667	0	0
T1	203548	68551	0	0
T2	193903	71066	0	0
T3	119162	43487	0	0
T4	1823	98	0	0
T5	120071	174379	0	0
T6	120092	171669	0	0
T18	1214	32	0	0
T19	1268	66	0	0
T20	8174	3053	0	0
T21	116347	145624	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378279597	377474083	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	378279597	93697385	0	0
GntImpliesValid_A	378279597	93697385	0	0
GrantKnown_A	378279597	377474083	0	0
IdxKnown_A	378279597	377474083	0	0
IndexIsCorrect_A	378279597	93697385	0	0
NoReadyValidNoGrant_A	378279597	42850945	0	0
Priority_A	378279597	99807520	0	0
ReadyAndValidImplyGrant_A	378279597	93697385	0	0
ReqAndReadyImplyGrant_A	378279597	93697385	0	0
ReqImpliesValid_A	378279597	99807520	0	0
ValidKnown_A	378279597	377474083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697385	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697385	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697385	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	42850945	0	0
T1	203548	243	0	0
T2	193903	0	0	0
T3	119162	0	0	0
T4	1823	7	0	0
T5	120071	688938	0	0
T6	120092	717116	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	53	0	0
T21	116347	591001	0	0
T22	0	539	0	0
T26	0	58	0	0
T42	0	11239	0	0
T46	0	12	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	99807520	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	150121	0	0
T6	120092	148261	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	147329	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697385	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697385	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	99807520	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	150121	0	0
T6	120092	148261	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	147329	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T6
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378279597	377474083	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	378279597	93697300	0	0
GntImpliesValid_A	378279597	93697300	0	0
GrantKnown_A	378279597	377474083	0	0
IdxKnown_A	378279597	377474083	0	0
IndexIsCorrect_A	378279597	93697300	0	0
NoReadyValidNoGrant_A	378279597	42850945	0	0
Priority_A	378279597	99807435	0	0
ReadyAndValidImplyGrant_A	378279597	93697300	0	0
ReqAndReadyImplyGrant_A	378279597	93697300	0	0
ReqImpliesValid_A	378279597	99807435	0	0
ValidKnown_A	378279597	377474083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697300	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697300	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697300	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	42850945	0	0
T1	203548	243	0	0
T2	193903	0	0	0
T3	119162	0	0	0
T4	1823	7	0	0
T5	120071	688938	0	0
T6	120092	717116	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	53	0	0
T21	116347	591001	0	0
T22	0	539	0	0
T26	0	58	0	0
T42	0	11239	0	0
T46	0	12	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	99807435	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	150121	0	0
T6	120092	148261	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	147329	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697300	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	93697300	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	22755	0	0
T6	120092	23867	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	19637	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	99807435	0	0
T1	203548	131239	0	0
T2	193903	100140	0	0
T3	119162	0	0	0
T4	1823	261	0	0
T5	120071	150121	0	0
T6	120092	148261	0	0
T18	1214	0	0	0
T19	1268	0	0	0
T20	8174	1846	0	0
T21	116347	147329	0	0
T22	0	30743	0	0
T26	0	217	0	0
T46	0	409	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378279597	377474083	0	0
T1	203548	203490	0	0
T2	193903	193810	0	0
T3	119162	114477	0	0
T4	1823	1762	0	0
T5	120071	120056	0	0
T6	120092	120074	0	0
T18	1214	1114	0	0
T19	1268	1050	0	0
T20	8174	8024	0	0
T21	116347	116332	0	0