Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 95.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 95.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_data_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_data_intg_chk.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_data_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_data_intg_chk


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_secded_inv_39_32_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T1,T3,T19 Yes T1,T3,T19 OUTPUT
err_o[1:0] Yes Yes T1,T3,T19 Yes T1,T3,T19 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk
TotalCoveredPercent
Totals 4 2 50.00
Total Bits 160 152 95.00
Total Bits 0->1 80 76 95.00
Total Bits 1->0 80 76 95.00

Ports 4 2 50.00
Port Bits 160 152 95.00
Port Bits 0->1 80 76 95.00
Port Bits 1->0 80 76 95.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[0] No No No OUTPUT
syndrome_o[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
syndrome_o[2] No No No OUTPUT
syndrome_o[3] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
syndrome_o[4] No No No OUTPUT
syndrome_o[6:5] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
err_o[1] No No No OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_core.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T3,T19,T22 Yes T3,T19,T22 OUTPUT
err_o[1:0] Yes Yes T3,T19,T22 Yes T3,T19,T22 OUTPUT

Toggle Coverage for Instance : tb.dut.u_flash_hw_if.u_data_intg_chk.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T120,T167,T275 Yes T120,T167,T275 OUTPUT
err_o[1:0] Yes Yes T120,T119,T167 Yes T120,T119,T167 OUTPUT

Toggle Coverage for Instance : tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T3,T5 Yes T1,T3,T4 INPUT
data_o[31:0] Yes Yes T1,T3,T5 Yes T1,T3,T4 OUTPUT
syndrome_o[6:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 OUTPUT
err_o[1:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.u_tlul_data_integ_dec.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T3,T5,T26 Yes T2,T3,T5 INPUT
data_o[31:0] Yes Yes T3,T5,T26 Yes T2,T3,T5 OUTPUT
syndrome_o[6:0] Yes Yes T2,T3,T41 Yes T3,T26,T46 OUTPUT
err_o[1:0] Yes Yes T3,T41,T55 Yes T3,T26,T42 OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_data_intg_chk.u_data_chk
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
data_i[38:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
data_o[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
syndrome_o[6:0] Yes Yes T173,T174,T271 Yes T173,T174,T271 OUTPUT
err_o[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

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