Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	30570513	1		T1	154506		T2	201		T3	65
full_word	7870365	1		T1	32381		T2	50		T3	42

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	38440568	1		T1	186887		T2	251		T3	107
auto[TlIntgErrCmd]	112	1		T66	4		T217	5		T218	9
auto[TlIntgErrData]	100	1		T66	8		T217	4		T218	7
auto[TlIntgErrBoth]	98	1		T66	8		T217	1		T218	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33825642	1		T1	167062		T2	201		T3	60
auto[1]	4615236	1		T1	19825		T2	50		T3	47

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	29896937	1		T1	151530		T2	195		T3	59
auto[TlIntgErrNone]	partial	auto[1]	673293	1		T1	2976		T2	6		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	3928573	1		T1	15532		T2	6		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3941765	1		T1	16849		T2	44		T3	41
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T217	3		T218	5		T255	5
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T66	4		T217	2		T218	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T325	1		T327	1		T326	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T218	1		T324	1		T328	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T66	4		T217	1		T218	3
auto[TlIntgErrData]	partial	auto[1]	46	1		T66	4		T217	2		T218	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T218	1		T327	1		T329	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T217	1		T247	1		T330	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T66	1		T218	2		T255	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1		T66	6		T218	2		T255	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T66	1		T217	1		T324	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T256	1		T258	1		T247	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18547	1		T103	921		T104	1124		T107	473
full_word	4083611	1		T1	27180		T9	24		T7	271

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4101872	1		T1	27180		T9	24		T7	271
auto[TlIntgErrCmd]	79	1		T66	6		T218	6		T255	6
auto[TlIntgErrData]	108	1		T66	6		T217	5		T218	4
auto[TlIntgErrBoth]	99	1		T66	7		T217	5		T218	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4077983	1		T1	27180		T9	24		T7	271
auto[1]	24175	1		T103	1425		T104	1422		T107	587

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1093	1		T103	13		T104	51		T107	19
auto[TlIntgErrNone]	partial	auto[1]	17195	1		T103	908		T104	1073		T107	454
auto[TlIntgErrNone]	full_word	auto[0]	4076769	1		T1	27180		T9	24		T7	271
auto[TlIntgErrNone]	full_word	auto[1]	6815	1		T103	517		T104	349		T107	133
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T66	1		T218	2		T255	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T66	5		T218	4		T255	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T255	1		T326	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T256	2		T325	1		T329	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T66	3		T217	3		T218	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T66	2		T217	1		T218	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T66	1		T217	1		T325	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T258	1		T331	1		T324	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T66	2		T217	1		T218	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T66	5		T217	4		T218	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T247	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T218	1		T324	1		T326	2