Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1488601028	1485135372	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1488601028	421714633	0	0
GntImpliesValid_A	1488601028	421714633	0	0
GrantKnown_A	1488601028	1485135372	0	0
IdxKnown_A	1488601028	1485135372	0	0
IndexIsCorrect_A	1488601028	421714633	0	0
NoReadyValidNoGrant_A	1488601028	173018105	0	0
Priority_A	1488601028	446189758	0	0
ReadyAndValidImplyGrant_A	1488601028	421714633	0	0
ReqAndReadyImplyGrant_A	1488601028	421714633	0	0
ReqImpliesValid_A	1488601028	446189758	0	0
ValidKnown_A	1488601028	1485135372	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	1485135372	0	0
T1	1513300	1513000	0	0
T2	4996	4776	0	0
T3	5208	4160	0	0
T4	570836	570812	0	0
T7	35332	35124	0	0
T8	1624784	1624528	0	0
T9	29336	28756	0	0
T13	3926524	3925744	0	0
T18	11828	11552	0	0
T19	3848	3636	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	421714633	0	0
T1	1513300	502544	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1456	0	0
T8	1624784	521594	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37946	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	421714633	0	0
T1	1513300	502544	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1456	0	0
T8	1624784	521594	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37946	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	1485135372	0	0
T1	1513300	1513000	0	0
T2	4996	4776	0	0
T3	5208	4160	0	0
T4	570836	570812	0	0
T7	35332	35124	0	0
T8	1624784	1624528	0	0
T9	29336	28756	0	0
T13	3926524	3925744	0	0
T18	11828	11552	0	0
T19	3848	3636	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	1485135372	0	0
T1	1513300	1513000	0	0
T2	4996	4776	0	0
T3	5208	4160	0	0
T4	570836	570812	0	0
T7	35332	35124	0	0
T8	1624784	1624528	0	0
T9	29336	28756	0	0
T13	3926524	3925744	0	0
T18	11828	11552	0	0
T19	3848	3636	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	421714633	0	0
T1	1513300	502544	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1456	0	0
T8	1624784	521594	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37946	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	173018105	0	0
T1	1513300	190298	0	0
T2	4996	256	0	0
T3	5208	528	0	0
T4	570836	20656	0	0
T5	0	66	0	0
T7	35332	2342	0	0
T8	1624784	213472	0	0
T9	29336	1144	0	0
T13	3926524	384	0	0
T14	0	1790	0	0
T18	11828	256	0	0
T19	3848	256	0	0
T20	0	1674	0	0
T51	0	8	0	0
T60	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	446189758	0	0
T1	1513300	583990	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1458	0	0
T8	1624784	642832	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37966	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	421714633	0	0
T1	1513300	502544	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1456	0	0
T8	1624784	521594	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37946	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	421714633	0	0
T1	1513300	502544	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1456	0	0
T8	1624784	521594	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37946	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	446189758	0	0
T1	1513300	583990	0	0
T2	4996	584	0	0
T3	5208	132	0	0
T4	570836	1859848	0	0
T5	0	34	0	0
T7	35332	1458	0	0
T8	1624784	642832	0	0
T9	29336	8200	0	0
T13	3926524	1438	0	0
T18	11828	64	0	0
T19	3848	64	0	0
T20	0	37966	0	0
T51	0	2	0	0
T59	0	45544	0	0
T60	0	255794	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1488601028	1485135372	0	0
T1	1513300	1513000	0	0
T2	4996	4776	0	0
T3	5208	4160	0	0
T4	570836	570812	0	0
T7	35332	35124	0	0
T8	1624784	1624528	0	0
T9	29336	28756	0	0
T13	3926524	3925744	0	0
T18	11828	11552	0	0
T19	3848	3636	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372150257	371283843	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	372150257	110425311	0	0
GntImpliesValid_A	372150257	110425311	0	0
GrantKnown_A	372150257	371283843	0	0
IdxKnown_A	372150257	371283843	0	0
IndexIsCorrect_A	372150257	110425311	0	0
NoReadyValidNoGrant_A	372150257	44744207	0	0
Priority_A	372150257	116517921	0	0
ReadyAndValidImplyGrant_A	372150257	110425311	0	0
ReqAndReadyImplyGrant_A	372150257	110425311	0	0
ReqImpliesValid_A	372150257	116517921	0	0
ValidKnown_A	372150257	371283843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425311	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425311	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425311	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	44744207	0	0
T1	378325	54630	0	0
T2	1249	128	0	0
T3	1302	264	0	0
T4	142709	5626	0	0
T7	8833	575	0	0
T8	406196	44655	0	0
T9	7334	505	0	0
T13	981631	192	0	0
T18	2957	128	0	0
T19	962	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	116517921	0	0
T1	378325	157726	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	122813	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425311	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425311	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	116517921	0	0
T1	378325	157726	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	122813	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372150257	371283843	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	372150257	110425238	0	0
GntImpliesValid_A	372150257	110425238	0	0
GrantKnown_A	372150257	371283843	0	0
IdxKnown_A	372150257	371283843	0	0
IndexIsCorrect_A	372150257	110425238	0	0
NoReadyValidNoGrant_A	372150257	44744146	0	0
Priority_A	372150257	116517909	0	0
ReadyAndValidImplyGrant_A	372150257	110425238	0	0
ReqAndReadyImplyGrant_A	372150257	110425238	0	0
ReqImpliesValid_A	372150257	116517909	0	0
ValidKnown_A	372150257	371283843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425238	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425238	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425238	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	44744146	0	0
T1	378325	54630	0	0
T2	1249	128	0	0
T3	1302	264	0	0
T4	142709	5626	0	0
T7	8833	575	0	0
T8	406196	44655	0	0
T9	7334	505	0	0
T13	981631	192	0	0
T18	2957	128	0	0
T19	962	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	116517909	0	0
T1	378325	157726	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	122813	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425238	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	110425238	0	0
T1	378325	139104	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	99190	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	116517909	0	0
T1	378325	157726	0	0
T2	1249	292	0	0
T3	1302	66	0	0
T4	142709	362788	0	0
T7	8833	332	0	0
T8	406196	122813	0	0
T9	7334	2775	0	0
T13	981631	719	0	0
T18	2957	32	0	0
T19	962	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T9,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T7
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T9,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T4,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T4,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372150257	371283843	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	372150257	100432042	0	0
GntImpliesValid_A	372150257	100432042	0	0
GrantKnown_A	372150257	371283843	0	0
IdxKnown_A	372150257	371283843	0	0
IndexIsCorrect_A	372150257	100432042	0	0
NoReadyValidNoGrant_A	372150257	41764876	0	0
Priority_A	372150257	106576964	0	0
ReadyAndValidImplyGrant_A	372150257	100432042	0	0
ReqAndReadyImplyGrant_A	372150257	100432042	0	0
ReqImpliesValid_A	372150257	106576964	0	0
ValidKnown_A	372150257	371283843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	41764876	0	0
T1	378325	40519	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	4702	0	0
T5	0	33	0	0
T7	8833	596	0	0
T8	406196	62081	0	0
T9	7334	67	0	0
T13	981631	0	0	0
T14	0	895	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	837	0	0
T51	0	4	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	106576964	0	0
T1	378325	134269	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	397	0	0
T8	406196	198603	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18983	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	106576964	0	0
T1	378325	134269	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	397	0	0
T8	406196	198603	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18983	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T9
1	0	Covered	T1,T9,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T9,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T7
1	0	Covered	T1,T4,T9
1	1	Covered	T1,T9,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T4,T9

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T7
1	1	Covered	T1,T4,T9

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T9,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	372150257	371283843	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	372150257	100432042	0	0
GntImpliesValid_A	372150257	100432042	0	0
GrantKnown_A	372150257	371283843	0	0
IdxKnown_A	372150257	371283843	0	0
IndexIsCorrect_A	372150257	100432042	0	0
NoReadyValidNoGrant_A	372150257	41764876	0	0
Priority_A	372150257	106576964	0	0
ReadyAndValidImplyGrant_A	372150257	100432042	0	0
ReqAndReadyImplyGrant_A	372150257	100432042	0	0
ReqImpliesValid_A	372150257	106576964	0	0
ValidKnown_A	372150257	371283843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	41764876	0	0
T1	378325	40519	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	4702	0	0
T5	0	33	0	0
T7	8833	596	0	0
T8	406196	62081	0	0
T9	7334	67	0	0
T13	981631	0	0	0
T14	0	895	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	837	0	0
T51	0	4	0	0
T60	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	106576964	0	0
T1	378325	134269	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	397	0	0
T8	406196	198603	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18983	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	100432042	0	0
T1	378325	112168	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	396	0	0
T8	406196	161607	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18973	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	106576964	0	0
T1	378325	134269	0	0
T2	1249	0	0	0
T3	1302	0	0	0
T4	142709	567136	0	0
T5	0	17	0	0
T7	8833	397	0	0
T8	406196	198603	0	0
T9	7334	1325	0	0
T13	981631	0	0	0
T18	2957	0	0	0
T19	962	0	0	0
T20	0	18983	0	0
T51	0	1	0	0
T59	0	22772	0	0
T60	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372150257	371283843	0	0
T1	378325	378250	0	0
T2	1249	1194	0	0
T3	1302	1040	0	0
T4	142709	142703	0	0
T7	8833	8781	0	0
T8	406196	406132	0	0
T9	7334	7189	0	0
T13	981631	981436	0	0
T18	2957	2888	0	0
T19	962	909	0	0