Module Definition
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Module Instance : tb.dut.gen_alert_senders[4].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.78 77.78


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
alert_ack_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_state_o Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[4].u_alert_sender
TotalCoveredPercent
Totals 9 7 77.78
Total Bits 18 14 77.78
Total Bits 0->1 9 7 77.78
Total Bits 1->0 9 7 77.78

Ports 9 7 77.78
Port Bits 18 14 77.78
Port Bits 0->1 9 7 77.78
Port Bits 1->0 9 7 77.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Unreachable Unreachable Unreachable INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T18,T96,T97 Yes T18,T96,T97 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Yes Yes T1,T4,T9 Yes T1,T4,T9 INPUT
alert_ack_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_state_o Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T1,T4,T9 Yes T1,T4,T9 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T1,T4,T9 Yes T1,T4,T9 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Yes Yes T13,T14,T147 Yes T13,T14,T147 INPUT
alert_ack_o Yes Yes T13,T14,T160 Yes T13,T14,T160 OUTPUT
alert_state_o Yes Yes T13,T14,T147 Yes T13,T14,T147 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T18,T13,T96 Yes T18,T13,T96 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T18,T13,T96 Yes T18,T13,T96 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Yes Yes T3,T13,T5 Yes T1,T3,T13 INPUT
alert_ack_o Yes Yes T1,T13,T5 Yes T1,T13,T5 OUTPUT
alert_state_o Yes Yes T1,T3,T13 Yes T1,T3,T13 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T1,T3,T18 Yes T1,T3,T18 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T1,T3,T18 Yes T1,T3,T18 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T9,T13 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_req_i Yes Yes T14,T16,T17 Yes T14,T16,T17 INPUT
alert_ack_o Yes Yes T66,T217,T218 Yes T66,T217,T218 OUTPUT
alert_state_o Yes Yes T14,T16,T17 Yes T14,T16,T17 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T18,T96,T97 Yes T18,T96,T97 INPUT
alert_rx_i.ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i.ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T18,T96,T14 Yes T18,T96,T14 OUTPUT

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