| T1072 |
/workspace/coverage/default/67.flash_ctrl_otp_reset.3154577135 |
|
|
Jul 10 07:30:22 PM PDT 24 |
Jul 10 07:32:36 PM PDT 24 |
129779000 ps |
| T174 |
/workspace/coverage/default/4.flash_ctrl_mid_op_rst.944058092 |
|
|
Jul 10 07:24:48 PM PDT 24 |
Jul 10 07:26:02 PM PDT 24 |
1478087500 ps |
| T1073 |
/workspace/coverage/default/40.flash_ctrl_sec_info_access.1409907885 |
|
|
Jul 10 07:29:33 PM PDT 24 |
Jul 10 07:30:55 PM PDT 24 |
6725674300 ps |
| T1074 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.2020168200 |
|
|
Jul 10 07:24:21 PM PDT 24 |
Jul 10 07:25:27 PM PDT 24 |
8265637200 ps |
| T1075 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3463319791 |
|
|
Jul 10 07:24:39 PM PDT 24 |
Jul 10 07:24:54 PM PDT 24 |
26504100 ps |
| T1076 |
/workspace/coverage/default/5.flash_ctrl_otp_reset.844363209 |
|
|
Jul 10 07:24:58 PM PDT 24 |
Jul 10 07:27:15 PM PDT 24 |
171368000 ps |
| T1077 |
/workspace/coverage/default/19.flash_ctrl_wo.1791866208 |
|
|
Jul 10 07:27:35 PM PDT 24 |
Jul 10 07:31:36 PM PDT 24 |
2602056600 ps |
| T1078 |
/workspace/coverage/default/15.flash_ctrl_wo.2154840405 |
|
|
Jul 10 07:26:48 PM PDT 24 |
Jul 10 07:29:38 PM PDT 24 |
7403549000 ps |
| T1079 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.1818742747 |
|
|
Jul 10 07:28:55 PM PDT 24 |
Jul 10 07:29:26 PM PDT 24 |
107120200 ps |
| T1080 |
/workspace/coverage/default/23.flash_ctrl_disable.3922939080 |
|
|
Jul 10 07:28:13 PM PDT 24 |
Jul 10 07:28:36 PM PDT 24 |
10173700 ps |
| T1081 |
/workspace/coverage/default/5.flash_ctrl_connect.3207927759 |
|
|
Jul 10 07:24:58 PM PDT 24 |
Jul 10 07:25:16 PM PDT 24 |
50736300 ps |
| T1082 |
/workspace/coverage/default/5.flash_ctrl_error_mp.2182651074 |
|
|
Jul 10 07:24:58 PM PDT 24 |
Jul 10 08:03:13 PM PDT 24 |
5837465300 ps |
| T1083 |
/workspace/coverage/default/4.flash_ctrl_disable.2227602066 |
|
|
Jul 10 07:24:51 PM PDT 24 |
Jul 10 07:25:19 PM PDT 24 |
31908000 ps |
| T1084 |
/workspace/coverage/default/28.flash_ctrl_smoke.2371581027 |
|
|
Jul 10 07:28:40 PM PDT 24 |
Jul 10 07:30:16 PM PDT 24 |
79586100 ps |
| T1085 |
/workspace/coverage/default/12.flash_ctrl_connect.1576834968 |
|
|
Jul 10 07:26:12 PM PDT 24 |
Jul 10 07:26:29 PM PDT 24 |
60118200 ps |
| T1086 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.813248455 |
|
|
Jul 10 07:24:21 PM PDT 24 |
Jul 10 07:25:49 PM PDT 24 |
1635414100 ps |
| T1087 |
/workspace/coverage/default/79.flash_ctrl_connect.2980944719 |
|
|
Jul 10 07:30:30 PM PDT 24 |
Jul 10 07:30:45 PM PDT 24 |
25451400 ps |
| T1088 |
/workspace/coverage/default/43.flash_ctrl_smoke.905350337 |
|
|
Jul 10 07:29:42 PM PDT 24 |
Jul 10 07:30:58 PM PDT 24 |
23837900 ps |
| T1089 |
/workspace/coverage/default/2.flash_ctrl_host_addr_infection.3071762975 |
|
|
Jul 10 07:24:51 PM PDT 24 |
Jul 10 07:25:26 PM PDT 24 |
39463800 ps |
| T1090 |
/workspace/coverage/default/9.flash_ctrl_error_prog_win.3633512792 |
|
|
Jul 10 07:25:48 PM PDT 24 |
Jul 10 07:41:34 PM PDT 24 |
392506400 ps |
| T1091 |
/workspace/coverage/default/6.flash_ctrl_error_mp.2736169619 |
|
|
Jul 10 07:25:02 PM PDT 24 |
Jul 10 08:05:16 PM PDT 24 |
20485774500 ps |
| T1092 |
/workspace/coverage/default/42.flash_ctrl_sec_info_access.2987539748 |
|
|
Jul 10 07:29:40 PM PDT 24 |
Jul 10 07:30:55 PM PDT 24 |
9571916300 ps |
| T1093 |
/workspace/coverage/default/29.flash_ctrl_disable.2597175944 |
|
|
Jul 10 07:28:34 PM PDT 24 |
Jul 10 07:28:56 PM PDT 24 |
39464900 ps |
| T1094 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.737225465 |
|
|
Jul 10 07:24:46 PM PDT 24 |
Jul 10 07:27:23 PM PDT 24 |
2230801500 ps |
| T1095 |
/workspace/coverage/default/70.flash_ctrl_connect.2988780637 |
|
|
Jul 10 07:30:29 PM PDT 24 |
Jul 10 07:30:43 PM PDT 24 |
27168200 ps |
| T1096 |
/workspace/coverage/default/15.flash_ctrl_otp_reset.2054210904 |
|
|
Jul 10 07:26:47 PM PDT 24 |
Jul 10 07:28:36 PM PDT 24 |
75084800 ps |
| T1097 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.374355716 |
|
|
Jul 10 07:24:55 PM PDT 24 |
Jul 10 07:25:21 PM PDT 24 |
33956700 ps |
| T195 |
/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3827891570 |
|
|
Jul 10 07:24:27 PM PDT 24 |
Jul 10 07:55:36 PM PDT 24 |
1180331751800 ps |
| T1098 |
/workspace/coverage/default/21.flash_ctrl_connect.4052205785 |
|
|
Jul 10 07:28:00 PM PDT 24 |
Jul 10 07:28:18 PM PDT 24 |
18701000 ps |
| T1099 |
/workspace/coverage/default/40.flash_ctrl_smoke.2990700263 |
|
|
Jul 10 07:29:32 PM PDT 24 |
Jul 10 07:30:49 PM PDT 24 |
87023400 ps |
| T1100 |
/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3542091125 |
|
|
Jul 10 07:24:54 PM PDT 24 |
Jul 10 07:25:31 PM PDT 24 |
39851500 ps |
| T1101 |
/workspace/coverage/default/3.flash_ctrl_alert_test.2804579363 |
|
|
Jul 10 07:24:44 PM PDT 24 |
Jul 10 07:24:59 PM PDT 24 |
102601400 ps |
| T1102 |
/workspace/coverage/default/14.flash_ctrl_phy_arb.3005735626 |
|
|
Jul 10 07:26:38 PM PDT 24 |
Jul 10 07:35:55 PM PDT 24 |
1396822800 ps |
| T1103 |
/workspace/coverage/default/12.flash_ctrl_ro.3104822850 |
|
|
Jul 10 07:26:14 PM PDT 24 |
Jul 10 07:28:09 PM PDT 24 |
1343863100 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_prog_reset.2402238464 |
|
|
Jul 10 07:24:29 PM PDT 24 |
Jul 10 07:28:09 PM PDT 24 |
2635106000 ps |
| T1105 |
/workspace/coverage/default/1.flash_ctrl_error_prog_win.450930995 |
|
|
Jul 10 07:24:26 PM PDT 24 |
Jul 10 07:37:52 PM PDT 24 |
1888279500 ps |
| T1106 |
/workspace/coverage/default/1.flash_ctrl_wo.4269501637 |
|
|
Jul 10 07:24:27 PM PDT 24 |
Jul 10 07:28:17 PM PDT 24 |
15225645900 ps |
| T359 |
/workspace/coverage/default/3.flash_ctrl_sec_info_access.419262493 |
|
|
Jul 10 07:24:50 PM PDT 24 |
Jul 10 07:26:14 PM PDT 24 |
2336978900 ps |
| T1107 |
/workspace/coverage/default/25.flash_ctrl_connect.605682056 |
|
|
Jul 10 07:34:30 PM PDT 24 |
Jul 10 07:34:47 PM PDT 24 |
27313300 ps |
| T1108 |
/workspace/coverage/default/6.flash_ctrl_connect.1026301787 |
|
|
Jul 10 07:25:20 PM PDT 24 |
Jul 10 07:25:39 PM PDT 24 |
74315800 ps |
| T379 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.3056070473 |
|
|
Jul 10 07:27:27 PM PDT 24 |
Jul 10 07:29:05 PM PDT 24 |
3032273500 ps |
| T1109 |
/workspace/coverage/default/0.flash_ctrl_intr_rd.390902415 |
|
|
Jul 10 07:24:15 PM PDT 24 |
Jul 10 07:27:53 PM PDT 24 |
1701922600 ps |
| T1110 |
/workspace/coverage/default/39.flash_ctrl_connect.3808983873 |
|
|
Jul 10 07:29:31 PM PDT 24 |
Jul 10 07:29:45 PM PDT 24 |
14661700 ps |
| T1111 |
/workspace/coverage/default/21.flash_ctrl_sec_info_access.4202553712 |
|
|
Jul 10 07:28:02 PM PDT 24 |
Jul 10 07:28:59 PM PDT 24 |
1361331700 ps |
| T1112 |
/workspace/coverage/default/23.flash_ctrl_alert_test.2567351867 |
|
|
Jul 10 07:28:13 PM PDT 24 |
Jul 10 07:28:28 PM PDT 24 |
58957100 ps |
| T1113 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2170998666 |
|
|
Jul 10 07:26:26 PM PDT 24 |
Jul 10 07:26:40 PM PDT 24 |
15462200 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2725507449 |
|
|
Jul 10 06:28:48 PM PDT 24 |
Jul 10 06:29:39 PM PDT 24 |
2084237700 ps |
| T243 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3272614965 |
|
|
Jul 10 06:29:34 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
16054200 ps |
| T103 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1867145498 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
274380600 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1238588311 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
509451700 ps |
| T107 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1115256007 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:29:21 PM PDT 24 |
68977000 ps |
| T244 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3395732811 |
|
|
Jul 10 06:29:40 PM PDT 24 |
Jul 10 06:29:55 PM PDT 24 |
29184400 ps |
| T245 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1603257875 |
|
|
Jul 10 06:29:21 PM PDT 24 |
Jul 10 06:29:37 PM PDT 24 |
85134900 ps |
| T1114 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2714553310 |
|
|
Jul 10 06:28:50 PM PDT 24 |
Jul 10 06:29:07 PM PDT 24 |
16193500 ps |
| T1115 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1142857880 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:01 PM PDT 24 |
13434800 ps |
| T65 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.944478236 |
|
|
Jul 10 06:28:50 PM PDT 24 |
Jul 10 06:29:26 PM PDT 24 |
8915180200 ps |
| T205 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2123515985 |
|
|
Jul 10 06:28:57 PM PDT 24 |
Jul 10 06:29:17 PM PDT 24 |
152385800 ps |
| T206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.233005483 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:04 PM PDT 24 |
28104200 ps |
| T317 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1581067030 |
|
|
Jul 10 06:29:08 PM PDT 24 |
Jul 10 06:29:23 PM PDT 24 |
62843500 ps |
| T318 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.4107389207 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:26 PM PDT 24 |
16277200 ps |
| T66 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2258677049 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:44:25 PM PDT 24 |
1667284400 ps |
| T105 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1706022867 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:29:32 PM PDT 24 |
75032500 ps |
| T106 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3703961746 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:30 PM PDT 24 |
83319900 ps |
| T319 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2184668153 |
|
|
Jul 10 06:29:39 PM PDT 24 |
Jul 10 06:29:55 PM PDT 24 |
53365000 ps |
| T237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2344181406 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:22 PM PDT 24 |
62494900 ps |
| T1116 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.402799244 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
37928100 ps |
| T1117 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.215707381 |
|
|
Jul 10 06:29:16 PM PDT 24 |
Jul 10 06:29:32 PM PDT 24 |
57809900 ps |
| T321 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3052076842 |
|
|
Jul 10 06:28:57 PM PDT 24 |
Jul 10 06:29:12 PM PDT 24 |
31632700 ps |
| T238 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1007272646 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:29:32 PM PDT 24 |
29632900 ps |
| T217 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3729574757 |
|
|
Jul 10 06:29:11 PM PDT 24 |
Jul 10 06:36:51 PM PDT 24 |
444260400 ps |
| T218 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3279796396 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:41:41 PM PDT 24 |
947013300 ps |
| T282 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.365931604 |
|
|
Jul 10 06:28:57 PM PDT 24 |
Jul 10 06:29:18 PM PDT 24 |
780019100 ps |
| T283 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1142887362 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:17 PM PDT 24 |
66799000 ps |
| T1118 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3690230938 |
|
|
Jul 10 06:29:19 PM PDT 24 |
Jul 10 06:29:38 PM PDT 24 |
14620800 ps |
| T1119 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3532226306 |
|
|
Jul 10 06:29:33 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
16307900 ps |
| T1120 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2782247074 |
|
|
Jul 10 06:29:08 PM PDT 24 |
Jul 10 06:29:25 PM PDT 24 |
63955700 ps |
| T1121 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4284734170 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:07 PM PDT 24 |
16188400 ps |
| T1122 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3540315348 |
|
|
Jul 10 06:29:16 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
20291900 ps |
| T219 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.76831930 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:18 PM PDT 24 |
727510500 ps |
| T1123 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3713553784 |
|
|
Jul 10 06:29:21 PM PDT 24 |
Jul 10 06:29:40 PM PDT 24 |
1562676900 ps |
| T1124 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2046054075 |
|
|
Jul 10 06:28:39 PM PDT 24 |
Jul 10 06:29:27 PM PDT 24 |
2182124200 ps |
| T1125 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3454106996 |
|
|
Jul 10 06:29:21 PM PDT 24 |
Jul 10 06:29:40 PM PDT 24 |
120977200 ps |
| T284 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2587704818 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:33 PM PDT 24 |
138439700 ps |
| T1126 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4165685462 |
|
|
Jul 10 06:29:07 PM PDT 24 |
Jul 10 06:29:21 PM PDT 24 |
15025700 ps |
| T1127 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4095276008 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
46993900 ps |
| T1128 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2396385813 |
|
|
Jul 10 06:28:39 PM PDT 24 |
Jul 10 06:28:55 PM PDT 24 |
20256000 ps |
| T220 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1059300088 |
|
|
Jul 10 06:28:55 PM PDT 24 |
Jul 10 06:29:14 PM PDT 24 |
44482300 ps |
| T222 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.444659139 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:28:56 PM PDT 24 |
55950700 ps |
| T255 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1501394721 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:44:09 PM PDT 24 |
786822700 ps |
| T1129 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.178357886 |
|
|
Jul 10 06:29:35 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
49602700 ps |
| T1130 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1808264705 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:29:20 PM PDT 24 |
447502500 ps |
| T1131 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4132730413 |
|
|
Jul 10 06:29:35 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
79608500 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1351889910 |
|
|
Jul 10 06:28:49 PM PDT 24 |
Jul 10 06:36:28 PM PDT 24 |
718356300 ps |
| T1132 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3115264149 |
|
|
Jul 10 06:29:33 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
17956000 ps |
| T1133 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1523311833 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:29:31 PM PDT 24 |
21539700 ps |
| T256 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3041481515 |
|
|
Jul 10 06:29:24 PM PDT 24 |
Jul 10 06:42:00 PM PDT 24 |
2838397700 ps |
| T1134 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.321416567 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:04 PM PDT 24 |
167312700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.810695520 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:06 PM PDT 24 |
19331000 ps |
| T258 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1864046251 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:41:17 PM PDT 24 |
3996816900 ps |
| T247 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3475748541 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:44:18 PM PDT 24 |
4014650600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1901071856 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
23615000 ps |
| T240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2068821241 |
|
|
Jul 10 06:28:54 PM PDT 24 |
Jul 10 06:29:10 PM PDT 24 |
57077700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1106632903 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:15 PM PDT 24 |
63235600 ps |
| T223 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3508957248 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:28:55 PM PDT 24 |
34232100 ps |
| T1138 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.76191748 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
45125000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2884312450 |
|
|
Jul 10 06:29:37 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
27381000 ps |
| T241 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.813668250 |
|
|
Jul 10 06:29:16 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
437550400 ps |
| T285 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.886844399 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
247399200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.168062815 |
|
|
Jul 10 06:28:46 PM PDT 24 |
Jul 10 06:29:01 PM PDT 24 |
83108400 ps |
| T1141 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1503365388 |
|
|
Jul 10 06:28:39 PM PDT 24 |
Jul 10 06:28:58 PM PDT 24 |
114723700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1556276341 |
|
|
Jul 10 06:29:07 PM PDT 24 |
Jul 10 06:29:23 PM PDT 24 |
21888800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1938020664 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:28:57 PM PDT 24 |
17354200 ps |
| T286 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3504973353 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:29:01 PM PDT 24 |
78101400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1024129547 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:26 PM PDT 24 |
15899700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2915359943 |
|
|
Jul 10 06:29:27 PM PDT 24 |
Jul 10 06:29:46 PM PDT 24 |
64801900 ps |
| T1146 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4139660421 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:34 PM PDT 24 |
1280731200 ps |
| T1147 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.982371064 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:29:42 PM PDT 24 |
229307500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3340781465 |
|
|
Jul 10 06:28:56 PM PDT 24 |
Jul 10 06:29:10 PM PDT 24 |
33522000 ps |
| T224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1759142111 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:07 PM PDT 24 |
143821300 ps |
| T331 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.693056449 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:36:51 PM PDT 24 |
1092952100 ps |
| T254 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1390259266 |
|
|
Jul 10 06:29:21 PM PDT 24 |
Jul 10 06:29:42 PM PDT 24 |
323315200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3537492649 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:25 PM PDT 24 |
15281500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2231618031 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
45607100 ps |
| T242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1850693020 |
|
|
Jul 10 06:28:57 PM PDT 24 |
Jul 10 06:29:18 PM PDT 24 |
62444200 ps |
| T287 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1165928001 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
366083000 ps |
| T1151 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.178595631 |
|
|
Jul 10 06:29:21 PM PDT 24 |
Jul 10 06:29:37 PM PDT 24 |
118598700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1518019516 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
661267700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3002357654 |
|
|
Jul 10 06:29:06 PM PDT 24 |
Jul 10 06:29:22 PM PDT 24 |
14365200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2831330687 |
|
|
Jul 10 06:29:27 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
25937300 ps |
| T239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3126712413 |
|
|
Jul 10 06:28:37 PM PDT 24 |
Jul 10 06:28:55 PM PDT 24 |
473322500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3194266593 |
|
|
Jul 10 06:28:56 PM PDT 24 |
Jul 10 06:29:11 PM PDT 24 |
38306200 ps |
| T1156 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.314180514 |
|
|
Jul 10 06:29:35 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
52934900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.802678280 |
|
|
Jul 10 06:29:41 PM PDT 24 |
Jul 10 06:29:57 PM PDT 24 |
18419100 ps |
| T1158 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2587167278 |
|
|
Jul 10 06:29:12 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
12754400 ps |
| T1159 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3471028206 |
|
|
Jul 10 06:29:37 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
30950400 ps |
| T1160 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.276948092 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:02 PM PDT 24 |
16780200 ps |
| T1161 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1099102637 |
|
|
Jul 10 06:28:58 PM PDT 24 |
Jul 10 06:29:17 PM PDT 24 |
67523400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3382866732 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:15 PM PDT 24 |
161752200 ps |
| T288 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1035665046 |
|
|
Jul 10 06:28:58 PM PDT 24 |
Jul 10 06:29:19 PM PDT 24 |
385471600 ps |
| T324 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2278204872 |
|
|
Jul 10 06:28:46 PM PDT 24 |
Jul 10 06:43:54 PM PDT 24 |
1245022200 ps |
| T289 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.382221347 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:32 PM PDT 24 |
403958000 ps |
| T1163 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.521659425 |
|
|
Jul 10 06:29:19 PM PDT 24 |
Jul 10 06:29:37 PM PDT 24 |
21098700 ps |
| T290 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2332371923 |
|
|
Jul 10 06:29:08 PM PDT 24 |
Jul 10 06:29:28 PM PDT 24 |
103205100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1395228045 |
|
|
Jul 10 06:29:06 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
183625400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.4070655356 |
|
|
Jul 10 06:28:39 PM PDT 24 |
Jul 10 06:28:57 PM PDT 24 |
13749400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1376762989 |
|
|
Jul 10 06:28:39 PM PDT 24 |
Jul 10 06:29:11 PM PDT 24 |
3473620400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3397072901 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
552920000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.207999350 |
|
|
Jul 10 06:29:33 PM PDT 24 |
Jul 10 06:29:50 PM PDT 24 |
101730400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2284224530 |
|
|
Jul 10 06:29:40 PM PDT 24 |
Jul 10 06:29:56 PM PDT 24 |
18014000 ps |
| T1170 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3848759582 |
|
|
Jul 10 06:29:02 PM PDT 24 |
Jul 10 06:29:20 PM PDT 24 |
54650200 ps |
| T322 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2195882918 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
79185900 ps |
| T1171 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.663419753 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:28:55 PM PDT 24 |
13304000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3892402180 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:29:13 PM PDT 24 |
49486200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3978178151 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:10 PM PDT 24 |
210949400 ps |
| T328 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2473597594 |
|
|
Jul 10 06:29:05 PM PDT 24 |
Jul 10 06:44:20 PM PDT 24 |
9340922000 ps |
| T250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4219202074 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:29:34 PM PDT 24 |
458542100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.812437406 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:05 PM PDT 24 |
226549700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2694187955 |
|
|
Jul 10 06:28:48 PM PDT 24 |
Jul 10 06:29:15 PM PDT 24 |
107907400 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3629427687 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:29:32 PM PDT 24 |
4392419300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3830971321 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:16 PM PDT 24 |
12512400 ps |
| T1178 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4253181778 |
|
|
Jul 10 06:29:39 PM PDT 24 |
Jul 10 06:29:55 PM PDT 24 |
99016100 ps |
| T248 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3644365200 |
|
|
Jul 10 06:29:10 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
125016000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4035185452 |
|
|
Jul 10 06:29:39 PM PDT 24 |
Jul 10 06:29:54 PM PDT 24 |
33495200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2268872709 |
|
|
Jul 10 06:29:25 PM PDT 24 |
Jul 10 06:29:40 PM PDT 24 |
48000600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2085664075 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:44 PM PDT 24 |
108039000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2950464080 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
19097500 ps |
| T1183 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3743656603 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:30 PM PDT 24 |
204495000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.354713977 |
|
|
Jul 10 06:28:51 PM PDT 24 |
Jul 10 06:29:04 PM PDT 24 |
29696200 ps |
| T1185 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3322323080 |
|
|
Jul 10 06:29:34 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
15352000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4039979977 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:34 PM PDT 24 |
346483700 ps |
| T1187 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3315261204 |
|
|
Jul 10 06:29:27 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
420734700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1325981129 |
|
|
Jul 10 06:28:48 PM PDT 24 |
Jul 10 06:29:03 PM PDT 24 |
53800900 ps |
| T251 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1382312999 |
|
|
Jul 10 06:29:24 PM PDT 24 |
Jul 10 06:29:44 PM PDT 24 |
299537300 ps |
| T291 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.163549517 |
|
|
Jul 10 06:28:59 PM PDT 24 |
Jul 10 06:29:41 PM PDT 24 |
9905131200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.339009201 |
|
|
Jul 10 06:29:03 PM PDT 24 |
Jul 10 06:29:23 PM PDT 24 |
103666100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3426986552 |
|
|
Jul 10 06:28:40 PM PDT 24 |
Jul 10 06:28:59 PM PDT 24 |
47643200 ps |
| T325 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2196578242 |
|
|
Jul 10 06:28:36 PM PDT 24 |
Jul 10 06:41:15 PM PDT 24 |
3261092300 ps |
| T1191 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.853683401 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:42 PM PDT 24 |
325222600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2212976653 |
|
|
Jul 10 06:29:35 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
27362900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1105180519 |
|
|
Jul 10 06:29:18 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
54103700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3118765146 |
|
|
Jul 10 06:29:38 PM PDT 24 |
Jul 10 06:29:54 PM PDT 24 |
16357300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1791110579 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:40 PM PDT 24 |
41611700 ps |
| T1196 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1737469903 |
|
|
Jul 10 06:29:42 PM PDT 24 |
Jul 10 06:29:57 PM PDT 24 |
85134500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1300893130 |
|
|
Jul 10 06:28:46 PM PDT 24 |
Jul 10 06:29:22 PM PDT 24 |
671383100 ps |
| T257 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2944653636 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:29:01 PM PDT 24 |
41339500 ps |
| T292 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3186399454 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:29:38 PM PDT 24 |
368549300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1449362812 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:29:19 PM PDT 24 |
18064000 ps |
| T225 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4188245569 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:02 PM PDT 24 |
29300800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1724627358 |
|
|
Jul 10 06:29:33 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
21540100 ps |
| T1200 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1061620737 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:29:30 PM PDT 24 |
157454600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.250220725 |
|
|
Jul 10 06:28:41 PM PDT 24 |
Jul 10 06:28:59 PM PDT 24 |
114063200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2880756266 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:29:28 PM PDT 24 |
56874400 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1917476034 |
|
|
Jul 10 06:28:47 PM PDT 24 |
Jul 10 06:29:09 PM PDT 24 |
61095300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1285973181 |
|
|
Jul 10 06:29:36 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
127875300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1845865830 |
|
|
Jul 10 06:28:48 PM PDT 24 |
Jul 10 06:29:03 PM PDT 24 |
13613700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3689709646 |
|
|
Jul 10 06:29:10 PM PDT 24 |
Jul 10 06:29:28 PM PDT 24 |
224134100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4164425394 |
|
|
Jul 10 06:29:09 PM PDT 24 |
Jul 10 06:29:28 PM PDT 24 |
12734400 ps |
| T1207 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.901904505 |
|
|
Jul 10 06:29:42 PM PDT 24 |
Jul 10 06:29:57 PM PDT 24 |
52900300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2385029655 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:29:38 PM PDT 24 |
44155300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2453601927 |
|
|
Jul 10 06:29:33 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
47689600 ps |
| T253 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.496297451 |
|
|
Jul 10 06:29:19 PM PDT 24 |
Jul 10 06:29:41 PM PDT 24 |
48934100 ps |
| T1210 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3121729191 |
|
|
Jul 10 06:29:11 PM PDT 24 |
Jul 10 06:29:27 PM PDT 24 |
57784800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4047498854 |
|
|
Jul 10 06:28:48 PM PDT 24 |
Jul 10 06:29:05 PM PDT 24 |
28035700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2987369011 |
|
|
Jul 10 06:29:27 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
46077200 ps |
| T1213 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3412359699 |
|
|
Jul 10 06:29:03 PM PDT 24 |
Jul 10 06:29:20 PM PDT 24 |
24424100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1003680287 |
|
|
Jul 10 06:29:35 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
19953500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.727434171 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:34 PM PDT 24 |
159603100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2622592166 |
|
|
Jul 10 06:29:34 PM PDT 24 |
Jul 10 06:29:51 PM PDT 24 |
27496500 ps |
| T249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2561807317 |
|
|
Jul 10 06:29:10 PM PDT 24 |
Jul 10 06:29:31 PM PDT 24 |
102166200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.622591732 |
|
|
Jul 10 06:29:37 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
26866100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3990713057 |
|
|
Jul 10 06:29:08 PM PDT 24 |
Jul 10 06:29:29 PM PDT 24 |
345240000 ps |
| T293 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1763344455 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
3101298700 ps |
| T1219 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2483589243 |
|
|
Jul 10 06:29:22 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
61600700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3630150299 |
|
|
Jul 10 06:28:49 PM PDT 24 |
Jul 10 06:29:05 PM PDT 24 |
38290200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3032488001 |
|
|
Jul 10 06:28:49 PM PDT 24 |
Jul 10 06:29:07 PM PDT 24 |
37857300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2036710644 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:17 PM PDT 24 |
12424000 ps |
| T226 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1046080533 |
|
|
Jul 10 06:28:53 PM PDT 24 |
Jul 10 06:29:08 PM PDT 24 |
17413900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.632887575 |
|
|
Jul 10 06:28:59 PM PDT 24 |
Jul 10 06:29:14 PM PDT 24 |
12991400 ps |
| T327 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2239322169 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:36:31 PM PDT 24 |
179671600 ps |
| T323 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1987523213 |
|
|
Jul 10 06:28:58 PM PDT 24 |
Jul 10 06:36:32 PM PDT 24 |
409670100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2065521279 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:33 PM PDT 24 |
40797800 ps |
| T329 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2169563290 |
|
|
Jul 10 06:29:13 PM PDT 24 |
Jul 10 06:36:52 PM PDT 24 |
1402932000 ps |
| T330 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.231165842 |
|
|
Jul 10 06:29:20 PM PDT 24 |
Jul 10 06:41:55 PM PDT 24 |
1438970400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3056667407 |
|
|
Jul 10 06:29:16 PM PDT 24 |
Jul 10 06:29:35 PM PDT 24 |
65931400 ps |
| T326 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.431530649 |
|
|
Jul 10 06:28:58 PM PDT 24 |
Jul 10 06:43:57 PM PDT 24 |
833881500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3702084657 |
|
|
Jul 10 06:28:58 PM PDT 24 |
Jul 10 06:29:19 PM PDT 24 |
462728700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2286119475 |
|
|
Jul 10 06:28:59 PM PDT 24 |
Jul 10 06:29:42 PM PDT 24 |
4767589700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3312464835 |
|
|
Jul 10 06:28:57 PM PDT 24 |
Jul 10 06:29:12 PM PDT 24 |
13977500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.486025551 |
|
|
Jul 10 06:29:16 PM PDT 24 |
Jul 10 06:29:34 PM PDT 24 |
83787700 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2076345241 |
|
|
Jul 10 06:28:54 PM PDT 24 |
Jul 10 06:29:11 PM PDT 24 |
22507300 ps |
| T1231 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4279077674 |
|
|
Jul 10 06:29:41 PM PDT 24 |
Jul 10 06:29:57 PM PDT 24 |
16845800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2651330177 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:29:33 PM PDT 24 |
37200900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3619935536 |
|
|
Jul 10 06:28:53 PM PDT 24 |
Jul 10 06:29:24 PM PDT 24 |
153892300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.641934488 |
|
|
Jul 10 06:29:15 PM PDT 24 |
Jul 10 06:35:44 PM PDT 24 |
564574000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4063336248 |
|
|
Jul 10 06:28:50 PM PDT 24 |
Jul 10 06:29:21 PM PDT 24 |
389011700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2533260261 |
|
|
Jul 10 06:28:53 PM PDT 24 |
Jul 10 06:29:13 PM PDT 24 |
232387900 ps |
| T1237 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3926930052 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:35:31 PM PDT 24 |
586235300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1335938948 |
|
|
Jul 10 06:29:14 PM PDT 24 |
Jul 10 06:29:30 PM PDT 24 |
14807600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3783440369 |
|
|
Jul 10 06:28:53 PM PDT 24 |
Jul 10 06:29:08 PM PDT 24 |
211122600 ps |
| T1240 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1416951259 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:36:48 PM PDT 24 |
1778048000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3386072372 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:10 PM PDT 24 |
161264000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2710248449 |
|
|
Jul 10 06:29:00 PM PDT 24 |
Jul 10 06:29:14 PM PDT 24 |
44606500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.560015975 |
|
|
Jul 10 06:29:04 PM PDT 24 |
Jul 10 06:29:21 PM PDT 24 |
18480600 ps |
| T1244 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2576897634 |
|
|
Jul 10 06:29:38 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
48247600 ps |
| T1245 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.18556445 |
|
|
Jul 10 06:29:03 PM PDT 24 |
Jul 10 06:29:20 PM PDT 24 |
14573700 ps |
| T1246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4213063626 |
|
|
Jul 10 06:28:52 PM PDT 24 |
Jul 10 06:29:25 PM PDT 24 |
49777500 ps |
| T1247 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2174004496 |
|
|
Jul 10 06:28:46 PM PDT 24 |
Jul 10 06:29:01 PM PDT 24 |
15581200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2314573584 |
|
|
Jul 10 06:29:38 PM PDT 24 |
Jul 10 06:29:52 PM PDT 24 |
49830800 ps |
| T1249 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3712087816 |
|
|
Jul 10 06:29:26 PM PDT 24 |
Jul 10 06:29:43 PM PDT 24 |
94931800 ps |
| T1250 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1815689963 |
|
|
Jul 10 06:29:03 PM PDT 24 |
Jul 10 06:29:20 PM PDT 24 |
25495100 ps |