Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	95.71	93.94	98.31	91.16	98.21	96.89	98.21

Total test records in report: 1261

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.432371973			Jul 10 06:28:59 PM PDT 24	Jul 10 06:29:16 PM PDT 24	118551200 ps
T1252	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2111104092			Jul 10 06:28:42 PM PDT 24	Jul 10 06:29:04 PM PDT 24	208554900 ps
T1253	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3813386101			Jul 10 06:29:17 PM PDT 24	Jul 10 06:29:39 PM PDT 24	64729800 ps
T1254	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3075528488			Jul 10 06:29:26 PM PDT 24	Jul 10 06:29:41 PM PDT 24	14379400 ps
T1255	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2212922232			Jul 10 06:28:42 PM PDT 24	Jul 10 06:28:58 PM PDT 24	58947400 ps
T1256	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2794532100			Jul 10 06:29:09 PM PDT 24	Jul 10 06:29:28 PM PDT 24	54013900 ps
T1257	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4053965589			Jul 10 06:29:00 PM PDT 24	Jul 10 06:29:18 PM PDT 24	230097400 ps
T1258	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3657687810			Jul 10 06:29:14 PM PDT 24	Jul 10 06:29:33 PM PDT 24	22240200 ps
T1259	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.36825699			Jul 10 06:28:39 PM PDT 24	Jul 10 06:28:54 PM PDT 24	14901500 ps
T1260	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.11830346			Jul 10 06:29:08 PM PDT 24	Jul 10 06:29:24 PM PDT 24	16992100 ps
T1261	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4256589866			Jul 10 06:28:58 PM PDT 24	Jul 10 06:29:12 PM PDT 24	18584600 ps

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.2119843082
Short name	T4
Test name
Test status
Simulation time	59367069100 ps
CPU time	379.14 seconds
Started	Jul 10 07:26:56 PM PDT 24
Finished	Jul 10 07:33:16 PM PDT 24
Peak memory	275048 kb
Host	smart-2afb6051-317b-4ec9-9bfc-713e9b9d39a0
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119843082 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.2119843082
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2258677049
Short name	T66
Test name
Test status
Simulation time	1667284400 ps
CPU time	902.23 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:44:25 PM PDT 24
Peak memory	263724 kb
Host	smart-0afb87f8-50d4-4414-9395-a24adbb420e7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258677049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr l_tl_intg_err.2258677049
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.3251006890
Short name	T1
Test name
Test status
Simulation time	3783284300 ps
CPU time	599.62 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:34:48 PM PDT 24
Peak memory	315968 kb
Host	smart-c8a0fa92-770d-43b5-946f-16dc6025f228
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251006890 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_rw_derr.3251006890
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.50291064
Short name	T60
Test name
Test status
Simulation time	80146943300 ps
CPU time	871.99 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:41:31 PM PDT 24
Peak memory	261100 kb
Host	smart-e95bb9a7-7a22-4478-8e62-cedcc90138f4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50291064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.flash_ctrl_hw_rma_reset.50291064
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.2470700729
Short name	T14
Test name
Test status
Simulation time	1936249600 ps
CPU time	4930.38 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 08:46:26 PM PDT 24
Peak memory	286332 kb
Host	smart-4c3d83e5-c10e-43d6-8d1b-826b4b7ccacd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470700729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2470700729
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.1933936046
Short name	T21
Test name
Test status
Simulation time	206193448500 ps
CPU time	394.21 seconds
Started	Jul 10 07:27:07 PM PDT 24
Finished	Jul 10 07:33:42 PM PDT 24
Peak memory	292044 kb
Host	smart-b03bf9b4-3be0-4e89-8de0-1f6bd726c124
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933936046 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.1933936046
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.2446002938
Short name	T150
Test name
Test status
Simulation time	43319900 ps
CPU time	132.17 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:28:27 PM PDT 24
Peak memory	264692 kb
Host	smart-e0f64992-9abd-4aeb-b4de-8806f9b3c1c0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446002938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.2446002938
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.3732858429
Short name	T72
Test name
Test status
Simulation time	7842384900 ps
CPU time	399.81 seconds
Started	Jul 10 07:24:43 PM PDT 24
Finished	Jul 10 07:31:24 PM PDT 24
Peak memory	263668 kb
Host	smart-9422a862-ab85-4dfb-be7c-e90b0f673ea0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3732858429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3732858429
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1867145498
Short name	T103
Test name
Test status
Simulation time	274380600 ps
CPU time	17.99 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	263624 kb
Host	smart-180578b2-7eca-4246-99cc-4ed7676c06de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867145498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors. 1867145498
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.4244145809
Short name	T44
Test name
Test status
Simulation time	19130154200 ps
CPU time	163.55 seconds
Started	Jul 10 07:26:53 PM PDT 24
Finished	Jul 10 07:29:38 PM PDT 24
Peak memory	260972 kb
Host	smart-ff085652-1c7b-47fe-8110-a643d3dd1d3b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244145809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ hw_sec_otp.4244145809
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.944058092
Short name	T174
Test name
Test status
Simulation time	1478087500 ps
CPU time	70.67 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:26:02 PM PDT 24
Peak memory	260808 kb
Host	smart-7c2a8f39-bcf2-4a4d-a2a0-93c095221831
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944058092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.944058092
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.572218810
Short name	T15
Test name
Test status
Simulation time	43444900 ps
CPU time	13.95 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:24:40 PM PDT 24
Peak memory	265516 kb
Host	smart-66fd3f97-7949-4bf8-beba-fcd8c0e57b47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572218810 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.572218810
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.3720404828
Short name	T158
Test name
Test status
Simulation time	44386900 ps
CPU time	131.83 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:27:50 PM PDT 24
Peak memory	260160 kb
Host	smart-9166f74f-97a8-473b-b652-d8aa50a75069
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720404828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.3720404828
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2882258986
Short name	T13
Test name
Test status
Simulation time	10012656100 ps
CPU time	149.16 seconds
Started	Jul 10 07:26:50 PM PDT 24
Finished	Jul 10 07:29:20 PM PDT 24
Peak memory	384720 kb
Host	smart-4269c237-f1ee-4f12-964d-2f1bf8f982a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882258986 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2882258986
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1603257875
Short name	T245
Test name
Test status
Simulation time	85134900 ps
CPU time	13.52 seconds
Started	Jul 10 06:29:21 PM PDT 24
Finished	Jul 10 06:29:37 PM PDT 24
Peak memory	261244 kb
Host	smart-d88d3303-1e25-4b9f-9af1-aa510401719a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603257875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 1603257875
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.3026531906
Short name	T457
Test name
Test status
Simulation time	85261400 ps
CPU time	132.62 seconds
Started	Jul 10 07:27:30 PM PDT 24
Finished	Jul 10 07:29:44 PM PDT 24
Peak memory	260040 kb
Host	smart-3ff99eaf-afb0-401f-ae33-0bcf89d41a57
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026531906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.3026531906
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.3371099931
Short name	T2
Test name
Test status
Simulation time	13016300 ps
CPU time	21.79 seconds
Started	Jul 10 07:29:51 PM PDT 24
Finished	Jul 10 07:30:14 PM PDT 24
Peak memory	273640 kb
Host	smart-61f887cb-47b6-4867-a6a0-b391cc3fb0a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371099931 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.3371099931
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.4267439688
Short name	T157
Test name
Test status
Simulation time	159329433300 ps
CPU time	1056.73 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:42:03 PM PDT 24
Peak memory	262408 kb
Host	smart-730180bc-21b3-45ed-96de-1b99338298b3
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267439688 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.4267439688
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3279796396
Short name	T218
Test name
Test status
Simulation time	947013300 ps
CPU time	750.08 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:41:41 PM PDT 24
Peak memory	263732 kb
Host	smart-5dc559c7-6ae9-491a-ba40-8fced1897262
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279796396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.3279796396
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.2213265070
Short name	T29
Test name
Test status
Simulation time	3449279600 ps
CPU time	75.08 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:26:02 PM PDT 24
Peak memory	263180 kb
Host	smart-7fc074a4-c902-444f-9193-e9ec79e00df0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213265070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2213265070
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.534421493
Short name	T178
Test name
Test status
Simulation time	15858300 ps
CPU time	13.84 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:25:12 PM PDT 24
Peak memory	261188 kb
Host	smart-53a67072-8eb9-4e96-9bc2-798c9a3b6a24
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=534421493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.534421493
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.1931583236
Short name	T96
Test name
Test status
Simulation time	52873100 ps
CPU time	13.85 seconds
Started	Jul 10 07:28:20 PM PDT 24
Finished	Jul 10 07:28:35 PM PDT 24
Peak memory	258520 kb
Host	smart-6d90e4a7-fc70-4e20-84ad-2dcab3482cef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931583236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 1931583236
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.132336556
Short name	T53
Test name
Test status
Simulation time	904034700 ps
CPU time	24.05 seconds
Started	Jul 10 07:24:59 PM PDT 24
Finished	Jul 10 07:25:27 PM PDT 24
Peak memory	262560 kb
Host	smart-fe83abfc-10bd-4a83-b1b8-97638dbd9fcb
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132336556 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.132336556
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.3114151359
Short name	T9
Test name
Test status
Simulation time	73372000 ps
CPU time	34.87 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:24:53 PM PDT 24
Peak memory	275676 kb
Host	smart-c402c0ce-7971-44c2-82f4-cef58ff2366e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114151359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.3114151359
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.1565952075
Short name	T37
Test name
Test status
Simulation time	2417290200 ps
CPU time	142.91 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:26:43 PM PDT 24
Peak memory	295440 kb
Host	smart-2fa4d1b0-26e2-47e0-a879-a7dcc2c70ae5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565952075 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1565952075
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.1088447691
Short name	T197
Test name
Test status
Simulation time	518021200 ps
CPU time	130.79 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:31:32 PM PDT 24
Peak memory	291564 kb
Host	smart-ce2ce54f-f82c-444e-927c-266a3e000300
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088447691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.1088447691
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2687956949
Short name	T276
Test name
Test status
Simulation time	104666900 ps
CPU time	13.75 seconds
Started	Jul 10 07:25:07 PM PDT 24
Finished	Jul 10 07:25:22 PM PDT 24
Peak memory	265424 kb
Host	smart-49102366-d052-49dd-8fdb-bf3ed14527ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687956949 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2687956949
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1917476034
Short name	T252
Test name
Test status
Simulation time	61095300 ps
CPU time	20.06 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:09 PM PDT 24
Peak memory	263736 kb
Host	smart-ccd89e36-7dcf-4d87-adab-0631f056337b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917476034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1 917476034
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.1042386656
Short name	T122
Test name
Test status
Simulation time	13002933700 ps
CPU time	513.39 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:33:00 PM PDT 24
Peak memory	274220 kb
Host	smart-502d07c0-4806-4a17-98fa-5fc1face7b9d
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042386656 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.1042386656
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3508957248
Short name	T223
Test name
Test status
Simulation time	34232100 ps
CPU time	13.51 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:28:55 PM PDT 24
Peak memory	262824 kb
Host	smart-dfff42ff-eb40-41e0-a496-90c1d83daa6a
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508957248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.3508957248
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.3986370934
Short name	T381
Test name
Test status
Simulation time	494308600 ps
CPU time	35.77 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:27:33 PM PDT 24
Peak memory	275876 kb
Host	smart-7fe06495-1da1-4050-a06d-04f7396472dc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986370934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.3986370934
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.2155827213
Short name	T119
Test name
Test status
Simulation time	3748849700 ps
CPU time	656.72 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:37:03 PM PDT 24
Peak memory	309872 kb
Host	smart-bd9519ea-74aa-4e34-bf99-829ba4d76dfc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155827213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.2155827213
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2684113085
Short name	T114
Test name
Test status
Simulation time	160187190900 ps
CPU time	1022.96 seconds
Started	Jul 10 07:26:53 PM PDT 24
Finished	Jul 10 07:43:57 PM PDT 24
Peak memory	260960 kb
Host	smart-5db0d6e8-c7de-44bf-a8ea-3fd43ad549b4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684113085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.flash_ctrl_hw_rma_reset.2684113085
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1581067030
Short name	T317
Test name
Test status
Simulation time	62843500 ps
CPU time	13.54 seconds
Started	Jul 10 06:29:08 PM PDT 24
Finished	Jul 10 06:29:23 PM PDT 24
Peak memory	261236 kb
Host	smart-955a6484-c404-42e2-bb29-c94ee7bad144
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581067030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test. 1581067030
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.1216302326
Short name	T124
Test name
Test status
Simulation time	2112651500 ps
CPU time	67.1 seconds
Started	Jul 10 07:24:26 PM PDT 24
Finished	Jul 10 07:25:36 PM PDT 24
Peak memory	263240 kb
Host	smart-1384da64-03aa-4dfe-8981-6f8653c94780
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216302326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1216302326
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wr_intg.3239608077
Short name	T12
Test name
Test status
Simulation time	88237000 ps
CPU time	15.02 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:24:33 PM PDT 24
Peak memory	265464 kb
Host	smart-2e2fc409-874a-4798-9876-afb704dcc11a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239608077 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3239608077
Directory	/workspace/0.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.2271974086
Short name	T59
Test name
Test status
Simulation time	672629200 ps
CPU time	2559.42 seconds
Started	Jul 10 07:24:43 PM PDT 24
Finished	Jul 10 08:07:24 PM PDT 24
Peak memory	264784 kb
Host	smart-c66f26b2-a7a3-4c0b-a634-16a2a9d89451
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271974086 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2271974086
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.2839199228
Short name	T181
Test name
Test status
Simulation time	16475647400 ps
CPU time	610.93 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:36:01 PM PDT 24
Peak memory	314648 kb
Host	smart-2a1f380d-d339-4838-9745-09408aad1ab6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839199228 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_rw_derr.2839199228
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.2433682058
Short name	T86
Test name
Test status
Simulation time	2641696900 ps
CPU time	43.26 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 07:25:13 PM PDT 24
Peak memory	264948 kb
Host	smart-441aff75-80cb-43f6-b2a7-747791270673
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433682058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.2433682058
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2044056618
Short name	T76
Test name
Test status
Simulation time	671214400 ps
CPU time	18.23 seconds
Started	Jul 10 07:24:17 PM PDT 24
Finished	Jul 10 07:24:39 PM PDT 24
Peak memory	264320 kb
Host	smart-adf4c2b3-4911-4f7b-97b8-333694629252
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044056618 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2044056618
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1864046251
Short name	T258
Test name
Test status
Simulation time	3996816900 ps
CPU time	754.13 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:41:17 PM PDT 24
Peak memory	263744 kb
Host	smart-cd878278-b457-4915-aff2-06492ee22095
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864046251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _tl_intg_err.1864046251
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3729574757
Short name	T217
Test name
Test status
Simulation time	444260400 ps
CPU time	458.24 seconds
Started	Jul 10 06:29:11 PM PDT 24
Finished	Jul 10 06:36:51 PM PDT 24
Peak memory	263736 kb
Host	smart-d7a9da76-5e1e-4430-9112-73fcd8f57720
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729574757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.3729574757
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.834134380
Short name	T3
Test name
Test status
Simulation time	27119000 ps
CPU time	13.48 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:19 PM PDT 24
Peak memory	265080 kb
Host	smart-9b072d56-88ae-497f-9a4a-2d9dfe248efc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834134380 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.834134380
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.3325473791
Short name	T315
Test name
Test status
Simulation time	2623969800 ps
CPU time	191.99 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:31:26 PM PDT 24
Peak memory	291360 kb
Host	smart-b84c7169-c51a-4f75-9eb0-518b832ae48a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325473791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_intr_rd.3325473791
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.431530649
Short name	T326
Test name
Test status
Simulation time	833881500 ps
CPU time	897.34 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:43:57 PM PDT 24
Peak memory	263736 kb
Host	smart-9e75115c-9634-43f9-adba-1b440ad77afe
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431530649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ tl_intg_err.431530649
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.3790577587
Short name	T112
Test name
Test status
Simulation time	167295378700 ps
CPU time	2128.74 seconds
Started	Jul 10 07:24:10 PM PDT 24
Finished	Jul 10 07:59:44 PM PDT 24
Peak memory	265036 kb
Host	smart-a606b583-7c0d-47cd-a050-70e3abb6e9a7
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790577587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.3790577587
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.1167654548
Short name	T16
Test name
Test status
Simulation time	7821779400 ps
CPU time	4953.35 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 08:47:09 PM PDT 24
Peak memory	287432 kb
Host	smart-96b24980-dc18-4f37-9f8e-f6f90339caa6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167654548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1167654548
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.2205372500
Short name	T339
Test name
Test status
Simulation time	30753400 ps
CPU time	22.18 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:28:25 PM PDT 24
Peak memory	273644 kb
Host	smart-18c7c3d8-2bda-4ab8-a56e-532d880f986d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205372500 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.2205372500
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.2043058823
Short name	T362
Test name
Test status
Simulation time	572241000 ps
CPU time	72.59 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:27:32 PM PDT 24
Peak memory	264804 kb
Host	smart-0a834d97-b7ea-436f-8d5e-9a95035919ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043058823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2043058823
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.805693733
Short name	T384
Test name
Test status
Simulation time	627630300 ps
CPU time	33.3 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:28:58 PM PDT 24
Peak memory	275684 kb
Host	smart-61617710-6719-425d-b221-3c135b29dc62
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805693733 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.805693733
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.3590515818
Short name	T5
Test name
Test status
Simulation time	69827300 ps
CPU time	28.33 seconds
Started	Jul 10 07:29:02 PM PDT 24
Finished	Jul 10 07:29:31 PM PDT 24
Peak memory	275760 kb
Host	smart-9dcb01f9-3329-4404-8049-96c316e768b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590515818 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.3590515818
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.2586264132
Short name	T115
Test name
Test status
Simulation time	13332300 ps
CPU time	15.75 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:24:42 PM PDT 24
Peak memory	274944 kb
Host	smart-a667b575-650b-4a9e-9a3b-8562d7b5a254
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586264132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2586264132
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3813386101
Short name	T1253
Test name
Test status
Simulation time	64729800 ps
CPU time	19.37 seconds
Started	Jul 10 06:29:17 PM PDT 24
Finished	Jul 10 06:29:39 PM PDT 24
Peak memory	262988 kb
Host	smart-ba29bc85-3ace-4d63-ae94-2e1f1cfb4251
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813386101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 3813386101
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.951955849
Short name	T484
Test name
Test status
Simulation time	790159900 ps
CPU time	1044.18 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:41:41 PM PDT 24
Peak memory	273124 kb
Host	smart-225e9fac-dd8c-4369-bee8-456509c48164
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951955849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.951955849
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.646323877
Short name	T920
Test name
Test status
Simulation time	18886000 ps
CPU time	13.58 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:24:34 PM PDT 24
Peak memory	260940 kb
Host	smart-2438ebcb-824c-4615-94f1-ade3ee0b084b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646323877 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.646323877
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.481612739
Short name	T1006
Test name
Test status
Simulation time	10033232700 ps
CPU time	50.29 seconds
Started	Jul 10 07:24:14 PM PDT 24
Finished	Jul 10 07:25:10 PM PDT 24
Peak memory	265500 kb
Host	smart-c99da5d4-f5aa-4598-b97c-d1cca58dfcfb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481612739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.481612739
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1400478983
Short name	T473
Test name
Test status
Simulation time	57213500 ps
CPU time	13.41 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 07:24:43 PM PDT 24
Peak memory	265072 kb
Host	smart-7cbc4dec-9c99-4bf9-99a2-8ae585cc9919
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400478983 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1400478983
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.679164279
Short name	T275
Test name
Test status
Simulation time	10019052500 ps
CPU time	173.17 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:27:56 PM PDT 24
Peak memory	288232 kb
Host	smart-86bf45a7-a9fb-4493-aa64-932111fea85b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679164279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.679164279
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.3993368990
Short name	T595
Test name
Test status
Simulation time	549154900 ps
CPU time	63.66 seconds
Started	Jul 10 07:24:31 PM PDT 24
Finished	Jul 10 07:25:37 PM PDT 24
Peak memory	263212 kb
Host	smart-144c349a-be3a-426e-9524-04015a695b76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993368990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3993368990
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.3377108886
Short name	T186
Test name
Test status
Simulation time	1045776900 ps
CPU time	66.14 seconds
Started	Jul 10 07:28:11 PM PDT 24
Finished	Jul 10 07:29:19 PM PDT 24
Peak memory	264832 kb
Host	smart-b5751079-7feb-453e-a1a6-aaa35100c610
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377108886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3377108886
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.1252506537
Short name	T145
Test name
Test status
Simulation time	772454800 ps
CPU time	592.86 seconds
Started	Jul 10 07:24:16 PM PDT 24
Finished	Jul 10 07:34:14 PM PDT 24
Peak memory	283424 kb
Host	smart-41388d10-b848-46cd-90d4-7950014fabfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252506537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1252506537
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3126455662
Short name	T77
Test name
Test status
Simulation time	915036700 ps
CPU time	16.6 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:24:47 PM PDT 24
Peak memory	265504 kb
Host	smart-d79b988d-664c-4c0b-aa65-65819b04c90a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126455662 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3126455662
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1300136539
Short name	T91
Test name
Test status
Simulation time	26944103200 ps
CPU time	311.16 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:33:27 PM PDT 24
Peak memory	292776 kb
Host	smart-9a07b007-6d24-4118-a441-4d365c540205
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300136539 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1300136539
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.363499801
Short name	T23
Test name
Test status
Simulation time	46805700 ps
CPU time	13.54 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:24:31 PM PDT 24
Peak memory	265400 kb
Host	smart-d8d73332-2e6e-4268-aaf4-ac41bdb499fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363499801 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.363499801
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2511267025
Short name	T58
Test name
Test status
Simulation time	24473600 ps
CPU time	14.15 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:25:09 PM PDT 24
Peak memory	277044 kb
Host	smart-80d31856-a0d1-4097-bab2-a84ba8639272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2511267025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.2511267025
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1187582809
Short name	T390
Test name
Test status
Simulation time	33870000 ps
CPU time	28.64 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:28:16 PM PDT 24
Peak memory	275668 kb
Host	smart-a5a5bfb8-d53e-4c33-ba81-a432c1fbab99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187582809 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1187582809
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3126712413
Short name	T239
Test name
Test status
Simulation time	473322500 ps
CPU time	16.55 seconds
Started	Jul 10 06:28:37 PM PDT 24
Finished	Jul 10 06:28:55 PM PDT 24
Peak memory	263720 kb
Host	smart-53ffbb06-9560-460c-a73c-a34e6de1e92f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126712413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3 126712413
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.1792056817
Short name	T262
Test name
Test status
Simulation time	577389200 ps
CPU time	125.55 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:26:44 PM PDT 24
Peak memory	265260 kb
Host	smart-b2bd470a-9e8f-48be-8075-7acbf55d0eb7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1792056817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1792056817
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2196578242
Short name	T325
Test name
Test status
Simulation time	3261092300 ps
CPU time	757.02 seconds
Started	Jul 10 06:28:36 PM PDT 24
Finished	Jul 10 06:41:15 PM PDT 24
Peak memory	263736 kb
Host	smart-12ab8c90-5044-48ea-8343-60432904642a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196578242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl _tl_intg_err.2196578242
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3475748541
Short name	T247
Test name
Test status
Simulation time	4014650600 ps
CPU time	900.18 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:44:18 PM PDT 24
Peak memory	263744 kb
Host	smart-7f3599f2-79da-4d93-8022-faf7f2f7a0af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475748541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr l_tl_intg_err.3475748541
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.2560242520
Short name	T236
Test name
Test status
Simulation time	71940300 ps
CPU time	13.85 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:24:34 PM PDT 24
Peak memory	261628 kb
Host	smart-3b869489-7951-44e9-a911-5bb0873aa367
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560242520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.2560242520
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.1778770179
Short name	T353
Test name
Test status
Simulation time	23412200 ps
CPU time	22.25 seconds
Started	Jul 10 07:24:14 PM PDT 24
Finished	Jul 10 07:24:41 PM PDT 24
Peak memory	273792 kb
Host	smart-6e6f576b-7ba6-410c-b27d-6b7da97e229e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778770179 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.1778770179
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.3070745692
Short name	T443
Test name
Test status
Simulation time	95443200 ps
CPU time	13.88 seconds
Started	Jul 10 07:24:14 PM PDT 24
Finished	Jul 10 07:24:34 PM PDT 24
Peak memory	259188 kb
Host	smart-e12885e0-2e31-4937-9e87-1c1401b00258
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070745692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.3070745692
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.3460365238
Short name	T337
Test name
Test status
Simulation time	20651900 ps
CPU time	22.34 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:25:04 PM PDT 24
Peak memory	273640 kb
Host	smart-fc2d234d-b7ea-4edd-b454-79c01c3fbf7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460365238 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.3460365238
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.4180779168
Short name	T643
Test name
Test status
Simulation time	24970100 ps
CPU time	20.58 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:26 PM PDT 24
Peak memory	273868 kb
Host	smart-9c6e77f6-81de-4f5c-afca-876c363fee8c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180779168 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.4180779168
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.686800975
Short name	T172
Test name
Test status
Simulation time	120165089700 ps
CPU time	830.8 seconds
Started	Jul 10 07:26:00 PM PDT 24
Finished	Jul 10 07:39:52 PM PDT 24
Peak memory	265004 kb
Host	smart-82121d55-1d2b-49d6-8b8e-e9bfd12175e8
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686800975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.flash_ctrl_hw_rma_reset.686800975
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.2434835462
Short name	T102
Test name
Test status
Simulation time	51102100 ps
CPU time	22.46 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:26:38 PM PDT 24
Peak memory	273572 kb
Host	smart-77ab9ea8-e4cc-4a49-a246-747cbfe850b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434835462 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.2434835462
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.821273996
Short name	T68
Test name
Test status
Simulation time	36277600 ps
CPU time	22.34 seconds
Started	Jul 10 07:26:36 PM PDT 24
Finished	Jul 10 07:26:58 PM PDT 24
Peak memory	273728 kb
Host	smart-9ff1e2d8-f14e-49fb-9209-7a6f19de3c85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821273996 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.821273996
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.2139556891
Short name	T371
Test name
Test status
Simulation time	2406220000 ps
CPU time	61.15 seconds
Started	Jul 10 07:26:43 PM PDT 24
Finished	Jul 10 07:27:46 PM PDT 24
Peak memory	263792 kb
Host	smart-902d6926-73f3-4ea4-9cce-33e7ff4217dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139556891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2139556891
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.1236176632
Short name	T367
Test name
Test status
Simulation time	5681011000 ps
CPU time	83.2 seconds
Started	Jul 10 07:27:19 PM PDT 24
Finished	Jul 10 07:28:43 PM PDT 24
Peak memory	264872 kb
Host	smart-51301356-3db7-4d2e-a2df-486ed879754f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236176632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1236176632
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.3474982895
Short name	T927
Test name
Test status
Simulation time	62354200 ps
CPU time	21.75 seconds
Started	Jul 10 07:27:34 PM PDT 24
Finished	Jul 10 07:27:58 PM PDT 24
Peak memory	273620 kb
Host	smart-bd649912-58e8-45f6-9b5f-e57b554ef029
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474982895 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.3474982895
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.3056070473
Short name	T379
Test name
Test status
Simulation time	3032273500 ps
CPU time	97.02 seconds
Started	Jul 10 07:27:27 PM PDT 24
Finished	Jul 10 07:29:05 PM PDT 24
Peak memory	260668 kb
Host	smart-a83560ef-16c6-401b-af50-ac596d8064a9
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056070473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3 056070473
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.2437685897
Short name	T358
Test name
Test status
Simulation time	1905712900 ps
CPU time	76.4 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:28:45 PM PDT 24
Peak memory	259884 kb
Host	smart-55510ba7-656f-477d-a228-58e505d810ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437685897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2437685897
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.3571907494
Short name	T1038
Test name
Test status
Simulation time	11115200 ps
CPU time	20.83 seconds
Started	Jul 10 07:28:30 PM PDT 24
Finished	Jul 10 07:28:52 PM PDT 24
Peak memory	273572 kb
Host	smart-099320c6-d24b-4b90-85f1-692322a40c05
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571907494 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.3571907494
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.986409106
Short name	T360
Test name
Test status
Simulation time	6933412900 ps
CPU time	75.21 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	263932 kb
Host	smart-40144b09-ce95-43c7-95cc-bf5e4e30cbb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986409106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.986409106
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.445878855
Short name	T184
Test name
Test status
Simulation time	84774307500 ps
CPU time	1928.53 seconds
Started	Jul 10 07:24:30 PM PDT 24
Finished	Jul 10 07:56:41 PM PDT 24
Peak memory	260564 kb
Host	smart-1d57c52e-391b-4a7a-84b2-9558d06fb940
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445878855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_hw_rma.445878855
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.584574731
Short name	T417
Test name
Test status
Simulation time	9021534100 ps
CPU time	80.41 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 07:25:36 PM PDT 24
Peak memory	265264 kb
Host	smart-fcb7da4d-2ac6-4410-9284-fe2a8cbb203f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584574731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_intr_wr.584574731
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.2420096627
Short name	T189
Test name
Test status
Simulation time	628234600 ps
CPU time	156.64 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 07:27:00 PM PDT 24
Peak memory	281784 kb
Host	smart-fec921aa-866f-4918-a442-cbc45f7fdd1e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2420096627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2420096627
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.1059336693
Short name	T155
Test name
Test status
Simulation time	60128394900 ps
CPU time	830.72 seconds
Started	Jul 10 07:26:43 PM PDT 24
Finished	Jul 10 07:40:35 PM PDT 24
Peak memory	264440 kb
Host	smart-71288695-eca2-4052-8ba0-09cd5874ca95
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059336693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.1059336693
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1078880592
Short name	T74
Test name
Test status
Simulation time	885758200 ps
CPU time	17.64 seconds
Started	Jul 10 07:24:41 PM PDT 24
Finished	Jul 10 07:25:00 PM PDT 24
Peak memory	263456 kb
Host	smart-21b0e887-feaf-4618-8ec2-a065b783f256
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078880592 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1078880592
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1808264705
Short name	T1130
Test name
Test status
Simulation time	447502500 ps
CPU time	37.94 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:29:20 PM PDT 24
Peak memory	261276 kb
Host	smart-b8f3c75c-07c0-4e45-8730-b2f11c75c530
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808264705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.1808264705
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4219202074
Short name	T250
Test name
Test status
Simulation time	458542100 ps
CPU time	16.63 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:34 PM PDT 24
Peak memory	263716 kb
Host	smart-9c3522cf-ca48-40b8-a18b-faa18ec54265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219202074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 4219202074
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.233005483
Short name	T206
Test name
Test status
Simulation time	28104200 ps
CPU time	15.56 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:04 PM PDT 24
Peak memory	263720 kb
Host	smart-96be0ec9-d950-4468-90a4-99672ae88b60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233005483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.233005483
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.1069816600
Short name	T999
Test name
Test status
Simulation time	2021466900 ps
CPU time	2182.57 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 08:00:41 PM PDT 24
Peak memory	264584 kb
Host	smart-eeef4ab5-3395-433f-9d84-016fd22c4760
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1069816600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.1069816600
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.2574672020
Short name	T840
Test name
Test status
Simulation time	74349225200 ps
CPU time	3679.54 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 08:25:43 PM PDT 24
Peak memory	265100 kb
Host	smart-42aa9355-60f2-420f-b571-f534152ae109
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574672020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.2574672020
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.3939532559
Short name	T584
Test name
Test status
Simulation time	453252900 ps
CPU time	120.96 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:26:19 PM PDT 24
Peak memory	295328 kb
Host	smart-61d5689f-8413-4b5e-a706-2ad9f5b2b94f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939532559 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3939532559
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3827891570
Short name	T195
Test name
Test status
Simulation time	1180331751800 ps
CPU time	1866.69 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 07:55:36 PM PDT 24
Peak memory	264128 kb
Host	smart-987ba651-40c8-4bcd-bc1e-be2f87e72c97
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827891570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.3827891570
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.2650634827
Short name	T182
Test name
Test status
Simulation time	7182109100 ps
CPU time	122.79 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:26:49 PM PDT 24
Peak memory	281860 kb
Host	smart-3c47c594-154b-43b9-9b81-36c2b3123f6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2650634827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2650634827
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.3548653756
Short name	T10
Test name
Test status
Simulation time	42820500 ps
CPU time	15.02 seconds
Started	Jul 10 07:24:41 PM PDT 24
Finished	Jul 10 07:24:57 PM PDT 24
Peak memory	260964 kb
Host	smart-1511b28d-2812-4004-9816-b2bdd5a25ee0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548653756 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3548653756
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.1283482969
Short name	T192
Test name
Test status
Simulation time	3987382800 ps
CPU time	146.62 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:27:50 PM PDT 24
Peak memory	281812 kb
Host	smart-99c032ae-8490-4ef0-bdd0-80bd280a8663
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1283482969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1283482969
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.1893029932
Short name	T190
Test name
Test status
Simulation time	2406302100 ps
CPU time	142.08 seconds
Started	Jul 10 07:25:35 PM PDT 24
Finished	Jul 10 07:27:59 PM PDT 24
Peak memory	281800 kb
Host	smart-7c753505-ef2c-44a6-a6f4-61f2c53b2434
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1893029932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1893029932
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1376762989
Short name	T1166
Test name
Test status
Simulation time	3473620400 ps
CPU time	29.44 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:29:11 PM PDT 24
Peak memory	261344 kb
Host	smart-38cbed77-aa81-4961-a877-d827acfbcfef
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376762989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.1376762989
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3629427687
Short name	T1176
Test name
Test status
Simulation time	4392419300 ps
CPU time	49.57 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:29:32 PM PDT 24
Peak memory	261216 kb
Host	smart-0e458e78-f76e-4ccb-aafb-d44112fb7363
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629427687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.3629427687
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3892402180
Short name	T1172
Test name
Test status
Simulation time	49486200 ps
CPU time	30.68 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:29:13 PM PDT 24
Peak memory	261304 kb
Host	smart-82e5e56c-3459-4812-bb66-7ac19db611e1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892402180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.3892402180
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3426986552
Short name	T1190
Test name
Test status
Simulation time	47643200 ps
CPU time	17.01 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:28:59 PM PDT 24
Peak memory	271996 kb
Host	smart-1c73ba10-ebf2-4847-9898-cd7ef2f1be0d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426986552 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3426986552
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1503365388
Short name	T1141
Test name
Test status
Simulation time	114723700 ps
CPU time	17.36 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:28:58 PM PDT 24
Peak memory	263944 kb
Host	smart-937177d0-0fbe-4ec7-87b9-bc59a2cc364d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503365388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1503365388
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2174004496
Short name	T1247
Test name
Test status
Simulation time	15581200 ps
CPU time	13.4 seconds
Started	Jul 10 06:28:46 PM PDT 24
Finished	Jul 10 06:29:01 PM PDT 24
Peak memory	261176 kb
Host	smart-53aee878-2b27-4103-bc4e-c8370f80a3a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174004496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2 174004496
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2396385813
Short name	T1128
Test name
Test status
Simulation time	20256000 ps
CPU time	13.95 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:28:55 PM PDT 24
Peak memory	261168 kb
Host	smart-9e91df90-f85b-4980-a7f4-5aa08b93c1c0
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396385813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.2396385813
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2111104092
Short name	T1252
Test name
Test status
Simulation time	208554900 ps
CPU time	18.76 seconds
Started	Jul 10 06:28:42 PM PDT 24
Finished	Jul 10 06:29:04 PM PDT 24
Peak memory	262788 kb
Host	smart-fe3b68b2-a8e9-4959-a5b7-7c79337b1ee1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111104092 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.2111104092
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.250220725
Short name	T1201
Test name
Test status
Simulation time	114063200 ps
CPU time	15.64 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:28:59 PM PDT 24
Peak memory	253012 kb
Host	smart-ab6c1a06-9827-4ccf-a523-d22400fb4f7b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250220725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.250220725
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.663419753
Short name	T1171
Test name
Test status
Simulation time	13304000 ps
CPU time	13.04 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:28:55 PM PDT 24
Peak memory	252960 kb
Host	smart-7bfe317e-8513-47db-abe3-d0b8d99cedea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663419753 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.663419753
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1300893130
Short name	T1197
Test name
Test status
Simulation time	671383100 ps
CPU time	34.14 seconds
Started	Jul 10 06:28:46 PM PDT 24
Finished	Jul 10 06:29:22 PM PDT 24
Peak memory	261344 kb
Host	smart-eb54770e-8bfe-4b9e-aaeb-afac340c3c47
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300893130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.1300893130
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2046054075
Short name	T1124
Test name
Test status
Simulation time	2182124200 ps
CPU time	46.3 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:29:27 PM PDT 24
Peak memory	260944 kb
Host	smart-0092b29d-5466-4e68-b4e8-ca81b66deed7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046054075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.2046054075
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.812437406
Short name	T1174
Test name
Test status
Simulation time	226549700 ps
CPU time	16.41 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:05 PM PDT 24
Peak memory	271996 kb
Host	smart-00683e79-b830-415b-bb7f-5bbf8b661106
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812437406 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.812437406
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3504973353
Short name	T286
Test name
Test status
Simulation time	78101400 ps
CPU time	17.67 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:29:01 PM PDT 24
Peak memory	261220 kb
Host	smart-09103734-deee-4cb2-b651-fadeae8ed780
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504973353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.3504973353
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2212922232
Short name	T1255
Test name
Test status
Simulation time	58947400 ps
CPU time	14.13 seconds
Started	Jul 10 06:28:42 PM PDT 24
Finished	Jul 10 06:28:58 PM PDT 24
Peak memory	260996 kb
Host	smart-6bdf7e48-77b7-4c47-9d65-aa81550ca70a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212922232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2 212922232
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.444659139
Short name	T222
Test name
Test status
Simulation time	55950700 ps
CPU time	13.42 seconds
Started	Jul 10 06:28:40 PM PDT 24
Finished	Jul 10 06:28:56 PM PDT 24
Peak memory	262772 kb
Host	smart-bc0079d3-9d55-4df5-bd52-c55bb734382b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444659139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_mem_partial_access.444659139
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1938020664
Short name	T1143
Test name
Test status
Simulation time	17354200 ps
CPU time	13.64 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:28:57 PM PDT 24
Peak memory	261028 kb
Host	smart-5105482b-7a6b-4a8e-b8f1-58dd8362834e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938020664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.1938020664
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2344181406
Short name	T237
Test name
Test status
Simulation time	62494900 ps
CPU time	33.33 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:22 PM PDT 24
Peak memory	261268 kb
Host	smart-9d18f58d-8a02-48bf-a1a0-ebb354928130
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344181406 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2344181406
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.4070655356
Short name	T1165
Test name
Test status
Simulation time	13749400 ps
CPU time	15.97 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:28:57 PM PDT 24
Peak memory	253152 kb
Host	smart-0aab7da5-c6de-4b4f-8c37-a65bbd643809
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070655356 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.4070655356
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.36825699
Short name	T1259
Test name
Test status
Simulation time	14901500 ps
CPU time	13.41 seconds
Started	Jul 10 06:28:39 PM PDT 24
Finished	Jul 10 06:28:54 PM PDT 24
Peak memory	252952 kb
Host	smart-215f85b0-bc09-48d5-a87a-55291b93b451
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825699 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.36825699
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2944653636
Short name	T257
Test name
Test status
Simulation time	41339500 ps
CPU time	17.67 seconds
Started	Jul 10 06:28:41 PM PDT 24
Finished	Jul 10 06:29:01 PM PDT 24
Peak memory	263732 kb
Host	smart-1fbf6ce1-7f4e-42cb-8dfc-d70956eafc10
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944653636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2 944653636
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2332371923
Short name	T290
Test name
Test status
Simulation time	103205100 ps
CPU time	19.41 seconds
Started	Jul 10 06:29:08 PM PDT 24
Finished	Jul 10 06:29:28 PM PDT 24
Peak memory	272000 kb
Host	smart-2185234c-e751-493f-8c44-a9d9054efe29
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332371923 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.2332371923
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3121729191
Short name	T1210
Test name
Test status
Simulation time	57784800 ps
CPU time	14.57 seconds
Started	Jul 10 06:29:11 PM PDT 24
Finished	Jul 10 06:29:27 PM PDT 24
Peak memory	263740 kb
Host	smart-aa7ff67d-69a2-442e-abe0-07065fe21238
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121729191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.3121729191
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4165685462
Short name	T1126
Test name
Test status
Simulation time	15025700 ps
CPU time	13.22 seconds
Started	Jul 10 06:29:07 PM PDT 24
Finished	Jul 10 06:29:21 PM PDT 24
Peak memory	261176 kb
Host	smart-ade1a365-6127-4818-b612-f5bf3762f142
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165685462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 4165685462
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3990713057
Short name	T1218
Test name
Test status
Simulation time	345240000 ps
CPU time	18.21 seconds
Started	Jul 10 06:29:08 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	263772 kb
Host	smart-c1dba24e-9383-4d27-942a-1f59428b48b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990713057 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3990713057
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.486025551
Short name	T1229
Test name
Test status
Simulation time	83787700 ps
CPU time	15.87 seconds
Started	Jul 10 06:29:16 PM PDT 24
Finished	Jul 10 06:29:34 PM PDT 24
Peak memory	252788 kb
Host	smart-c6f01077-a829-4fdc-ac41-bb64aa06771b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486025551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.486025551
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2587167278
Short name	T1158
Test name
Test status
Simulation time	12754400 ps
CPU time	15.77 seconds
Started	Jul 10 06:29:12 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	252948 kb
Host	smart-9b6e39dd-7dc1-4f30-9b86-b1b7d073bb51
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587167278 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2587167278
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3703961746
Short name	T106
Test name
Test status
Simulation time	83319900 ps
CPU time	18.7 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:30 PM PDT 24
Peak memory	278696 kb
Host	smart-24bcf691-0c0c-4081-add4-ee62dd190a7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703961746 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3703961746
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2794532100
Short name	T1256
Test name
Test status
Simulation time	54013900 ps
CPU time	17 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:28 PM PDT 24
Peak memory	263712 kb
Host	smart-bf2ddc17-e119-4216-a139-f9b4e5f826bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794532100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.2794532100
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1395228045
Short name	T1164
Test name
Test status
Simulation time	183625400 ps
CPU time	36.38 seconds
Started	Jul 10 06:29:06 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	263660 kb
Host	smart-2bcfecd1-5f44-4d89-a3cc-6ec200d8b9a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395228045 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1395228045
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.11830346
Short name	T1260
Test name
Test status
Simulation time	16992100 ps
CPU time	15.68 seconds
Started	Jul 10 06:29:08 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	252924 kb
Host	smart-e2657a6a-1dd3-471d-b04f-75858dfff50a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11830346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.11830346
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2782247074
Short name	T1120
Test name
Test status
Simulation time	63955700 ps
CPU time	15.87 seconds
Started	Jul 10 06:29:08 PM PDT 24
Finished	Jul 10 06:29:25 PM PDT 24
Peak memory	252936 kb
Host	smart-14f890e2-234e-42ce-be25-8f07979fd0b4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782247074 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2782247074
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3689709646
Short name	T1205
Test name
Test status
Simulation time	224134100 ps
CPU time	15.77 seconds
Started	Jul 10 06:29:10 PM PDT 24
Finished	Jul 10 06:29:28 PM PDT 24
Peak memory	262816 kb
Host	smart-ab768031-3008-4626-ab20-2c5eaf86538b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689709646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors. 3689709646
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1165928001
Short name	T287
Test name
Test status
Simulation time	366083000 ps
CPU time	17.47 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	271236 kb
Host	smart-57725e15-8ecd-4d6d-aa38-4fbc31beee6e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165928001 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1165928001
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1556276341
Short name	T1142
Test name
Test status
Simulation time	21888800 ps
CPU time	14.65 seconds
Started	Jul 10 06:29:07 PM PDT 24
Finished	Jul 10 06:29:23 PM PDT 24
Peak memory	263716 kb
Host	smart-e8ab9b60-e0c6-4615-9dbd-213e3fee2bf0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556276341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.1556276341
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3537492649
Short name	T1149
Test name
Test status
Simulation time	15281500 ps
CPU time	14.01 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:25 PM PDT 24
Peak memory	261108 kb
Host	smart-e5265fab-56c4-4c97-8099-2bd4eca24c0c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537492649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 3537492649
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.886844399
Short name	T285
Test name
Test status
Simulation time	247399200 ps
CPU time	17.85 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	263720 kb
Host	smart-e7255dbc-5666-4ca0-8d69-9d7abb124df7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886844399 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.886844399
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1523311833
Short name	T1133
Test name
Test status
Simulation time	21539700 ps
CPU time	15.78 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:31 PM PDT 24
Peak memory	252952 kb
Host	smart-9afc3ab1-bbba-4e90-ae78-99979ef3894d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523311833 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1523311833
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4164425394
Short name	T1206
Test name
Test status
Simulation time	12734400 ps
CPU time	15.61 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:28 PM PDT 24
Peak memory	252948 kb
Host	smart-f622bec7-1572-4a46-acd6-13c8f311d49b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164425394 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.4164425394
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2561807317
Short name	T249
Test name
Test status
Simulation time	102166200 ps
CPU time	18.3 seconds
Started	Jul 10 06:29:10 PM PDT 24
Finished	Jul 10 06:29:31 PM PDT 24
Peak memory	263720 kb
Host	smart-de41a986-d9b4-44af-9b7c-17e1b7b6255f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561807317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 2561807317
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1501394721
Short name	T255
Test name
Test status
Simulation time	786822700 ps
CPU time	894.04 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:44:09 PM PDT 24
Peak memory	263744 kb
Host	smart-869064e3-f0ae-475d-9d73-b37042fe0b24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501394721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.1501394721
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1105180519
Short name	T1193
Test name
Test status
Simulation time	54103700 ps
CPU time	15.31 seconds
Started	Jul 10 06:29:18 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	272000 kb
Host	smart-8396d8f0-ff45-46f2-9a43-6bd56e2b3090
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105180519 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1105180519
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1007272646
Short name	T238
Test name
Test status
Simulation time	29632900 ps
CPU time	16.76 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:32 PM PDT 24
Peak memory	261320 kb
Host	smart-73c2aff7-89fc-4092-9cba-121dbfed1dde
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007272646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.1007272646
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.4107389207
Short name	T318
Test name
Test status
Simulation time	16277200 ps
CPU time	14.13 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:26 PM PDT 24
Peak memory	261104 kb
Host	smart-d8064de9-c53e-4714-9d2b-973f3233081a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107389207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 4107389207
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.4095276008
Short name	T1127
Test name
Test status
Simulation time	46993900 ps
CPU time	17.71 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	263676 kb
Host	smart-da1f3eb2-82b9-43cf-895a-d348c8d7cfed
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095276008 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.4095276008
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3056667407
Short name	T1225
Test name
Test status
Simulation time	65931400 ps
CPU time	15.64 seconds
Started	Jul 10 06:29:16 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	252980 kb
Host	smart-1c82e672-4581-46c4-9c5c-7a6befd33209
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056667407 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3056667407
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.402799244
Short name	T1116
Test name
Test status
Simulation time	37928100 ps
CPU time	12.98 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	253080 kb
Host	smart-3f9e70c0-bd08-4b81-bbf3-fdc2356e9486
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402799244 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.402799244
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3644365200
Short name	T248
Test name
Test status
Simulation time	125016000 ps
CPU time	16.69 seconds
Started	Jul 10 06:29:10 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	263716 kb
Host	smart-3737cfcf-2b65-47ce-ac1d-0a8259dccf41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644365200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors. 3644365200
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.693056449
Short name	T331
Test name
Test status
Simulation time	1092952100 ps
CPU time	455.85 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:36:51 PM PDT 24
Peak memory	263744 kb
Host	smart-e50de081-d1e2-4643-ab50-cb299b25f7df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693056449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl _tl_intg_err.693056449
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1706022867
Short name	T105
Test name
Test status
Simulation time	75032500 ps
CPU time	18.59 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:29:32 PM PDT 24
Peak memory	271952 kb
Host	smart-6d5bb6f0-4cef-41cb-8c3e-68d740b7e559
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706022867 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1706022867
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2651330177
Short name	T1232
Test name
Test status
Simulation time	37200900 ps
CPU time	14.62 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:33 PM PDT 24
Peak memory	261200 kb
Host	smart-97b946a0-14ef-4cdf-92b0-8b352132cf56
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651330177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.flash_ctrl_csr_rw.2651330177
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2880756266
Short name	T1202
Test name
Test status
Simulation time	56874400 ps
CPU time	13.5 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:29:28 PM PDT 24
Peak memory	261120 kb
Host	smart-11a027ed-2559-47a9-a45f-0b8860e669fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880756266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 2880756266
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4039979977
Short name	T1186
Test name
Test status
Simulation time	346483700 ps
CPU time	15.76 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:34 PM PDT 24
Peak memory	262320 kb
Host	smart-c12f8da5-97ad-4912-85fe-bacd208f6d0e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039979977 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.4039979977
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2065521279
Short name	T1224
Test name
Test status
Simulation time	40797800 ps
CPU time	15.6 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:33 PM PDT 24
Peak memory	252948 kb
Host	smart-59fd0585-61af-445e-9730-b2f538a43ceb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065521279 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2065521279
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1061620737
Short name	T1200
Test name
Test status
Simulation time	157454600 ps
CPU time	15.88 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:29:30 PM PDT 24
Peak memory	252940 kb
Host	smart-af7071e6-8bf4-419b-85c5-cdd51e30c963
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061620737 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.1061620737
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2169563290
Short name	T329
Test name
Test status
Simulation time	1402932000 ps
CPU time	457.73 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:36:52 PM PDT 24
Peak memory	263912 kb
Host	smart-8bed2fcb-53f6-44a0-a898-0924973622ea
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169563290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr l_tl_intg_err.2169563290
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.496297451
Short name	T253
Test name
Test status
Simulation time	48934100 ps
CPU time	19.87 seconds
Started	Jul 10 06:29:19 PM PDT 24
Finished	Jul 10 06:29:41 PM PDT 24
Peak memory	270552 kb
Host	smart-e59c010e-5e4c-4a84-abf6-d54229c8a830
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496297451 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.496297451
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2587704818
Short name	T284
Test name
Test status
Simulation time	138439700 ps
CPU time	16.43 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:33 PM PDT 24
Peak memory	261260 kb
Host	smart-194a948d-4295-4eb1-89c0-047bc94612d6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587704818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.flash_ctrl_csr_rw.2587704818
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2950464080
Short name	T1182
Test name
Test status
Simulation time	19097500 ps
CPU time	13.36 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	261268 kb
Host	smart-a1db7b65-b2c1-4295-89f1-ffc1d956f6de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950464080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 2950464080
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1763344455
Short name	T293
Test name
Test status
Simulation time	3101298700 ps
CPU time	18.78 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	261424 kb
Host	smart-21704af3-f5d8-4d16-9782-f6ea1c150fdf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763344455 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1763344455
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1901071856
Short name	T1136
Test name
Test status
Simulation time	23615000 ps
CPU time	15.7 seconds
Started	Jul 10 06:29:13 PM PDT 24
Finished	Jul 10 06:29:29 PM PDT 24
Peak memory	253000 kb
Host	smart-48b07960-049c-43db-a670-d6d468f63a82
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901071856 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.1901071856
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3690230938
Short name	T1118
Test name
Test status
Simulation time	14620800 ps
CPU time	16.89 seconds
Started	Jul 10 06:29:19 PM PDT 24
Finished	Jul 10 06:29:38 PM PDT 24
Peak memory	253012 kb
Host	smart-49b22fb7-d4af-444b-9717-9a5518bc1db7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690230938 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.3690230938
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.853683401
Short name	T1191
Test name
Test status
Simulation time	325222600 ps
CPU time	16.8 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:42 PM PDT 24
Peak memory	271972 kb
Host	smart-7b365e79-0d46-4dcd-840d-e043a5b7f44d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853683401 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.853683401
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3657687810
Short name	T1258
Test name
Test status
Simulation time	22240200 ps
CPU time	16.29 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:33 PM PDT 24
Peak memory	261232 kb
Host	smart-0ad653ca-9897-4c4f-a02b-6029e774aaa3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657687810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.3657687810
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1335938948
Short name	T1238
Test name
Test status
Simulation time	14807600 ps
CPU time	13.99 seconds
Started	Jul 10 06:29:14 PM PDT 24
Finished	Jul 10 06:29:30 PM PDT 24
Peak memory	261236 kb
Host	smart-129ba260-4ba2-4224-976b-63c73356b6a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335938948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 1335938948
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.982371064
Short name	T1147
Test name
Test status
Simulation time	229307500 ps
CPU time	20.51 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:29:42 PM PDT 24
Peak memory	263752 kb
Host	smart-1c1ab542-3f03-4847-9bd9-98a9828f5321
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982371064 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.982371064
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3540315348
Short name	T1122
Test name
Test status
Simulation time	20291900 ps
CPU time	15.85 seconds
Started	Jul 10 06:29:16 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	252836 kb
Host	smart-f9329bbe-a7cd-44ee-b17f-537aa531390a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540315348 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3540315348
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.215707381
Short name	T1117
Test name
Test status
Simulation time	57809900 ps
CPU time	13.22 seconds
Started	Jul 10 06:29:16 PM PDT 24
Finished	Jul 10 06:29:32 PM PDT 24
Peak memory	253020 kb
Host	smart-b1ce6c3a-99e4-4196-9a4e-9764a7a82999
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215707381 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.215707381
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.813668250
Short name	T241
Test name
Test status
Simulation time	437550400 ps
CPU time	16.65 seconds
Started	Jul 10 06:29:16 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	263724 kb
Host	smart-1ba6252d-c29d-4f16-90e8-b15e093108e2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813668250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.813668250
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.641934488
Short name	T1234
Test name
Test status
Simulation time	564574000 ps
CPU time	385.84 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:35:44 PM PDT 24
Peak memory	263752 kb
Host	smart-a4dab759-3807-4020-a8c0-dc951256fe2b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641934488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl _tl_intg_err.641934488
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1390259266
Short name	T254
Test name
Test status
Simulation time	323315200 ps
CPU time	18.91 seconds
Started	Jul 10 06:29:21 PM PDT 24
Finished	Jul 10 06:29:42 PM PDT 24
Peak memory	271992 kb
Host	smart-dfa7c5d0-804d-4be2-bdb6-c1a8d151ecd4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390259266 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1390259266
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3454106996
Short name	T1125
Test name
Test status
Simulation time	120977200 ps
CPU time	17.06 seconds
Started	Jul 10 06:29:21 PM PDT 24
Finished	Jul 10 06:29:40 PM PDT 24
Peak memory	261300 kb
Host	smart-438ef491-6e1b-43b4-be48-e423e87b33b4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454106996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.3454106996
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.178595631
Short name	T1151
Test name
Test status
Simulation time	118598700 ps
CPU time	13.42 seconds
Started	Jul 10 06:29:21 PM PDT 24
Finished	Jul 10 06:29:37 PM PDT 24
Peak memory	261192 kb
Host	smart-5b31a9f3-cda5-457b-9950-49f7d44ba38b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178595631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.178595631
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3713553784
Short name	T1123
Test name
Test status
Simulation time	1562676900 ps
CPU time	16.88 seconds
Started	Jul 10 06:29:21 PM PDT 24
Finished	Jul 10 06:29:40 PM PDT 24
Peak memory	263704 kb
Host	smart-db3abd68-ffb3-4bda-b631-caa0ac0eb557
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713553784 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3713553784
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.521659425
Short name	T1163
Test name
Test status
Simulation time	21098700 ps
CPU time	15.71 seconds
Started	Jul 10 06:29:19 PM PDT 24
Finished	Jul 10 06:29:37 PM PDT 24
Peak memory	253004 kb
Host	smart-8cbba7da-9f5e-40b1-a751-e9b82082340d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521659425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.521659425
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.76191748
Short name	T1138
Test name
Test status
Simulation time	45125000 ps
CPU time	13.68 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:29:35 PM PDT 24
Peak memory	253016 kb
Host	smart-764c9a11-c189-45df-b10f-4dd60b3cbab6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76191748 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.76191748
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2085664075
Short name	T1181
Test name
Test status
Simulation time	108039000 ps
CPU time	18.83 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:44 PM PDT 24
Peak memory	263736 kb
Host	smart-08ac7890-e931-4049-8891-2d6fad960ba7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085664075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 2085664075
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.231165842
Short name	T330
Test name
Test status
Simulation time	1438970400 ps
CPU time	752.69 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:41:55 PM PDT 24
Peak memory	271936 kb
Host	smart-ee07cd06-7ceb-47ec-b77b-57f1dacd0586
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231165842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl _tl_intg_err.231165842
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2195882918
Short name	T322
Test name
Test status
Simulation time	79185900 ps
CPU time	18.99 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	280152 kb
Host	smart-84ae9b5f-efe0-4f30-ac65-dd7c690e3e67
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195882918 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2195882918
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2483589243
Short name	T1219
Test name
Test status
Simulation time	61600700 ps
CPU time	18 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	263724 kb
Host	smart-c58ad85a-cb26-4e0e-bb94-d31a736db0c8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483589243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.2483589243
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3186399454
Short name	T292
Test name
Test status
Simulation time	368549300 ps
CPU time	15.41 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:29:38 PM PDT 24
Peak memory	262424 kb
Host	smart-3362889e-690a-40e4-b08e-9d638845e34d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186399454 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3186399454
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1791110579
Short name	T1195
Test name
Test status
Simulation time	41611700 ps
CPU time	15.42 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:40 PM PDT 24
Peak memory	253076 kb
Host	smart-40c8934e-4f96-4ce2-9f85-4ecf7e0c578f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791110579 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1791110579
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2385029655
Short name	T1208
Test name
Test status
Simulation time	44155300 ps
CPU time	16.06 seconds
Started	Jul 10 06:29:20 PM PDT 24
Finished	Jul 10 06:29:38 PM PDT 24
Peak memory	253084 kb
Host	smart-02bc2ba6-3200-40e9-a186-6555c9a5f26a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385029655 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.2385029655
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1238588311
Short name	T104
Test name
Test status
Simulation time	509451700 ps
CPU time	19 seconds
Started	Jul 10 06:29:22 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	263712 kb
Host	smart-aec80c60-e76b-49e9-9241-604870e12eb7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238588311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 1238588311
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2987369011
Short name	T1212
Test name
Test status
Simulation time	46077200 ps
CPU time	14.66 seconds
Started	Jul 10 06:29:27 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	263796 kb
Host	smart-b8b649c0-1151-4606-958d-0711c9d22ee9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987369011 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2987369011
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3315261204
Short name	T1187
Test name
Test status
Simulation time	420734700 ps
CPU time	14.63 seconds
Started	Jul 10 06:29:27 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	261656 kb
Host	smart-50b659fc-a77c-488e-bd9a-21a0b136c0d5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315261204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.3315261204
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3075528488
Short name	T1254
Test name
Test status
Simulation time	14379400 ps
CPU time	14.28 seconds
Started	Jul 10 06:29:26 PM PDT 24
Finished	Jul 10 06:29:41 PM PDT 24
Peak memory	261120 kb
Host	smart-07fc7fae-8efc-4527-8513-b72e2ce1b445
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075528488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 3075528488
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2915359943
Short name	T1145
Test name
Test status
Simulation time	64801900 ps
CPU time	17.95 seconds
Started	Jul 10 06:29:27 PM PDT 24
Finished	Jul 10 06:29:46 PM PDT 24
Peak memory	262612 kb
Host	smart-e4824aab-0c73-440c-b927-8141842a0c3f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915359943 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2915359943
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3712087816
Short name	T1249
Test name
Test status
Simulation time	94931800 ps
CPU time	15.95 seconds
Started	Jul 10 06:29:26 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	253080 kb
Host	smart-d07bbdd2-5787-42f4-8252-6b471b29080e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712087816 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3712087816
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2831330687
Short name	T1154
Test name
Test status
Simulation time	25937300 ps
CPU time	13.41 seconds
Started	Jul 10 06:29:27 PM PDT 24
Finished	Jul 10 06:29:43 PM PDT 24
Peak memory	252828 kb
Host	smart-4902c051-6c1d-4ccd-b704-4a68160f2a96
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831330687 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2831330687
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1382312999
Short name	T251
Test name
Test status
Simulation time	299537300 ps
CPU time	18.19 seconds
Started	Jul 10 06:29:24 PM PDT 24
Finished	Jul 10 06:29:44 PM PDT 24
Peak memory	263720 kb
Host	smart-1623d397-6000-4701-9745-eb8a47758db9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382312999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 1382312999
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3041481515
Short name	T256
Test name
Test status
Simulation time	2838397700 ps
CPU time	754.66 seconds
Started	Jul 10 06:29:24 PM PDT 24
Finished	Jul 10 06:42:00 PM PDT 24
Peak memory	263784 kb
Host	smart-e2c26238-ee63-4167-8da4-1bd9629f4622
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041481515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.3041481515
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.944478236
Short name	T65
Test name
Test status
Simulation time	8915180200 ps
CPU time	35.87 seconds
Started	Jul 10 06:28:50 PM PDT 24
Finished	Jul 10 06:29:26 PM PDT 24
Peak memory	261348 kb
Host	smart-7c424773-16b5-433f-93f5-0a5fd1a95e33
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944478236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.flash_ctrl_csr_aliasing.944478236
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2725507449
Short name	T64
Test name
Test status
Simulation time	2084237700 ps
CPU time	49.84 seconds
Started	Jul 10 06:28:48 PM PDT 24
Finished	Jul 10 06:29:39 PM PDT 24
Peak memory	261216 kb
Host	smart-96eacb1e-e210-4d75-a2fa-dabc7d18ecdf
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725507449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.2725507449
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2694187955
Short name	T1175
Test name
Test status
Simulation time	107907400 ps
CPU time	25.81 seconds
Started	Jul 10 06:28:48 PM PDT 24
Finished	Jul 10 06:29:15 PM PDT 24
Peak memory	261340 kb
Host	smart-a521cec5-826c-462d-b4bf-d1982b7467f8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694187955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.2694187955
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.321416567
Short name	T1134
Test name
Test status
Simulation time	167312700 ps
CPU time	16.14 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:04 PM PDT 24
Peak memory	271984 kb
Host	smart-5d1f3af7-e8aa-4905-83e2-075f2ceceb98
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321416567 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.321416567
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3032488001
Short name	T1221
Test name
Test status
Simulation time	37857300 ps
CPU time	16.47 seconds
Started	Jul 10 06:28:49 PM PDT 24
Finished	Jul 10 06:29:07 PM PDT 24
Peak memory	263736 kb
Host	smart-76b7d1f2-c1ae-4e33-b1ec-b035bda334a9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032488001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.3032488001
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.168062815
Short name	T1140
Test name
Test status
Simulation time	83108400 ps
CPU time	13.36 seconds
Started	Jul 10 06:28:46 PM PDT 24
Finished	Jul 10 06:29:01 PM PDT 24
Peak memory	261172 kb
Host	smart-d2f0c887-4fab-4262-ba34-72815c8511b4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168062815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.168062815
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4188245569
Short name	T225
Test name
Test status
Simulation time	29300800 ps
CPU time	13.6 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:02 PM PDT 24
Peak memory	261920 kb
Host	smart-277bff35-2830-44a5-b2b4-4d47eb844c04
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188245569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_mem_partial_access.4188245569
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.276948092
Short name	T1160
Test name
Test status
Simulation time	16780200 ps
CPU time	13.9 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:02 PM PDT 24
Peak memory	261064 kb
Host	smart-9868601a-8411-4f4c-8350-4f836a5b8fd4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276948092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem _walk.276948092
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3630150299
Short name	T1220
Test name
Test status
Simulation time	38290200 ps
CPU time	15.23 seconds
Started	Jul 10 06:28:49 PM PDT 24
Finished	Jul 10 06:29:05 PM PDT 24
Peak memory	261260 kb
Host	smart-2112bb6c-c5f8-4057-b12f-aac625ed2f1c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630150299 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3630150299
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1142857880
Short name	T1115
Test name
Test status
Simulation time	13434800 ps
CPU time	13.18 seconds
Started	Jul 10 06:28:47 PM PDT 24
Finished	Jul 10 06:29:01 PM PDT 24
Peak memory	252956 kb
Host	smart-3c6ae4b4-2e0f-4830-8617-7cba83005f85
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142857880 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1142857880
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1845865830
Short name	T1204
Test name
Test status
Simulation time	13613700 ps
CPU time	13.54 seconds
Started	Jul 10 06:28:48 PM PDT 24
Finished	Jul 10 06:29:03 PM PDT 24
Peak memory	252948 kb
Host	smart-ed68ba82-5d74-4452-a3f4-e73e10a24a31
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845865830 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.1845865830
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2278204872
Short name	T324
Test name
Test status
Simulation time	1245022200 ps
CPU time	906.14 seconds
Started	Jul 10 06:28:46 PM PDT 24
Finished	Jul 10 06:43:54 PM PDT 24
Peak memory	263776 kb
Host	smart-4765deef-7020-4316-9cc0-43cb1e1422c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278204872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.2278204872
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2268872709
Short name	T1180
Test name
Test status
Simulation time	48000600 ps
CPU time	14.02 seconds
Started	Jul 10 06:29:25 PM PDT 24
Finished	Jul 10 06:29:40 PM PDT 24
Peak memory	261104 kb
Host	smart-4d0cb2e4-59e5-4f52-a076-0bd149a5263f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268872709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 2268872709
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.622591732
Short name	T1217
Test name
Test status
Simulation time	26866100 ps
CPU time	13.6 seconds
Started	Jul 10 06:29:37 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261140 kb
Host	smart-836679fe-b3bf-4764-add8-1bec8c6dba3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622591732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.622591732
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1285973181
Short name	T1203
Test name
Test status
Simulation time	127875300 ps
CPU time	13.75 seconds
Started	Jul 10 06:29:36 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261224 kb
Host	smart-26fd05ff-43f9-43d8-adad-f0dc576007f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285973181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 1285973181
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3532226306
Short name	T1119
Test name
Test status
Simulation time	16307900 ps
CPU time	13.94 seconds
Started	Jul 10 06:29:33 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261108 kb
Host	smart-c0050550-34f7-4a9b-a6fe-05a770cb26b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532226306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test. 3532226306
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2453601927
Short name	T1209
Test name
Test status
Simulation time	47689600 ps
CPU time	13.74 seconds
Started	Jul 10 06:29:33 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261180 kb
Host	smart-587b0414-6896-4fb5-a9c6-3a051bae86e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453601927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test. 2453601927
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2622592166
Short name	T1216
Test name
Test status
Simulation time	27496500 ps
CPU time	13.8 seconds
Started	Jul 10 06:29:34 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261080 kb
Host	smart-f360eee7-af15-4be7-b45b-fc091eff538e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622592166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 2622592166
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2576897634
Short name	T1244
Test name
Test status
Simulation time	48247600 ps
CPU time	13.37 seconds
Started	Jul 10 06:29:38 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261196 kb
Host	smart-3b7f0f17-3611-4db0-8081-e59f5eb80143
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576897634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test. 2576897634
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4132730413
Short name	T1131
Test name
Test status
Simulation time	79608500 ps
CPU time	13.43 seconds
Started	Jul 10 06:29:35 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261248 kb
Host	smart-d50a12a0-cf44-4992-acbd-f36cbc87b1d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132730413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 4132730413
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3115264149
Short name	T1132
Test name
Test status
Simulation time	17956000 ps
CPU time	14.06 seconds
Started	Jul 10 06:29:33 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261108 kb
Host	smart-442323e7-4ea2-42b6-94d1-1745da7ad484
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115264149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 3115264149
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1724627358
Short name	T1199
Test name
Test status
Simulation time	21540100 ps
CPU time	14.39 seconds
Started	Jul 10 06:29:33 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261108 kb
Host	smart-aaaf890f-afb1-4b2d-8ae6-7b5d2bd21d1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724627358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test. 1724627358
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.4063336248
Short name	T1235
Test name
Test status
Simulation time	389011700 ps
CPU time	30.32 seconds
Started	Jul 10 06:28:50 PM PDT 24
Finished	Jul 10 06:29:21 PM PDT 24
Peak memory	261332 kb
Host	smart-3ac31fdc-8c3f-41f7-ac24-9b5c57e322b6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063336248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.4063336248
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4139660421
Short name	T1146
Test name
Test status
Simulation time	1280731200 ps
CPU time	40.48 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:34 PM PDT 24
Peak memory	261208 kb
Host	smart-40336fe2-716d-4fdf-816b-b1d050ad104f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139660421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.4139660421
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.4213063626
Short name	T1246
Test name
Test status
Simulation time	49777500 ps
CPU time	31.14 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:25 PM PDT 24
Peak memory	261340 kb
Host	smart-24435024-44b8-47dd-ac08-e2068a628a09
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213063626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.4213063626
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3386072372
Short name	T1241
Test name
Test status
Simulation time	161264000 ps
CPU time	17.04 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:10 PM PDT 24
Peak memory	272044 kb
Host	smart-0ee10bfc-97bf-4c77-a7a6-75458d967781
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386072372 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.3386072372
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3978178151
Short name	T1173
Test name
Test status
Simulation time	210949400 ps
CPU time	17.4 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:10 PM PDT 24
Peak memory	261208 kb
Host	smart-a34dbdb5-8695-4b9f-8324-fe325d41a457
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978178151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.3978178151
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1325981129
Short name	T1188
Test name
Test status
Simulation time	53800900 ps
CPU time	13.44 seconds
Started	Jul 10 06:28:48 PM PDT 24
Finished	Jul 10 06:29:03 PM PDT 24
Peak memory	261224 kb
Host	smart-13c5278d-6548-4f30-87bc-5fd02b36dbb6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325981129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1 325981129
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1759142111
Short name	T224
Test name
Test status
Simulation time	143821300 ps
CPU time	13.52 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:07 PM PDT 24
Peak memory	262648 kb
Host	smart-fe6a59ad-b0fe-485c-93cc-809702dfc37d
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759142111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.1759142111
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4284734170
Short name	T1121
Test name
Test status
Simulation time	16188400 ps
CPU time	14.12 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:07 PM PDT 24
Peak memory	261016 kb
Host	smart-6df0fa38-75a9-4f02-8f74-878fdfeabbd1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284734170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.4284734170
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2533260261
Short name	T1236
Test name
Test status
Simulation time	232387900 ps
CPU time	19.44 seconds
Started	Jul 10 06:28:53 PM PDT 24
Finished	Jul 10 06:29:13 PM PDT 24
Peak memory	261524 kb
Host	smart-ad8f5bce-7827-4fdd-bc1b-07eb9638255d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533260261 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2533260261
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2714553310
Short name	T1114
Test name
Test status
Simulation time	16193500 ps
CPU time	16.14 seconds
Started	Jul 10 06:28:50 PM PDT 24
Finished	Jul 10 06:29:07 PM PDT 24
Peak memory	253012 kb
Host	smart-0fd56caa-899e-4efb-895b-ebfa1b6922d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714553310 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2714553310
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4047498854
Short name	T1211
Test name
Test status
Simulation time	28035700 ps
CPU time	15.75 seconds
Started	Jul 10 06:28:48 PM PDT 24
Finished	Jul 10 06:29:05 PM PDT 24
Peak memory	252988 kb
Host	smart-5d5c0eec-f21d-4288-9aa1-9aeed533f069
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047498854 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.4047498854
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1351889910
Short name	T246
Test name
Test status
Simulation time	718356300 ps
CPU time	457.86 seconds
Started	Jul 10 06:28:49 PM PDT 24
Finished	Jul 10 06:36:28 PM PDT 24
Peak memory	263752 kb
Host	smart-f6e01cc8-37a2-4496-ac84-1b01c601d826
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351889910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.1351889910
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.178357886
Short name	T1129
Test name
Test status
Simulation time	49602700 ps
CPU time	13.57 seconds
Started	Jul 10 06:29:35 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261108 kb
Host	smart-16cd367d-8d8a-49b3-87e0-92a18e2d7122
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178357886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.178357886
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.207999350
Short name	T1168
Test name
Test status
Simulation time	101730400 ps
CPU time	13.32 seconds
Started	Jul 10 06:29:33 PM PDT 24
Finished	Jul 10 06:29:50 PM PDT 24
Peak memory	261108 kb
Host	smart-902a3021-d490-4d72-9c34-ed5eaac6bc2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207999350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.207999350
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2884312450
Short name	T1139
Test name
Test status
Simulation time	27381000 ps
CPU time	13.86 seconds
Started	Jul 10 06:29:37 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261144 kb
Host	smart-a13639a9-b28b-45a9-abd0-ce3fb39242e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884312450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 2884312450
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.314180514
Short name	T1156
Test name
Test status
Simulation time	52934900 ps
CPU time	13.72 seconds
Started	Jul 10 06:29:35 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261236 kb
Host	smart-95be8493-7d5d-41fc-ab28-e9ad30f80502
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314180514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.314180514
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2212976653
Short name	T1192
Test name
Test status
Simulation time	27362900 ps
CPU time	13.56 seconds
Started	Jul 10 06:29:35 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261236 kb
Host	smart-ba29b7a0-7967-4c07-977a-2cde0d489944
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212976653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test. 2212976653
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1003680287
Short name	T1214
Test name
Test status
Simulation time	19953500 ps
CPU time	13.43 seconds
Started	Jul 10 06:29:35 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261084 kb
Host	smart-9428d3d1-d171-40bb-92a9-8e42dea7305e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003680287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 1003680287
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3272614965
Short name	T243
Test name
Test status
Simulation time	16054200 ps
CPU time	14.19 seconds
Started	Jul 10 06:29:34 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261104 kb
Host	smart-3297457e-9205-4e96-80e2-da298790ddbf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272614965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 3272614965
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3322323080
Short name	T1185
Test name
Test status
Simulation time	15352000 ps
CPU time	13.61 seconds
Started	Jul 10 06:29:34 PM PDT 24
Finished	Jul 10 06:29:51 PM PDT 24
Peak memory	261240 kb
Host	smart-baa4cff9-a502-48d2-adf2-436505665225
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322323080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 3322323080
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1737469903
Short name	T1196
Test name
Test status
Simulation time	85134500 ps
CPU time	13.45 seconds
Started	Jul 10 06:29:42 PM PDT 24
Finished	Jul 10 06:29:57 PM PDT 24
Peak memory	261256 kb
Host	smart-79585050-f5f2-4243-a05f-06541804dafe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737469903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test. 1737469903
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2314573584
Short name	T1248
Test name
Test status
Simulation time	49830800 ps
CPU time	13.19 seconds
Started	Jul 10 06:29:38 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261292 kb
Host	smart-f0ca6a79-c818-440a-9c03-151815e94ffe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314573584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test. 2314573584
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.163549517
Short name	T291
Test name
Test status
Simulation time	9905131200 ps
CPU time	40.11 seconds
Started	Jul 10 06:28:59 PM PDT 24
Finished	Jul 10 06:29:41 PM PDT 24
Peak memory	261284 kb
Host	smart-5e6838a5-29cf-435c-84aa-c19af75695ff
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163549517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.flash_ctrl_csr_aliasing.163549517
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2286119475
Short name	T1227
Test name
Test status
Simulation time	4767589700 ps
CPU time	41.53 seconds
Started	Jul 10 06:28:59 PM PDT 24
Finished	Jul 10 06:29:42 PM PDT 24
Peak memory	261216 kb
Host	smart-e853dd72-8bfb-4f97-8d91-f7a80aadb42b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286119475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.2286119475
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2231618031
Short name	T1150
Test name
Test status
Simulation time	45607100 ps
CPU time	30.57 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	261276 kb
Host	smart-f9600e72-06f3-41b4-a8ac-c28dfd756999
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231618031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.2231618031
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1059300088
Short name	T220
Test name
Test status
Simulation time	44482300 ps
CPU time	18.36 seconds
Started	Jul 10 06:28:55 PM PDT 24
Finished	Jul 10 06:29:14 PM PDT 24
Peak memory	272000 kb
Host	smart-babe88ef-b3de-49dc-b74e-092158dd3c32
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059300088 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1059300088
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.810695520
Short name	T1135
Test name
Test status
Simulation time	19331000 ps
CPU time	13.8 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:29:06 PM PDT 24
Peak memory	263748 kb
Host	smart-bf9b6a53-0b38-4bd2-9bdc-b7ff967d631b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810695520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_csr_rw.810695520
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.354713977
Short name	T1184
Test name
Test status
Simulation time	29696200 ps
CPU time	13.32 seconds
Started	Jul 10 06:28:51 PM PDT 24
Finished	Jul 10 06:29:04 PM PDT 24
Peak memory	261220 kb
Host	smart-92e8b9b0-19a4-480a-86df-c4e2ed2d68c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354713977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.354713977
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1046080533
Short name	T226
Test name
Test status
Simulation time	17413900 ps
CPU time	13.93 seconds
Started	Jul 10 06:28:53 PM PDT 24
Finished	Jul 10 06:29:08 PM PDT 24
Peak memory	262844 kb
Host	smart-fe55e500-7a60-478b-bac9-752975956478
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046080533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.1046080533
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3783440369
Short name	T1239
Test name
Test status
Simulation time	211122600 ps
CPU time	13.53 seconds
Started	Jul 10 06:28:53 PM PDT 24
Finished	Jul 10 06:29:08 PM PDT 24
Peak memory	261012 kb
Host	smart-ba367dd9-cbb2-436d-84c1-d5c800687676
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783440369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.3783440369
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3619935536
Short name	T1233
Test name
Test status
Simulation time	153892300 ps
CPU time	30.36 seconds
Started	Jul 10 06:28:53 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	261344 kb
Host	smart-21a637ea-b6f6-4d53-9869-21b87d16952c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619935536 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3619935536
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2076345241
Short name	T1230
Test name
Test status
Simulation time	22507300 ps
CPU time	15.79 seconds
Started	Jul 10 06:28:54 PM PDT 24
Finished	Jul 10 06:29:11 PM PDT 24
Peak memory	253076 kb
Host	smart-897d92de-f773-4195-b78c-78788ee87133
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076345241 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2076345241
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3830971321
Short name	T1177
Test name
Test status
Simulation time	12512400 ps
CPU time	15.59 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:16 PM PDT 24
Peak memory	253016 kb
Host	smart-b9518a54-f666-45f3-b987-a15d660081a8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830971321 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3830971321
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2068821241
Short name	T240
Test name
Test status
Simulation time	57077700 ps
CPU time	15.79 seconds
Started	Jul 10 06:28:54 PM PDT 24
Finished	Jul 10 06:29:10 PM PDT 24
Peak memory	263720 kb
Host	smart-525d4fa6-14cd-466d-b62f-56b544675ba7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068821241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2 068821241
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2239322169
Short name	T327
Test name
Test status
Simulation time	179671600 ps
CPU time	458.52 seconds
Started	Jul 10 06:28:52 PM PDT 24
Finished	Jul 10 06:36:31 PM PDT 24
Peak memory	263720 kb
Host	smart-6b338a22-79b1-41d2-9598-5b9943a1fa5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239322169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.2239322169
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4279077674
Short name	T1231
Test name
Test status
Simulation time	16845800 ps
CPU time	14.13 seconds
Started	Jul 10 06:29:41 PM PDT 24
Finished	Jul 10 06:29:57 PM PDT 24
Peak memory	261092 kb
Host	smart-e65210c2-fef6-4797-ba1c-2cd2a2939ce5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279077674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 4279077674
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3471028206
Short name	T1159
Test name
Test status
Simulation time	30950400 ps
CPU time	13.14 seconds
Started	Jul 10 06:29:37 PM PDT 24
Finished	Jul 10 06:29:52 PM PDT 24
Peak memory	261344 kb
Host	smart-3af3a659-e9ca-4717-97ff-c9ed1c7befc8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471028206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 3471028206
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.4253181778
Short name	T1178
Test name
Test status
Simulation time	99016100 ps
CPU time	13.57 seconds
Started	Jul 10 06:29:39 PM PDT 24
Finished	Jul 10 06:29:55 PM PDT 24
Peak memory	261172 kb
Host	smart-a20bc045-ed39-407d-8457-7f513d4311d4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253181778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 4253181778
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4035185452
Short name	T1179
Test name
Test status
Simulation time	33495200 ps
CPU time	13.48 seconds
Started	Jul 10 06:29:39 PM PDT 24
Finished	Jul 10 06:29:54 PM PDT 24
Peak memory	261228 kb
Host	smart-56485db6-99eb-4e6e-a666-e3e4d09f5272
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035185452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 4035185452
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.802678280
Short name	T1157
Test name
Test status
Simulation time	18419100 ps
CPU time	13.64 seconds
Started	Jul 10 06:29:41 PM PDT 24
Finished	Jul 10 06:29:57 PM PDT 24
Peak memory	261140 kb
Host	smart-e807df36-c953-4285-83df-b242529b7131
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802678280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.802678280
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2284224530
Short name	T1169
Test name
Test status
Simulation time	18014000 ps
CPU time	13.42 seconds
Started	Jul 10 06:29:40 PM PDT 24
Finished	Jul 10 06:29:56 PM PDT 24
Peak memory	261112 kb
Host	smart-b5266b2b-7383-4015-979a-e0315f9cf707
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284224530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 2284224530
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2184668153
Short name	T319
Test name
Test status
Simulation time	53365000 ps
CPU time	14.02 seconds
Started	Jul 10 06:29:39 PM PDT 24
Finished	Jul 10 06:29:55 PM PDT 24
Peak memory	261240 kb
Host	smart-0083c0c8-391d-4379-be95-4a55dbb5de59
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184668153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 2184668153
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3118765146
Short name	T1194
Test name
Test status
Simulation time	16357300 ps
CPU time	14.03 seconds
Started	Jul 10 06:29:38 PM PDT 24
Finished	Jul 10 06:29:54 PM PDT 24
Peak memory	261176 kb
Host	smart-6f2495dc-0275-4dcf-8b5c-f826a97cb754
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118765146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 3118765146
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.901904505
Short name	T1207
Test name
Test status
Simulation time	52900300 ps
CPU time	13.57 seconds
Started	Jul 10 06:29:42 PM PDT 24
Finished	Jul 10 06:29:57 PM PDT 24
Peak memory	261172 kb
Host	smart-626034e4-e388-487b-a496-7261987c4522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901904505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.901904505
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3395732811
Short name	T244
Test name
Test status
Simulation time	29184400 ps
CPU time	13.28 seconds
Started	Jul 10 06:29:40 PM PDT 24
Finished	Jul 10 06:29:55 PM PDT 24
Peak memory	261236 kb
Host	smart-1762d295-906b-4feb-889e-11569bff6b20
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395732811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test. 3395732811
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1035665046
Short name	T288
Test name
Test status
Simulation time	385471600 ps
CPU time	19.21 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:29:19 PM PDT 24
Peak memory	270372 kb
Host	smart-687d3988-e8ab-40f5-a948-555a76a077cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035665046 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1035665046
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4053965589
Short name	T1257
Test name
Test status
Simulation time	230097400 ps
CPU time	17.19 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:18 PM PDT 24
Peak memory	261704 kb
Host	smart-d8c5f894-14e6-4aad-bbb8-06632ea88a1e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053965589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.4053965589
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3382866732
Short name	T1162
Test name
Test status
Simulation time	161752200 ps
CPU time	13.39 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:15 PM PDT 24
Peak memory	261240 kb
Host	smart-84959224-1495-4aa6-bb6b-f8732b15d833
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382866732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3 382866732
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.365931604
Short name	T282
Test name
Test status
Simulation time	780019100 ps
CPU time	20.43 seconds
Started	Jul 10 06:28:57 PM PDT 24
Finished	Jul 10 06:29:18 PM PDT 24
Peak memory	263612 kb
Host	smart-c04bd99a-0626-47e9-8c28-e47b8190a3b7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365931604 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.365931604
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4256589866
Short name	T1261
Test name
Test status
Simulation time	18584600 ps
CPU time	13.29 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:29:12 PM PDT 24
Peak memory	252944 kb
Host	smart-f3ca6cf1-8ae5-4eaf-8f4b-a7fcd32d4fb3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256589866 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.4256589866
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1106632903
Short name	T1137
Test name
Test status
Simulation time	63235600 ps
CPU time	14.06 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:15 PM PDT 24
Peak memory	252952 kb
Host	smart-97ca5219-a095-42e3-b7cc-e3313f7329b1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106632903 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1106632903
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1850693020
Short name	T242
Test name
Test status
Simulation time	62444200 ps
CPU time	19.66 seconds
Started	Jul 10 06:28:57 PM PDT 24
Finished	Jul 10 06:29:18 PM PDT 24
Peak memory	263724 kb
Host	smart-44c3cfec-4f07-45ee-95db-a011de8f417e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850693020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1 850693020
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.76831930
Short name	T219
Test name
Test status
Simulation time	727510500 ps
CPU time	17.08 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:18 PM PDT 24
Peak memory	271992 kb
Host	smart-374dea34-4fab-43f5-a0aa-1903c3e4a0d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76831930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.76831930
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1142887362
Short name	T283
Test name
Test status
Simulation time	66799000 ps
CPU time	15.66 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:17 PM PDT 24
Peak memory	263756 kb
Host	smart-fff04894-d4bc-4ec9-bce0-bdac0b08bd17
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142887362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.1142887362
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3052076842
Short name	T321
Test name
Test status
Simulation time	31632700 ps
CPU time	13.52 seconds
Started	Jul 10 06:28:57 PM PDT 24
Finished	Jul 10 06:29:12 PM PDT 24
Peak memory	261116 kb
Host	smart-f9b2161a-043e-44bb-9217-0da218fcfef7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052076842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3 052076842
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3702084657
Short name	T1226
Test name
Test status
Simulation time	462728700 ps
CPU time	20.02 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:29:19 PM PDT 24
Peak memory	261320 kb
Host	smart-622263d3-3415-4e10-bd0b-8f79eb8b7b30
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702084657 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3702084657
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2036710644
Short name	T1222
Test name
Test status
Simulation time	12424000 ps
CPU time	15.84 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:17 PM PDT 24
Peak memory	252960 kb
Host	smart-fdeca16e-52c1-49a4-98ec-25c0fdd1d66e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036710644 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2036710644
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2710248449
Short name	T1242
Test name
Test status
Simulation time	44606500 ps
CPU time	13.05 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:29:14 PM PDT 24
Peak memory	253080 kb
Host	smart-98a8a9dc-45eb-4ce9-9a5b-167fcfb05566
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710248449 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2710248449
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.432371973
Short name	T1251
Test name
Test status
Simulation time	118551200 ps
CPU time	15.68 seconds
Started	Jul 10 06:28:59 PM PDT 24
Finished	Jul 10 06:29:16 PM PDT 24
Peak memory	263728 kb
Host	smart-baad8d07-7025-4aee-b85d-88f453153b8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432371973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.432371973
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1416951259
Short name	T1240
Test name
Test status
Simulation time	1778048000 ps
CPU time	466.41 seconds
Started	Jul 10 06:29:00 PM PDT 24
Finished	Jul 10 06:36:48 PM PDT 24
Peak memory	263756 kb
Host	smart-e9915df0-3d19-4a21-8e4a-b2179d36bfd6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416951259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl _tl_intg_err.1416951259
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1518019516
Short name	T1152
Test name
Test status
Simulation time	661267700 ps
CPU time	18.7 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	272008 kb
Host	smart-d00ed956-f91b-4b87-bded-ef02d132f10e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518019516 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1518019516
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3194266593
Short name	T1155
Test name
Test status
Simulation time	38306200 ps
CPU time	13.81 seconds
Started	Jul 10 06:28:56 PM PDT 24
Finished	Jul 10 06:29:11 PM PDT 24
Peak memory	263720 kb
Host	smart-50c0b63f-3669-48f0-8a3a-ea21f16a8c10
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194266593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.flash_ctrl_csr_rw.3194266593
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3312464835
Short name	T1228
Test name
Test status
Simulation time	13977500 ps
CPU time	13.78 seconds
Started	Jul 10 06:28:57 PM PDT 24
Finished	Jul 10 06:29:12 PM PDT 24
Peak memory	261176 kb
Host	smart-50575488-b7b9-447e-80e0-dc832c8b9a8c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312464835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3 312464835
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1099102637
Short name	T1161
Test name
Test status
Simulation time	67523400 ps
CPU time	17.58 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:29:17 PM PDT 24
Peak memory	263752 kb
Host	smart-7cad9184-636d-430e-bba6-5931651829be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099102637 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1099102637
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.632887575
Short name	T1223
Test name
Test status
Simulation time	12991400 ps
CPU time	13.31 seconds
Started	Jul 10 06:28:59 PM PDT 24
Finished	Jul 10 06:29:14 PM PDT 24
Peak memory	253028 kb
Host	smart-635b5732-91f8-4122-a33d-bcf1489b241c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632887575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.632887575
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3340781465
Short name	T1148
Test name
Test status
Simulation time	33522000 ps
CPU time	13.34 seconds
Started	Jul 10 06:28:56 PM PDT 24
Finished	Jul 10 06:29:10 PM PDT 24
Peak memory	253064 kb
Host	smart-21602d63-de5c-4540-a310-d216b626c2a6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340781465 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3340781465
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2123515985
Short name	T205
Test name
Test status
Simulation time	152385800 ps
CPU time	18.62 seconds
Started	Jul 10 06:28:57 PM PDT 24
Finished	Jul 10 06:29:17 PM PDT 24
Peak memory	263712 kb
Host	smart-652993da-a02e-4259-9562-9a478753aea8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123515985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2 123515985
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1987523213
Short name	T323
Test name
Test status
Simulation time	409670100 ps
CPU time	452.47 seconds
Started	Jul 10 06:28:58 PM PDT 24
Finished	Jul 10 06:36:32 PM PDT 24
Peak memory	263740 kb
Host	smart-0584bad2-35a5-4695-a07b-d2076ebe188d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987523213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.1987523213
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.339009201
Short name	T1189
Test name
Test status
Simulation time	103666100 ps
CPU time	18.29 seconds
Started	Jul 10 06:29:03 PM PDT 24
Finished	Jul 10 06:29:23 PM PDT 24
Peak memory	277840 kb
Host	smart-91689883-7cdf-44f7-a2e7-3ceed4c8b14f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339009201 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.339009201
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1815689963
Short name	T1250
Test name
Test status
Simulation time	25495100 ps
CPU time	16.55 seconds
Started	Jul 10 06:29:03 PM PDT 24
Finished	Jul 10 06:29:20 PM PDT 24
Peak memory	263712 kb
Host	smart-7fb2fdb0-66b6-42d1-872d-72016242c104
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815689963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.1815689963
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1449362812
Short name	T1198
Test name
Test status
Simulation time	18064000 ps
CPU time	14.05 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:29:19 PM PDT 24
Peak memory	261116 kb
Host	smart-bc2e74ee-d10b-4f36-a00b-600a4cbbf416
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449362812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1 449362812
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3397072901
Short name	T1167
Test name
Test status
Simulation time	552920000 ps
CPU time	18.43 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:29:24 PM PDT 24
Peak memory	262564 kb
Host	smart-fa2734c6-b36d-4b3b-83d0-341a54c4cc21
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397072901 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3397072901
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3412359699
Short name	T1213
Test name
Test status
Simulation time	24424100 ps
CPU time	15.68 seconds
Started	Jul 10 06:29:03 PM PDT 24
Finished	Jul 10 06:29:20 PM PDT 24
Peak memory	252948 kb
Host	smart-c33aa0d7-d868-4a73-a9ec-12574b37bc1f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412359699 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3412359699
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.560015975
Short name	T1243
Test name
Test status
Simulation time	18480600 ps
CPU time	15.88 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:29:21 PM PDT 24
Peak memory	252860 kb
Host	smart-b5d40979-e831-4405-a144-c5a3a14de4ed
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560015975 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.560015975
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1115256007
Short name	T107
Test name
Test status
Simulation time	68977000 ps
CPU time	16.12 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:29:21 PM PDT 24
Peak memory	263700 kb
Host	smart-ebc18c16-f299-4327-ace1-0d8ed0e0fbd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115256007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1 115256007
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2473597594
Short name	T328
Test name
Test status
Simulation time	9340922000 ps
CPU time	914.13 seconds
Started	Jul 10 06:29:05 PM PDT 24
Finished	Jul 10 06:44:20 PM PDT 24
Peak memory	263944 kb
Host	smart-b8b3c454-99d2-4893-b56d-84d1566f4e9f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473597594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.2473597594
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3743656603
Short name	T1183
Test name
Test status
Simulation time	204495000 ps
CPU time	17.77 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:30 PM PDT 24
Peak memory	271188 kb
Host	smart-c3c5a3c3-a509-449d-9234-48e5ba77670f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743656603 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3743656603
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.727434171
Short name	T1215
Test name
Test status
Simulation time	159603100 ps
CPU time	16.23 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:34 PM PDT 24
Peak memory	263652 kb
Host	smart-26e0b072-c65e-4f6d-820f-aed310a69c4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727434171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_csr_rw.727434171
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1024129547
Short name	T1144
Test name
Test status
Simulation time	15899700 ps
CPU time	14.05 seconds
Started	Jul 10 06:29:09 PM PDT 24
Finished	Jul 10 06:29:26 PM PDT 24
Peak memory	261180 kb
Host	smart-0d39afbd-4699-465d-abfd-93d0cc3e9e6f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024129547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1 024129547
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.382221347
Short name	T289
Test name
Test status
Simulation time	403958000 ps
CPU time	15.23 seconds
Started	Jul 10 06:29:15 PM PDT 24
Finished	Jul 10 06:29:32 PM PDT 24
Peak memory	262404 kb
Host	smart-11f59d63-0c42-4b12-8b94-0679b4b4baac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382221347 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.382221347
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.18556445
Short name	T1245
Test name
Test status
Simulation time	14573700 ps
CPU time	15.99 seconds
Started	Jul 10 06:29:03 PM PDT 24
Finished	Jul 10 06:29:20 PM PDT 24
Peak memory	252820 kb
Host	smart-d1e325d8-26b9-4911-b7c8-30cf98c8f221
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.18556445
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3002357654
Short name	T1153
Test name
Test status
Simulation time	14365200 ps
CPU time	15.58 seconds
Started	Jul 10 06:29:06 PM PDT 24
Finished	Jul 10 06:29:22 PM PDT 24
Peak memory	252888 kb
Host	smart-1da7dc29-193d-464e-864f-39d4b354ce88
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002357654 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3002357654
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3848759582
Short name	T1170
Test name
Test status
Simulation time	54650200 ps
CPU time	16.61 seconds
Started	Jul 10 06:29:02 PM PDT 24
Finished	Jul 10 06:29:20 PM PDT 24
Peak memory	263148 kb
Host	smart-4230d30f-217f-415d-8a68-7a73840e015d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848759582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3 848759582
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3926930052
Short name	T1237
Test name
Test status
Simulation time	586235300 ps
CPU time	385.49 seconds
Started	Jul 10 06:29:04 PM PDT 24
Finished	Jul 10 06:35:31 PM PDT 24
Peak memory	263752 kb
Host	smart-4f54dddc-c409-4a30-8102-c1cccbb23cba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926930052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl _tl_intg_err.3926930052
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.1647113516
Short name	T541
Test name
Test status
Simulation time	27596900 ps
CPU time	13.46 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 07:24:36 PM PDT 24
Peak memory	258508 kb
Host	smart-15ea2896-9ecd-4205-b12e-f189d0f9ac70
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647113516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.1 647113516
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.2531975274
Short name	T538
Test name
Test status
Simulation time	2046786700 ps
CPU time	420.91 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:31:19 PM PDT 24
Peak memory	263476 kb
Host	smart-42e71893-8d0b-42f1-9f11-71973520062f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2531975274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2531975274
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.1818025193
Short name	T88
Test name
Test status
Simulation time	1085393400 ps
CPU time	2148.66 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 08:00:04 PM PDT 24
Peak memory	265236 kb
Host	smart-b74961c5-4735-45f3-b095-6ea4c4690db3
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818025193 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1818025193
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.2083263563
Short name	T57
Test name
Test status
Simulation time	679938200 ps
CPU time	25.41 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:24:48 PM PDT 24
Peak memory	262600 kb
Host	smart-46015e63-02b3-4420-afb7-0eeaa7ea7983
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083263563 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2083263563
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.1512883583
Short name	T261
Test name
Test status
Simulation time	1315781300 ps
CPU time	41.34 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:25:02 PM PDT 24
Peak memory	264964 kb
Host	smart-c1134ada-77c7-427d-b4cc-069f3dea3c76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512883583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.1512883583
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.1801958641
Short name	T51
Test name
Test status
Simulation time	38933200 ps
CPU time	30.18 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:24:57 PM PDT 24
Peak memory	275668 kb
Host	smart-10e773ff-bbd3-4363-8cb1-2d54947e8740
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801958641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.1801958641
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2134895699
Short name	T994
Test name
Test status
Simulation time	516495852400 ps
CPU time	2144.04 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 08:00:06 PM PDT 24
Peak memory	264192 kb
Host	smart-f72bbc7a-0a8e-4b8f-84f0-b9964b784ae7
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134895699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_host_ctrl_arb.2134895699
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.1487035810
Short name	T678
Test name
Test status
Simulation time	61757300 ps
CPU time	100.67 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:25:59 PM PDT 24
Peak memory	262544 kb
Host	smart-512f5096-9854-4f3a-b61e-8af077ad2c73
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1487035810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1487035810
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1808141695
Short name	T271
Test name
Test status
Simulation time	25778700 ps
CPU time	13.44 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:24:40 PM PDT 24
Peak memory	260276 kb
Host	smart-ce382f3d-73e8-457e-a2de-69b1fd660d5a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808141695 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1808141695
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3282381376
Short name	T573
Test name
Test status
Simulation time	100143556100 ps
CPU time	857.72 seconds
Started	Jul 10 07:24:08 PM PDT 24
Finished	Jul 10 07:38:29 PM PDT 24
Peak memory	261084 kb
Host	smart-30b41e79-36b9-44cf-8ab3-a037d4ee43fb
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282381376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.3282381376
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2564061916
Short name	T656
Test name
Test status
Simulation time	1907434700 ps
CPU time	79.4 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:25:36 PM PDT 24
Peak memory	260872 kb
Host	smart-9dcc7bac-e33b-4082-9d2c-83185f20ea0a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564061916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h w_sec_otp.2564061916
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_integrity.3468844536
Short name	T991
Test name
Test status
Simulation time	4134442800 ps
CPU time	746.65 seconds
Started	Jul 10 07:24:09 PM PDT 24
Finished	Jul 10 07:36:40 PM PDT 24
Peak memory	335880 kb
Host	smart-142ac6fe-1897-4552-99e0-010bcb3895b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468844536 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_integrity.3468844536
Directory	/workspace/0.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.390902415
Short name	T1109
Test name
Test status
Simulation time	1701922600 ps
CPU time	212.72 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:27:53 PM PDT 24
Peak memory	284828 kb
Host	smart-366ca2c2-c12e-4237-bf6d-7dca7e88e9e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390902415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash _ctrl_intr_rd.390902415
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.708240795
Short name	T1011
Test name
Test status
Simulation time	23266164100 ps
CPU time	297.58 seconds
Started	Jul 10 07:24:08 PM PDT 24
Finished	Jul 10 07:29:09 PM PDT 24
Peak memory	284968 kb
Host	smart-004fc629-9efe-4cb7-b0ab-747e3339aa85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708240795 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.708240795
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1294051690
Short name	T785
Test name
Test status
Simulation time	22300626300 ps
CPU time	201.4 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:27:39 PM PDT 24
Peak memory	260008 kb
Host	smart-2bb7170f-51c9-4aab-ac1a-545db7ddbbdf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129 4051690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1294051690
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.3742904728
Short name	T294
Test name
Test status
Simulation time	4070603100 ps
CPU time	91.37 seconds
Started	Jul 10 07:24:08 PM PDT 24
Finished	Jul 10 07:25:42 PM PDT 24
Peak memory	263412 kb
Host	smart-e44b7aa8-0c74-4df7-beef-adf95970c49a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742904728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3742904728
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.1896505075
Short name	T94
Test name
Test status
Simulation time	3433543700 ps
CPU time	69.77 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:25:32 PM PDT 24
Peak memory	260612 kb
Host	smart-7ee5b2d5-1ee4-4ebd-b333-3b36189a2bce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1896505075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1896505075
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.1278286603
Short name	T209
Test name
Test status
Simulation time	37869786600 ps
CPU time	140.16 seconds
Started	Jul 10 07:24:10 PM PDT 24
Finished	Jul 10 07:26:34 PM PDT 24
Peak memory	265156 kb
Host	smart-82be9aa6-6dbb-4fa5-8586-2c2d6362ce12
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278286603 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.1278286603
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.784206316
Short name	T709
Test name
Test status
Simulation time	38873300 ps
CPU time	132.93 seconds
Started	Jul 10 07:24:08 PM PDT 24
Finished	Jul 10 07:26:25 PM PDT 24
Peak memory	264696 kb
Host	smart-0b295047-d827-4808-91c7-0d024dac514d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784206316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp _reset.784206316
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.423525999
Short name	T835
Test name
Test status
Simulation time	2146740700 ps
CPU time	141.83 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:26:39 PM PDT 24
Peak memory	281836 kb
Host	smart-adcc76c9-16f5-458f-aac8-0e6b0e85508b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423525999 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.423525999
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.1869908350
Short name	T455
Test name
Test status
Simulation time	64795600 ps
CPU time	314.84 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:29:32 PM PDT 24
Peak memory	263312 kb
Host	smart-e1aef766-568b-49b1-a7fc-3b8271c31cb2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1869908350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1869908350
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.2403359845
Short name	T716
Test name
Test status
Simulation time	1120775100 ps
CPU time	924.51 seconds
Started	Jul 10 07:24:10 PM PDT 24
Finished	Jul 10 07:39:40 PM PDT 24
Peak memory	284536 kb
Host	smart-752bcfb5-c026-4e42-b6e5-b314ca90b092
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403359845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2403359845
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2329586749
Short name	T759
Test name
Test status
Simulation time	770335200 ps
CPU time	120.54 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	262880 kb
Host	smart-eb53bded-b786-4e51-9c6e-052647af1577
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2329586749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2329586749
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.2957996658
Short name	T816
Test name
Test status
Simulation time	72041500 ps
CPU time	31.88 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:24:56 PM PDT 24
Peak memory	272320 kb
Host	smart-38a01d6d-42bb-44ad-bb15-9237d885d026
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957996658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.2957996658
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.3177950349
Short name	T561
Test name
Test status
Simulation time	1093061500 ps
CPU time	47.93 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:25:12 PM PDT 24
Peak memory	281652 kb
Host	smart-676473f1-21f1-4275-9fc3-6089437a521f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177950349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_rd_ooo.3177950349
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.2306048941
Short name	T866
Test name
Test status
Simulation time	24971000 ps
CPU time	14.45 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 07:24:30 PM PDT 24
Peak memory	265312 kb
Host	smart-a7c55e0a-149f-4954-a577-abd9eedb2ad2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2306048941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep .2306048941
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3450259572
Short name	T837
Test name
Test status
Simulation time	106997800 ps
CPU time	22.46 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:24:44 PM PDT 24
Peak memory	265388 kb
Host	smart-4d9a3aa4-d379-4d3c-adee-8420832fae08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450259572 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3450259572
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1505032027
Short name	T732
Test name
Test status
Simulation time	93142500 ps
CPU time	22.57 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:24:45 PM PDT 24
Peak memory	265404 kb
Host	smart-78700887-4f63-41de-b0c4-15f94678d63c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505032027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.1505032027
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.2014815865
Short name	T661
Test name
Test status
Simulation time	998595200 ps
CPU time	105.68 seconds
Started	Jul 10 07:24:10 PM PDT 24
Finished	Jul 10 07:26:00 PM PDT 24
Peak memory	290028 kb
Host	smart-238f39e7-0a3e-4d03-bbfd-02fd70fa718b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014815865 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_ro.2014815865
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.3524298110
Short name	T911
Test name
Test status
Simulation time	2143681500 ps
CPU time	132.54 seconds
Started	Jul 10 07:24:10 PM PDT 24
Finished	Jul 10 07:26:27 PM PDT 24
Peak memory	281860 kb
Host	smart-ee993390-3418-4b42-b8d2-c385ce1ae091
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3524298110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3524298110
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.3989189760
Short name	T1015
Test name
Test status
Simulation time	13070988600 ps
CPU time	595.14 seconds
Started	Jul 10 07:24:07 PM PDT 24
Finished	Jul 10 07:34:06 PM PDT 24
Peak memory	310068 kb
Host	smart-cea78b8c-87ca-4efe-97bd-beeabcd3c6ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989189760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.3989189760
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_derr.3657448920
Short name	T873
Test name
Test status
Simulation time	8626128200 ps
CPU time	580.07 seconds
Started	Jul 10 07:24:13 PM PDT 24
Finished	Jul 10 07:33:58 PM PDT 24
Peak memory	315872 kb
Host	smart-5b755188-cc02-4f78-b962-866571a499e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657448920 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.flash_ctrl_rw_derr.3657448920
Directory	/workspace/0.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.2584798169
Short name	T566
Test name
Test status
Simulation time	62053400 ps
CPU time	28.87 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:24:45 PM PDT 24
Peak memory	268540 kb
Host	smart-b6c5de3a-527e-43c5-886c-70ba91ae6efe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584798169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_rw_evict.2584798169
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1572822847
Short name	T665
Test name
Test status
Simulation time	30841700 ps
CPU time	31.14 seconds
Started	Jul 10 07:24:14 PM PDT 24
Finished	Jul 10 07:24:51 PM PDT 24
Peak memory	268680 kb
Host	smart-43bcc932-e2e5-4b82-8111-d87a98f1db08
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572822847 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1572822847
Directory	/workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.3686309204
Short name	T899
Test name
Test status
Simulation time	5838599200 ps
CPU time	67.38 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:25:24 PM PDT 24
Peak memory	263812 kb
Host	smart-f8a263fc-3916-4107-a507-61d755f80bb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686309204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3686309204
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.372569961
Short name	T1031
Test name
Test status
Simulation time	1523562000 ps
CPU time	107.45 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:26:09 PM PDT 24
Peak memory	265100 kb
Host	smart-57f8c302-1320-44af-93b4-daa19a477cfc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372569961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr_address.372569961
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.1219353055
Short name	T760
Test name
Test status
Simulation time	4503339200 ps
CPU time	90.98 seconds
Started	Jul 10 07:24:17 PM PDT 24
Finished	Jul 10 07:25:52 PM PDT 24
Peak memory	273588 kb
Host	smart-aff760d8-6abf-44e4-8e7a-cad01f0229d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219353055 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.1219353055
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.3522719766
Short name	T523
Test name
Test status
Simulation time	1396409700 ps
CPU time	138.69 seconds
Started	Jul 10 07:24:07 PM PDT 24
Finished	Jul 10 07:26:30 PM PDT 24
Peak memory	281636 kb
Host	smart-ca1e92bb-9a21-43e7-a027-c211f0f515ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522719766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3522719766
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.3484341117
Short name	T494
Test name
Test status
Simulation time	16307500 ps
CPU time	23.71 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 07:24:47 PM PDT 24
Peak memory	259744 kb
Host	smart-22ace32a-9be3-4ffa-b6ae-1fa53aa96228
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484341117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3484341117
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.4280390134
Short name	T215
Test name
Test status
Simulation time	90819100 ps
CPU time	62.23 seconds
Started	Jul 10 07:24:16 PM PDT 24
Finished	Jul 10 07:25:23 PM PDT 24
Peak memory	270580 kb
Host	smart-917cd5b6-af37-4d29-8a93-72d1decf904f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280390134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres s_all.4280390134
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.3867393841
Short name	T483
Test name
Test status
Simulation time	30898500 ps
CPU time	26.67 seconds
Started	Jul 10 07:24:12 PM PDT 24
Finished	Jul 10 07:24:44 PM PDT 24
Peak memory	262332 kb
Host	smart-1f8e867c-7f03-44b2-afd5-e5fbf2533337
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867393841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3867393841
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.505911073
Short name	T903
Test name
Test status
Simulation time	9163694000 ps
CPU time	180.12 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 07:27:23 PM PDT 24
Peak memory	265536 kb
Host	smart-12b28cb2-8d7a-4520-ad27-12a9683c702a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505911073 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.flash_ctrl_wo.505911073
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.376565825
Short name	T947
Test name
Test status
Simulation time	141554700 ps
CPU time	15.1 seconds
Started	Jul 10 07:24:08 PM PDT 24
Finished	Jul 10 07:24:27 PM PDT 24
Peak memory	258884 kb
Host	smart-e1e9bab0-7c05-4f17-956b-ed4e947be6a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=376565825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swee p.376565825
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.3562071235
Short name	T11
Test name
Test status
Simulation time	39525600 ps
CPU time	13.81 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:24:45 PM PDT 24
Peak memory	261584 kb
Host	smart-685836e4-0cfa-4395-a251-f6f0fbc5c5fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562071235 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3562071235
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.917125462
Short name	T853
Test name
Test status
Simulation time	70093000 ps
CPU time	13.62 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:24:50 PM PDT 24
Peak memory	258460 kb
Host	smart-fb62d935-54ee-4cae-9c88-9d396a41ddd2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917125462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.917125462
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.1434466459
Short name	T333
Test name
Test status
Simulation time	76519000 ps
CPU time	14.03 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:24:54 PM PDT 24
Peak memory	265092 kb
Host	smart-171a289c-e902-4893-bc68-90b6699b0977
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434466459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.1434466459
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.1529833944
Short name	T1001
Test name
Test status
Simulation time	13860400 ps
CPU time	14.09 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:24:50 PM PDT 24
Peak memory	274692 kb
Host	smart-4f0cc094-59e8-4d26-9273-40e8dea7a6f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529833944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1529833944
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.4151867936
Short name	T175
Test name
Test status
Simulation time	10792364400 ps
CPU time	500.65 seconds
Started	Jul 10 07:24:15 PM PDT 24
Finished	Jul 10 07:32:41 PM PDT 24
Peak memory	263500 kb
Host	smart-f0988b81-d30e-431a-ade0-292109c79df4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4151867936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.4151867936
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.159753675
Short name	T121
Test name
Test status
Simulation time	10380271700 ps
CPU time	2482.53 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 08:05:53 PM PDT 24
Peak memory	265160 kb
Host	smart-8f6b39ca-7471-4a76-a788-d3a11a65a95e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=159753675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.159753675
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.2958321125
Short name	T791
Test name
Test status
Simulation time	2535678000 ps
CPU time	1994.44 seconds
Started	Jul 10 07:24:26 PM PDT 24
Finished	Jul 10 07:57:47 PM PDT 24
Peak memory	264516 kb
Host	smart-6aa649ec-0e7d-462c-94e2-c0c600564e8c
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958321125 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2958321125
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.450930995
Short name	T1105
Test name
Test status
Simulation time	1888279500 ps
CPU time	804.71 seconds
Started	Jul 10 07:24:26 PM PDT 24
Finished	Jul 10 07:37:52 PM PDT 24
Peak memory	273452 kb
Host	smart-1b7da39e-bc0a-473b-8969-d525a1e8b3fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450930995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.450930995
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.2707079593
Short name	T54
Test name
Test status
Simulation time	1334303000 ps
CPU time	26.51 seconds
Started	Jul 10 07:24:24 PM PDT 24
Finished	Jul 10 07:24:52 PM PDT 24
Peak memory	262624 kb
Host	smart-19e03251-657c-496a-9881-b76f4cdc83ae
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707079593 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2707079593
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.2878771326
Short name	T861
Test name
Test status
Simulation time	387318279400 ps
CPU time	2600.74 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 08:07:49 PM PDT 24
Peak memory	273404 kb
Host	smart-0eedd87f-b048-462a-a78f-9ffb4631a3a8
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878771326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.2878771326
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.1572501349
Short name	T694
Test name
Test status
Simulation time	63391700 ps
CPU time	29.92 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:25:19 PM PDT 24
Peak memory	268488 kb
Host	smart-f40ab74b-0ba5-4b48-8d79-3e33a648ea2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572501349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.1572501349
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4177158970
Short name	T844
Test name
Test status
Simulation time	472338542800 ps
CPU time	2192.09 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 08:00:55 PM PDT 24
Peak memory	264232 kb
Host	smart-c8d4ab16-4ef3-431e-8355-d7394492fec4
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177158970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.4177158970
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.3168556316
Short name	T463
Test name
Test status
Simulation time	203844000 ps
CPU time	101.65 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:26:05 PM PDT 24
Peak memory	265272 kb
Host	smart-774fcb2d-1956-4bcd-bf33-629edaf74b17
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3168556316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3168556316
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.959252277
Short name	T576
Test name
Test status
Simulation time	10092369600 ps
CPU time	42.72 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:25:38 PM PDT 24
Peak memory	266652 kb
Host	smart-084d53c0-399e-47fa-aa88-ddc83806b58a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959252277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.959252277
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.3152723134
Short name	T113
Test name
Test status
Simulation time	175710442600 ps
CPU time	1860.95 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:55:23 PM PDT 24
Peak memory	259956 kb
Host	smart-c920a86b-b71f-4865-b1be-984e83083e74
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152723134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.3152723134
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1210529839
Short name	T877
Test name
Test status
Simulation time	40129201700 ps
CPU time	842.85 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:38:30 PM PDT 24
Peak memory	263796 kb
Host	smart-a1b4fa46-fc8c-4a7e-9718-03b0bdd8ff77
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210529839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.1210529839
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.696972794
Short name	T47
Test name
Test status
Simulation time	1220379700 ps
CPU time	92.67 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:26:00 PM PDT 24
Peak memory	262848 kb
Host	smart-c02b80fd-20b9-4b53-80dc-4b193c1e28a0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696972794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw _sec_otp.696972794
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.1191178913
Short name	T229
Test name
Test status
Simulation time	7972389400 ps
CPU time	578.45 seconds
Started	Jul 10 07:24:20 PM PDT 24
Finished	Jul 10 07:34:02 PM PDT 24
Peak memory	325380 kb
Host	smart-83b5ce1f-1eef-4d38-a93f-3bf5af85b006
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191178913 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_integrity.1191178913
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.64125969
Short name	T749
Test name
Test status
Simulation time	1868248500 ps
CPU time	200.83 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:27:47 PM PDT 24
Peak memory	290812 kb
Host	smart-36b3ea66-cfc5-4529-8c48-624d2eb02025
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64125969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ ctrl_intr_rd.64125969
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2977847653
Short name	T966
Test name
Test status
Simulation time	21707208200 ps
CPU time	287.49 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:29:25 PM PDT 24
Peak memory	291036 kb
Host	smart-b88bf274-f83b-40a2-a98d-d75212bec451
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977847653 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2977847653
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.2020168200
Short name	T1074
Test name
Test status
Simulation time	8265637200 ps
CPU time	62.83 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:25:27 PM PDT 24
Peak memory	265316 kb
Host	smart-c14e3278-4909-46fb-b3bc-932e57d9a14c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020168200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.flash_ctrl_intr_wr.2020168200
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3857237396
Short name	T27
Test name
Test status
Simulation time	96151394400 ps
CPU time	195.17 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:27:46 PM PDT 24
Peak memory	259924 kb
Host	smart-f527e7fb-deec-4a99-8bb9-464fbbebf0b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385 7237396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3857237396
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3030101035
Short name	T514
Test name
Test status
Simulation time	47687100 ps
CPU time	13.32 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 07:24:49 PM PDT 24
Peak memory	259968 kb
Host	smart-78266794-d7b8-44f3-a7a9-b2a7f5e3b4d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030101035 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3030101035
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.747685295
Short name	T180
Test name
Test status
Simulation time	3956032500 ps
CPU time	72.48 seconds
Started	Jul 10 07:24:22 PM PDT 24
Finished	Jul 10 07:25:37 PM PDT 24
Peak memory	260592 kb
Host	smart-04fc7b02-581a-4130-b7be-a5115cff3a27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747685295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.747685295
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.3593703946
Short name	T539
Test name
Test status
Simulation time	38366100 ps
CPU time	110.97 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 07:26:20 PM PDT 24
Peak memory	260048 kb
Host	smart-0a4b318e-fad9-4a53-8cf2-0c0e2ae13219
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593703946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.3593703946
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.249190959
Short name	T555
Test name
Test status
Simulation time	17170490600 ps
CPU time	242.14 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:28:29 PM PDT 24
Peak memory	281808 kb
Host	smart-01814814-6874-4ac4-b6d9-9fb8f74cbbd6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249190959 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.249190959
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1724364357
Short name	T203
Test name
Test status
Simulation time	43836300 ps
CPU time	13.59 seconds
Started	Jul 10 07:24:31 PM PDT 24
Finished	Jul 10 07:24:46 PM PDT 24
Peak memory	261584 kb
Host	smart-dadef01f-f97a-4b41-968f-652063b405d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1724364357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1724364357
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.4153357912
Short name	T828
Test name
Test status
Simulation time	2892190500 ps
CPU time	384.57 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:30:47 PM PDT 24
Peak memory	263440 kb
Host	smart-bb641b8e-8b84-4188-8f13-b0f5f357eb86
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4153357912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.4153357912
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.631772317
Short name	T176
Test name
Test status
Simulation time	27030800 ps
CPU time	14.07 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:24:51 PM PDT 24
Peak memory	262596 kb
Host	smart-7b04e8ae-5654-4445-89a2-543f58248dbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631772317 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.631772317
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.2402238464
Short name	T1104
Test name
Test status
Simulation time	2635106000 ps
CPU time	217.52 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:28:09 PM PDT 24
Peak memory	265276 kb
Host	smart-27d88a04-6ae4-4740-8db0-940b76381007
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402238464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.2402238464
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3532958449
Short name	T685
Test name
Test status
Simulation time	757584000 ps
CPU time	120.25 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:26:24 PM PDT 24
Peak memory	262720 kb
Host	smart-5db6a6c3-f966-475d-b559-d9d71c6214d8
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3532958449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3532958449
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.897944209
Short name	T708
Test name
Test status
Simulation time	65784300 ps
CPU time	31.42 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:25:08 PM PDT 24
Peak memory	280432 kb
Host	smart-d6726aa1-e452-4c22-a180-5d51b041fb29
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897944209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.flash_ctrl_rd_intg.897944209
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.465093065
Short name	T411
Test name
Test status
Simulation time	127234200 ps
CPU time	34.98 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:25:25 PM PDT 24
Peak memory	268496 kb
Host	smart-496f8b20-127f-4196-8580-d7167b9d3b58
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465093065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_re_evict.465093065
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.4289914015
Short name	T611
Test name
Test status
Simulation time	63776200 ps
CPU time	22.7 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:24:50 PM PDT 24
Peak memory	265060 kb
Host	smart-c5f6369d-8796-41bd-b834-422e0f132c20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289914015 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.4289914015
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1730012193
Short name	T631
Test name
Test status
Simulation time	26473500 ps
CPU time	22.78 seconds
Started	Jul 10 07:24:22 PM PDT 24
Finished	Jul 10 07:24:47 PM PDT 24
Peak memory	265412 kb
Host	smart-a964b8ce-a56e-4482-ab3d-f6f958abdb34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730012193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.1730012193
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.2883715262
Short name	T165
Test name
Test status
Simulation time	167241235900 ps
CPU time	907.56 seconds
Started	Jul 10 07:24:30 PM PDT 24
Finished	Jul 10 07:39:40 PM PDT 24
Peak memory	261264 kb
Host	smart-c8bfd0b3-a7ad-46e9-8140-37dff6ead933
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883715262 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2883715262
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.2687859219
Short name	T201
Test name
Test status
Simulation time	2367898600 ps
CPU time	127.64 seconds
Started	Jul 10 07:24:11 PM PDT 24
Finished	Jul 10 07:26:24 PM PDT 24
Peak memory	281764 kb
Host	smart-56806c3d-a9b4-42dc-b2d3-3efb0eb4534c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687859219 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_ro.2687859219
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.483714473
Short name	T8
Test name
Test status
Simulation time	4224465300 ps
CPU time	601.2 seconds
Started	Jul 10 07:24:18 PM PDT 24
Finished	Jul 10 07:34:24 PM PDT 24
Peak memory	312456 kb
Host	smart-8b8f46c8-c579-4969-8e19-3c4dab066e70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483714473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.483714473
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.557688218
Short name	T227
Test name
Test status
Simulation time	38224328400 ps
CPU time	753.01 seconds
Started	Jul 10 07:24:19 PM PDT 24
Finished	Jul 10 07:37:00 PM PDT 24
Peak memory	339808 kb
Host	smart-acab1852-2330-4f36-9500-f5d80c2ae123
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557688218 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_rw_derr.557688218
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict.1676805849
Short name	T385
Test name
Test status
Simulation time	35795100 ps
CPU time	31.84 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:25:03 PM PDT 24
Peak memory	268508 kb
Host	smart-ec0f8ec8-a018-4e3d-9adc-a0187fd2c84b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676805849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_rw_evict.1676805849
Directory	/workspace/1.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1027269715
Short name	T478
Test name
Test status
Simulation time	259788400 ps
CPU time	31.27 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:25:03 PM PDT 24
Peak memory	275676 kb
Host	smart-4e91ec15-93a3-453c-85b2-f895816578cb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027269715 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1027269715
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.4254893348
Short name	T610
Test name
Test status
Simulation time	4080474400 ps
CPU time	640.04 seconds
Started	Jul 10 07:24:25 PM PDT 24
Finished	Jul 10 07:35:07 PM PDT 24
Peak memory	312692 kb
Host	smart-f066d784-5488-4dee-8b34-a97e40a19ac8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254893348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s err.4254893348
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.1594353763
Short name	T505
Test name
Test status
Simulation time	521982600 ps
CPU time	64.76 seconds
Started	Jul 10 07:24:22 PM PDT 24
Finished	Jul 10 07:25:34 PM PDT 24
Peak memory	265412 kb
Host	smart-429bbfdb-cf02-4c8e-89de-763d2ed37803
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594353763 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.1594353763
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.813248455
Short name	T1086
Test name
Test status
Simulation time	1635414100 ps
CPU time	85.78 seconds
Started	Jul 10 07:24:21 PM PDT 24
Finished	Jul 10 07:25:49 PM PDT 24
Peak memory	274040 kb
Host	smart-5b39bc3f-560a-49c0-b7d7-6bb3f0d99e23
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813248455 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_counter.813248455
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.760397654
Short name	T649
Test name
Test status
Simulation time	83500500 ps
CPU time	145.48 seconds
Started	Jul 10 07:24:22 PM PDT 24
Finished	Jul 10 07:26:50 PM PDT 24
Peak memory	276808 kb
Host	smart-27235c43-761a-4a79-990b-1af5b34b54c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760397654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.760397654
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.2938498237
Short name	T568
Test name
Test status
Simulation time	14637400 ps
CPU time	23.7 seconds
Started	Jul 10 07:24:16 PM PDT 24
Finished	Jul 10 07:24:45 PM PDT 24
Peak memory	259640 kb
Host	smart-e512bdc8-e4fd-4b63-8759-2f0bb140fe82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938498237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2938498237
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.2148410374
Short name	T210
Test name
Test status
Simulation time	3955954700 ps
CPU time	1440.75 seconds
Started	Jul 10 07:24:43 PM PDT 24
Finished	Jul 10 07:48:45 PM PDT 24
Peak memory	289044 kb
Host	smart-e2cb5c37-098e-4421-9ec3-1ae0b670e0e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148410374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.2148410374
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.572443072
Short name	T652
Test name
Test status
Simulation time	42600300 ps
CPU time	26.31 seconds
Started	Jul 10 07:24:23 PM PDT 24
Finished	Jul 10 07:24:51 PM PDT 24
Peak memory	262208 kb
Host	smart-4fb19b48-bda9-49f4-83f9-ff5d1211807c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572443072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.572443072
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.4269501637
Short name	T1106
Test name
Test status
Simulation time	15225645900 ps
CPU time	227.85 seconds
Started	Jul 10 07:24:27 PM PDT 24
Finished	Jul 10 07:28:17 PM PDT 24
Peak memory	265024 kb
Host	smart-e1e47f3a-17a6-4820-ace3-ee6c69d4120f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269501637 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_wo.4269501637
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.493142590
Short name	T235
Test name
Test status
Simulation time	47919200 ps
CPU time	14.78 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 07:24:50 PM PDT 24
Peak memory	260568 kb
Host	smart-f8abc84f-a718-4a56-a80c-f856654edc07
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493142590 -assert nopostproc +UVM _TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.493142590
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.2411550621
Short name	T491
Test name
Test status
Simulation time	185097000 ps
CPU time	14.33 seconds
Started	Jul 10 07:26:01 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	258316 kb
Host	smart-3ac9c14f-beda-4174-ac2a-09c15aa86a71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411550621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test. 2411550621
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.4084153793
Short name	T995
Test name
Test status
Simulation time	55311400 ps
CPU time	13.35 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	274760 kb
Host	smart-da4d34bf-faa5-4d7a-8674-a6862fafeb4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084153793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.4084153793
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1499928181
Short name	T675
Test name
Test status
Simulation time	10037127200 ps
CPU time	50.71 seconds
Started	Jul 10 07:26:01 PM PDT 24
Finished	Jul 10 07:26:52 PM PDT 24
Peak memory	270884 kb
Host	smart-4e7952c7-b348-4ba8-ace4-d129598a813e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499928181 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1499928181
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2654278478
Short name	T179
Test name
Test status
Simulation time	17699200 ps
CPU time	13.48 seconds
Started	Jul 10 07:26:07 PM PDT 24
Finished	Jul 10 07:26:21 PM PDT 24
Peak memory	264944 kb
Host	smart-1c52cbc0-2c94-44ff-b1e6-d9d5af0cbe4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654278478 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2654278478
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.4256971395
Short name	T803
Test name
Test status
Simulation time	5868032600 ps
CPU time	121.16 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:28:06 PM PDT 24
Peak memory	260892 kb
Host	smart-7f1cb745-3dc0-4800-b30d-ba868ee25829
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256971395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ hw_sec_otp.4256971395
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.149531903
Short name	T519
Test name
Test status
Simulation time	1370530700 ps
CPU time	169.84 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:28:55 PM PDT 24
Peak memory	291616 kb
Host	smart-fe85b503-afc6-45e3-b412-1e5e6d7acc26
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149531903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas h_ctrl_intr_rd.149531903
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1107420646
Short name	T879
Test name
Test status
Simulation time	11703500400 ps
CPU time	135.76 seconds
Started	Jul 10 07:26:05 PM PDT 24
Finished	Jul 10 07:28:22 PM PDT 24
Peak memory	293100 kb
Host	smart-7f55bebe-5dee-4b18-bdc3-3ba254b157a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107420646 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1107420646
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.108631060
Short name	T470
Test name
Test status
Simulation time	1967838500 ps
CPU time	87.02 seconds
Started	Jul 10 07:26:05 PM PDT 24
Finished	Jul 10 07:27:33 PM PDT 24
Peak memory	260780 kb
Host	smart-c5a7c056-cabd-47a8-a65e-497b047198f6
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108631060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.108631060
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1011740645
Short name	T832
Test name
Test status
Simulation time	25879000 ps
CPU time	13.32 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:18 PM PDT 24
Peak memory	265016 kb
Host	smart-e435f877-61e9-41db-82da-d4feac65d272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011740645 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1011740645
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.3475875013
Short name	T660
Test name
Test status
Simulation time	51933646200 ps
CPU time	349.73 seconds
Started	Jul 10 07:26:00 PM PDT 24
Finished	Jul 10 07:31:51 PM PDT 24
Peak memory	274528 kb
Host	smart-8620cac4-e2db-4de9-8ebc-686061c24d86
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475875013 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.3475875013
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.2468133451
Short name	T885
Test name
Test status
Simulation time	40929500 ps
CPU time	112.18 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:27:56 PM PDT 24
Peak memory	260156 kb
Host	smart-85bf8e82-41de-4ef8-a2aa-c48e0c3e6e81
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468133451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o tp_reset.2468133451
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3707621744
Short name	T204
Test name
Test status
Simulation time	297005100 ps
CPU time	405.48 seconds
Started	Jul 10 07:26:01 PM PDT 24
Finished	Jul 10 07:32:47 PM PDT 24
Peak memory	263080 kb
Host	smart-3b18efb1-0296-47e3-9692-cd5dbe2cb8b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3707621744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3707621744
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.684202017
Short name	T992
Test name
Test status
Simulation time	66455900 ps
CPU time	16.57 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:21 PM PDT 24
Peak memory	265168 kb
Host	smart-da124c5d-6b38-4a8d-b9cb-efb1f00d69bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684202017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.flash_ctrl_prog_reset.684202017
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.3160743340
Short name	T634
Test name
Test status
Simulation time	284884900 ps
CPU time	882.81 seconds
Started	Jul 10 07:26:00 PM PDT 24
Finished	Jul 10 07:40:44 PM PDT 24
Peak memory	284688 kb
Host	smart-da7025be-7f73-4d86-a09a-fd418260b2b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160743340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3160743340
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.3414541216
Short name	T703
Test name
Test status
Simulation time	59820200 ps
CPU time	34.91 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:39 PM PDT 24
Peak memory	275760 kb
Host	smart-99036a45-72d2-4583-a2cc-3ef681a87456
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414541216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.3414541216
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.419730540
Short name	T496
Test name
Test status
Simulation time	922989700 ps
CPU time	94.84 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:27:38 PM PDT 24
Peak memory	291400 kb
Host	smart-4e772e38-de3a-4987-bf4f-36cb666bcd48
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419730540 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 10.flash_ctrl_ro.419730540
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.554937931
Short name	T587
Test name
Test status
Simulation time	47803400 ps
CPU time	31.18 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:37 PM PDT 24
Peak memory	275676 kb
Host	smart-decb1c51-4ede-44ef-a03f-9dc91933394a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554937931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_rw_evict.554937931
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2433719748
Short name	T1029
Test name
Test status
Simulation time	61431000 ps
CPU time	31.09 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:37 PM PDT 24
Peak memory	273664 kb
Host	smart-bd39885f-e85c-41c2-99a3-ed0625947794
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433719748 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2433719748
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.419632795
Short name	T1066
Test name
Test status
Simulation time	3844539900 ps
CPU time	70.15 seconds
Started	Jul 10 07:26:01 PM PDT 24
Finished	Jul 10 07:27:12 PM PDT 24
Peak memory	264836 kb
Host	smart-d90a7c95-95d8-461a-b459-abca97f5b12e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419632795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.419632795
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.1018893760
Short name	T704
Test name
Test status
Simulation time	43839600 ps
CPU time	171.93 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:28:58 PM PDT 24
Peak memory	279588 kb
Host	smart-90908bac-b2e6-4450-8731-b24184e5a955
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1018893760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1018893760
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.347236380
Short name	T689
Test name
Test status
Simulation time	4323116400 ps
CPU time	181.79 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:29:07 PM PDT 24
Peak memory	265332 kb
Host	smart-af08f0a8-f749-446e-8209-d4802ddc17b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347236380 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.flash_ctrl_wo.347236380
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.2941670223
Short name	T404
Test name
Test status
Simulation time	81550200 ps
CPU time	13.61 seconds
Started	Jul 10 07:26:19 PM PDT 24
Finished	Jul 10 07:26:34 PM PDT 24
Peak memory	265252 kb
Host	smart-4e27de97-aa79-4646-a171-d83b1d40db79
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941670223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 2941670223
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.1741094735
Short name	T798
Test name
Test status
Simulation time	41683200 ps
CPU time	15.64 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:26:35 PM PDT 24
Peak memory	274832 kb
Host	smart-2268f35b-3336-4798-9f67-dbaeb72c8d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741094735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1741094735
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.688386661
Short name	T1020
Test name
Test status
Simulation time	10083064800 ps
CPU time	39.63 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:26:56 PM PDT 24
Peak memory	266780 kb
Host	smart-602b0c9a-2074-47af-8c35-a53d87b7f472
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688386661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.688386661
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1259139277
Short name	T745
Test name
Test status
Simulation time	44465500 ps
CPU time	13.74 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:26:33 PM PDT 24
Peak memory	258660 kb
Host	smart-3a9cfcc6-ccc2-4900-bd1b-c8ebbd3efca5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259139277 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1259139277
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1498024414
Short name	T61
Test name
Test status
Simulation time	40120983100 ps
CPU time	841.25 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:40:21 PM PDT 24
Peak memory	265044 kb
Host	smart-854b0f7a-1eb4-4692-84fa-a81445da7a83
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498024414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.1498024414
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2180761657
Short name	T856
Test name
Test status
Simulation time	1451409000 ps
CPU time	67.79 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:27:25 PM PDT 24
Peak memory	261012 kb
Host	smart-3776d4d0-1b3b-4034-8056-774500f152e9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180761657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ hw_sec_otp.2180761657
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.952831075
Short name	T32
Test name
Test status
Simulation time	1605067200 ps
CPU time	201.47 seconds
Started	Jul 10 07:26:22 PM PDT 24
Finished	Jul 10 07:29:44 PM PDT 24
Peak memory	291348 kb
Host	smart-7164d420-8525-4f9a-9b11-fa97b80effc0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952831075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas h_ctrl_intr_rd.952831075
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.739233974
Short name	T516
Test name
Test status
Simulation time	23696171800 ps
CPU time	143.53 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:28:40 PM PDT 24
Peak memory	291084 kb
Host	smart-1061e7f5-3393-479e-86fd-4dd9505abdae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739233974 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.739233974
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.1237066955
Short name	T376
Test name
Test status
Simulation time	1701358900 ps
CPU time	69.74 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:27:25 PM PDT 24
Peak memory	263704 kb
Host	smart-e4c177d0-23e3-4d39-a9ba-57e320cdcc6d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237066955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1 237066955
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1212787250
Short name	T277
Test name
Test status
Simulation time	51771900 ps
CPU time	13.56 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:26:30 PM PDT 24
Peak memory	259932 kb
Host	smart-d338c48f-7daf-4f92-b8d2-ba85647517be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212787250 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1212787250
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.1397539129
Short name	T71
Test name
Test status
Simulation time	19038665400 ps
CPU time	266.4 seconds
Started	Jul 10 07:26:17 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	274740 kb
Host	smart-2fa4980e-9c4d-41ae-b4ff-6ee3059fe751
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397539129 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.1397539129
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.3895122404
Short name	T214
Test name
Test status
Simulation time	717874500 ps
CPU time	214.63 seconds
Started	Jul 10 07:26:05 PM PDT 24
Finished	Jul 10 07:29:41 PM PDT 24
Peak memory	263240 kb
Host	smart-9c1b9010-ca9c-4d36-a5a2-6276ceee2df3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3895122404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3895122404
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.4261409574
Short name	T813
Test name
Test status
Simulation time	8263536100 ps
CPU time	150.42 seconds
Started	Jul 10 07:26:17 PM PDT 24
Finished	Jul 10 07:28:49 PM PDT 24
Peak memory	260580 kb
Host	smart-1260db1e-90dd-4a56-b57e-ce8eab72f65b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261409574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.4261409574
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.521622701
Short name	T824
Test name
Test status
Simulation time	278667400 ps
CPU time	426.12 seconds
Started	Jul 10 07:26:05 PM PDT 24
Finished	Jul 10 07:33:12 PM PDT 24
Peak memory	281700 kb
Host	smart-54601412-5ea2-4175-905e-eca5f5137e51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521622701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.521622701
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.1801488837
Short name	T387
Test name
Test status
Simulation time	151282600 ps
CPU time	34.89 seconds
Started	Jul 10 07:26:16 PM PDT 24
Finished	Jul 10 07:26:52 PM PDT 24
Peak memory	268480 kb
Host	smart-336bce54-10b5-41e9-a44e-2530d350627a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801488837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.1801488837
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.3604310663
Short name	T92
Test name
Test status
Simulation time	1204278200 ps
CPU time	122.86 seconds
Started	Jul 10 07:26:21 PM PDT 24
Finished	Jul 10 07:28:25 PM PDT 24
Peak memory	291472 kb
Host	smart-840a80eb-1463-49fc-9e34-ff6a9d15dd83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604310663 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.3604310663
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.4274874007
Short name	T582
Test name
Test status
Simulation time	8615426100 ps
CPU time	673.5 seconds
Started	Jul 10 07:26:16 PM PDT 24
Finished	Jul 10 07:37:31 PM PDT 24
Peak memory	309644 kb
Host	smart-8e23839a-d5cc-4d9f-ae8b-1ef49d2b8882
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274874007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.4274874007
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.394929933
Short name	T134
Test name
Test status
Simulation time	80846500 ps
CPU time	31.06 seconds
Started	Jul 10 07:26:22 PM PDT 24
Finished	Jul 10 07:26:54 PM PDT 24
Peak memory	275644 kb
Host	smart-eb8afeee-8e67-430b-a4d1-7a71bbb4ea2f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394929933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_rw_evict.394929933
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.757770601
Short name	T802
Test name
Test status
Simulation time	63419800 ps
CPU time	31.04 seconds
Started	Jul 10 07:26:20 PM PDT 24
Finished	Jul 10 07:26:52 PM PDT 24
Peak memory	273624 kb
Host	smart-0b6101a6-980f-4910-8b9b-ed15eddadbb1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757770601 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.757770601
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.2964683465
Short name	T497
Test name
Test status
Simulation time	104920700 ps
CPU time	121.79 seconds
Started	Jul 10 07:26:03 PM PDT 24
Finished	Jul 10 07:28:06 PM PDT 24
Peak memory	276236 kb
Host	smart-e1c47843-eac8-4ee7-b7b5-527e0717ddc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964683465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2964683465
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.2371399587
Short name	T346
Test name
Test status
Simulation time	11953890300 ps
CPU time	248.62 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	265208 kb
Host	smart-22a44074-9db6-4ea4-ae7a-13c9921cced2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371399587 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.flash_ctrl_wo.2371399587
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.2481485150
Short name	T852
Test name
Test status
Simulation time	61674300 ps
CPU time	13.53 seconds
Started	Jul 10 07:26:26 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	265216 kb
Host	smart-461f64d0-9d5e-42fa-9089-d878e988c881
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481485150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 2481485150
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.1576834968
Short name	T1085
Test name
Test status
Simulation time	60118200 ps
CPU time	15.92 seconds
Started	Jul 10 07:26:12 PM PDT 24
Finished	Jul 10 07:26:29 PM PDT 24
Peak memory	274844 kb
Host	smart-9a30d0ff-0916-4701-83e6-0fa845fbd3ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576834968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1576834968
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.2413263925
Short name	T1009
Test name
Test status
Simulation time	28477100 ps
CPU time	20.64 seconds
Started	Jul 10 07:26:22 PM PDT 24
Finished	Jul 10 07:26:43 PM PDT 24
Peak memory	273776 kb
Host	smart-90bf1e48-cc82-4f87-8d97-d89e5ad23efa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413263925 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.2413263925
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3567696256
Short name	T545
Test name
Test status
Simulation time	10011888200 ps
CPU time	128.38 seconds
Started	Jul 10 07:26:28 PM PDT 24
Finished	Jul 10 07:28:37 PM PDT 24
Peak memory	359520 kb
Host	smart-42638890-c32f-4739-ac48-797bc48ecaa3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567696256 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3567696256
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.3854554278
Short name	T1033
Test name
Test status
Simulation time	213194000 ps
CPU time	13.24 seconds
Started	Jul 10 07:26:25 PM PDT 24
Finished	Jul 10 07:26:39 PM PDT 24
Peak memory	260400 kb
Host	smart-66c4189f-d4d8-4a41-bcaf-8f90aba95218
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854554278 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.3854554278
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.131036990
Short name	T981
Test name
Test status
Simulation time	40123808600 ps
CPU time	897.93 seconds
Started	Jul 10 07:26:22 PM PDT 24
Finished	Jul 10 07:41:21 PM PDT 24
Peak memory	264372 kb
Host	smart-2413f9bf-a273-499a-9e93-bfd2cc484b51
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131036990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.flash_ctrl_hw_rma_reset.131036990
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.22535513
Short name	T997
Test name
Test status
Simulation time	7793879700 ps
CPU time	161.53 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:28:58 PM PDT 24
Peak memory	262084 kb
Host	smart-8afa807d-6b7a-419a-9da3-954a479ea52d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22535513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw _sec_otp.22535513
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.3364095203
Short name	T311
Test name
Test status
Simulation time	1447075100 ps
CPU time	199.35 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:29:34 PM PDT 24
Peak memory	291500 kb
Host	smart-179bb40d-d88d-40d0-b071-60e9ca36499f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364095203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.3364095203
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1359107616
Short name	T889
Test name
Test status
Simulation time	43658185800 ps
CPU time	346.97 seconds
Started	Jul 10 07:26:16 PM PDT 24
Finished	Jul 10 07:32:04 PM PDT 24
Peak memory	291948 kb
Host	smart-731c1f58-b4d8-4479-80fc-5ebc15052327
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359107616 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.1359107616
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.1265229134
Short name	T950
Test name
Test status
Simulation time	4020439400 ps
CPU time	86 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:27:40 PM PDT 24
Peak memory	262772 kb
Host	smart-1e719bd2-926f-479b-aa2d-3e9b1a88ef2a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265229134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1 265229134
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2170998666
Short name	T1113
Test name
Test status
Simulation time	15462200 ps
CPU time	13.3 seconds
Started	Jul 10 07:26:26 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	260060 kb
Host	smart-5e922bbc-cd2b-4d0f-a514-e94c65b4f904
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170998666 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.2170998666
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.656369082
Short name	T123
Test name
Test status
Simulation time	16375866500 ps
CPU time	207.04 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:29:47 PM PDT 24
Peak memory	273144 kb
Host	smart-1a00a950-0e40-4953-91a2-3875e876197e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656369082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.656369082
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.2539736546
Short name	T110
Test name
Test status
Simulation time	60409800 ps
CPU time	132.41 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:28:32 PM PDT 24
Peak memory	260312 kb
Host	smart-d996a072-66c8-4c05-8270-4aa072c8d68e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539736546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.2539736546
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.3776645568
Short name	T432
Test name
Test status
Simulation time	122342400 ps
CPU time	280.89 seconds
Started	Jul 10 07:26:21 PM PDT 24
Finished	Jul 10 07:31:03 PM PDT 24
Peak memory	263236 kb
Host	smart-e6c40922-b738-45b3-85d8-d9a9285dfa18
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3776645568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3776645568
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.4182648691
Short name	T259
Test name
Test status
Simulation time	20797300 ps
CPU time	14.2 seconds
Started	Jul 10 07:26:16 PM PDT 24
Finished	Jul 10 07:26:31 PM PDT 24
Peak memory	265356 kb
Host	smart-d51cd499-7c13-493b-b713-5e90dae4ac06
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182648691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.4182648691
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.848591481
Short name	T560
Test name
Test status
Simulation time	102214800 ps
CPU time	177.31 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:29:12 PM PDT 24
Peak memory	281536 kb
Host	smart-d37ecf13-7a5b-4c48-9630-c9790e6d9031
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848591481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.848591481
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.3903608729
Short name	T391
Test name
Test status
Simulation time	271917700 ps
CPU time	32.89 seconds
Started	Jul 10 07:26:17 PM PDT 24
Finished	Jul 10 07:26:51 PM PDT 24
Peak memory	275684 kb
Host	smart-00e0b9d9-1970-46c2-a11d-96e315b1b8f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903608729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.3903608729
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.3104822850
Short name	T1103
Test name
Test status
Simulation time	1343863100 ps
CPU time	114.04 seconds
Started	Jul 10 07:26:14 PM PDT 24
Finished	Jul 10 07:28:09 PM PDT 24
Peak memory	281772 kb
Host	smart-af2872cd-a687-4221-9a0d-572534f6d35e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104822850 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.3104822850
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.4031081584
Short name	T393
Test name
Test status
Simulation time	8850074900 ps
CPU time	638.53 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:36:55 PM PDT 24
Peak memory	318620 kb
Host	smart-a99d3956-b02d-4bef-9a95-c35e11b2afa0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031081584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.flash_ctrl_rw.4031081584
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.1340999987
Short name	T386
Test name
Test status
Simulation time	43300100 ps
CPU time	31.79 seconds
Started	Jul 10 07:26:13 PM PDT 24
Finished	Jul 10 07:26:46 PM PDT 24
Peak memory	275672 kb
Host	smart-3a51f866-4285-4b2f-a19d-5af249738ef2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340999987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.1340999987
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1327974435
Short name	T345
Test name
Test status
Simulation time	29986800 ps
CPU time	31.02 seconds
Started	Jul 10 07:26:17 PM PDT 24
Finished	Jul 10 07:26:50 PM PDT 24
Peak memory	268540 kb
Host	smart-707d60e6-500f-49e4-a4bb-2f7dd977ea5e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327974435 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1327974435
Directory	/workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.442084831
Short name	T1058
Test name
Test status
Simulation time	10697912300 ps
CPU time	80.41 seconds
Started	Jul 10 07:26:18 PM PDT 24
Finished	Jul 10 07:27:41 PM PDT 24
Peak memory	263840 kb
Host	smart-d7ac725c-c117-4250-a74e-289d4d3f39e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442084831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.442084831
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.1537439005
Short name	T508
Test name
Test status
Simulation time	43278200 ps
CPU time	73.58 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:27:30 PM PDT 24
Peak memory	275596 kb
Host	smart-6d6f16d6-c53d-4f8d-94b4-f35223da2368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1537439005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1537439005
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.2893841777
Short name	T1071
Test name
Test status
Simulation time	2415687300 ps
CPU time	205.99 seconds
Started	Jul 10 07:26:15 PM PDT 24
Finished	Jul 10 07:29:43 PM PDT 24
Peak memory	265272 kb
Host	smart-b253b056-b108-42ae-bb98-4606151540be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893841777 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.flash_ctrl_wo.2893841777
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.3217307345
Short name	T510
Test name
Test status
Simulation time	147669300 ps
CPU time	13.32 seconds
Started	Jul 10 07:26:38 PM PDT 24
Finished	Jul 10 07:26:52 PM PDT 24
Peak memory	258404 kb
Host	smart-b9ecef48-05e3-4ca6-b6db-ef3cb205c2a5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217307345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 3217307345
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.2601940060
Short name	T506
Test name
Test status
Simulation time	50294900 ps
CPU time	13.37 seconds
Started	Jul 10 07:26:37 PM PDT 24
Finished	Jul 10 07:26:51 PM PDT 24
Peak memory	274792 kb
Host	smart-463dade0-353a-49cc-8812-740bf6757b1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601940060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2601940060
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2184020592
Short name	T905
Test name
Test status
Simulation time	10114392600 ps
CPU time	35.05 seconds
Started	Jul 10 07:26:38 PM PDT 24
Finished	Jul 10 07:27:14 PM PDT 24
Peak memory	264640 kb
Host	smart-68005cfa-ce49-4e90-b6b6-06cb45da8232
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184020592 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2184020592
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.280474661
Short name	T829
Test name
Test status
Simulation time	131575000 ps
CPU time	13.29 seconds
Started	Jul 10 07:26:41 PM PDT 24
Finished	Jul 10 07:26:55 PM PDT 24
Peak memory	265036 kb
Host	smart-5054792d-0894-48de-880b-24be0b4d98b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280474661 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.280474661
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2100650449
Short name	T650
Test name
Test status
Simulation time	160180819800 ps
CPU time	883.01 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:41:11 PM PDT 24
Peak memory	264992 kb
Host	smart-0d79d8aa-5cfc-48f1-89cd-dd0be57547fd
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100650449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.2100650449
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2403950546
Short name	T1030
Test name
Test status
Simulation time	6910631200 ps
CPU time	125.41 seconds
Started	Jul 10 07:26:25 PM PDT 24
Finished	Jul 10 07:28:31 PM PDT 24
Peak memory	261040 kb
Host	smart-6c0056df-b005-48d9-a185-bf0058d1e50a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403950546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.2403950546
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.3663988765
Short name	T1067
Test name
Test status
Simulation time	7101199200 ps
CPU time	232.24 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:30:20 PM PDT 24
Peak memory	291568 kb
Host	smart-52b68c7d-9936-4424-aed1-889e3eed64d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663988765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.3663988765
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4249677486
Short name	T934
Test name
Test status
Simulation time	12677379200 ps
CPU time	290.26 seconds
Started	Jul 10 07:26:26 PM PDT 24
Finished	Jul 10 07:31:17 PM PDT 24
Peak memory	292036 kb
Host	smart-4eebbc95-e763-4689-b39b-e0b5be4ab5f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249677486 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.4249677486
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.3585504179
Short name	T577
Test name
Test status
Simulation time	1983075800 ps
CPU time	79.59 seconds
Started	Jul 10 07:26:25 PM PDT 24
Finished	Jul 10 07:27:46 PM PDT 24
Peak memory	263380 kb
Host	smart-216aeb78-5033-4cb5-99ae-fddc18ef7b42
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585504179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3 585504179
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2102190331
Short name	T707
Test name
Test status
Simulation time	15417400 ps
CPU time	13.51 seconds
Started	Jul 10 07:26:42 PM PDT 24
Finished	Jul 10 07:26:57 PM PDT 24
Peak memory	260892 kb
Host	smart-b2c4e113-b87b-4f8f-96b5-0b6d8c399ebc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102190331 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2102190331
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.1845073759
Short name	T126
Test name
Test status
Simulation time	30773721100 ps
CPU time	410.11 seconds
Started	Jul 10 07:26:29 PM PDT 24
Finished	Jul 10 07:33:20 PM PDT 24
Peak memory	275180 kb
Host	smart-87f4ed5b-5d80-4ae1-9e0f-4d58dc82a45e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845073759 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.1845073759
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.4072491678
Short name	T111
Test name
Test status
Simulation time	39466200 ps
CPU time	112.84 seconds
Started	Jul 10 07:26:28 PM PDT 24
Finished	Jul 10 07:28:22 PM PDT 24
Peak memory	260152 kb
Host	smart-1922efe7-5af1-4417-8b04-684528ac617e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072491678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.4072491678
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.2736635951
Short name	T651
Test name
Test status
Simulation time	4094008500 ps
CPU time	356.44 seconds
Started	Jul 10 07:26:24 PM PDT 24
Finished	Jul 10 07:32:21 PM PDT 24
Peak memory	263172 kb
Host	smart-03c13826-0f20-4602-aa83-83968f12c134
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2736635951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2736635951
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.3658470834
Short name	T397
Test name
Test status
Simulation time	36292600 ps
CPU time	13.55 seconds
Started	Jul 10 07:26:25 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	265316 kb
Host	smart-7b760e9f-424e-4bc4-96cf-79ea1bbe77b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658470834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.3658470834
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.555920085
Short name	T558
Test name
Test status
Simulation time	13552433900 ps
CPU time	950.76 seconds
Started	Jul 10 07:26:29 PM PDT 24
Finished	Jul 10 07:42:20 PM PDT 24
Peak memory	286832 kb
Host	smart-ba29b763-bb67-43f0-8a40-0d9276ca8120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555920085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.555920085
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.565771442
Short name	T553
Test name
Test status
Simulation time	159532900 ps
CPU time	36.05 seconds
Started	Jul 10 07:26:40 PM PDT 24
Finished	Jul 10 07:27:18 PM PDT 24
Peak memory	269948 kb
Host	smart-011f0b69-0213-4bc5-b202-62502387adbd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565771442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_re_evict.565771442
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.1233791732
Short name	T200
Test name
Test status
Simulation time	2918046400 ps
CPU time	125.63 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:28:34 PM PDT 24
Peak memory	281740 kb
Host	smart-2f8b2a46-1633-494c-9380-0e30280ee01d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233791732 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.1233791732
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.3643667114
Short name	T128
Test name
Test status
Simulation time	11285054400 ps
CPU time	504.52 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:34:52 PM PDT 24
Peak memory	314440 kb
Host	smart-0cc1f9dc-1a2d-44ad-a4a4-64d34cf64a37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643667114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.flash_ctrl_rw.3643667114
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict.3675196459
Short name	T954
Test name
Test status
Simulation time	44533400 ps
CPU time	28.74 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:26:56 PM PDT 24
Peak memory	268560 kb
Host	smart-87a6cd0d-7b71-4348-81b5-d82c0d6bac81
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675196459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_rw_evict.3675196459
Directory	/workspace/13.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1015567111
Short name	T446
Test name
Test status
Simulation time	67519600 ps
CPU time	30.64 seconds
Started	Jul 10 07:26:39 PM PDT 24
Finished	Jul 10 07:27:10 PM PDT 24
Peak memory	275680 kb
Host	smart-eda09766-e69c-4e08-acb9-564e4ba27af7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015567111 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1015567111
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.2977041701
Short name	T669
Test name
Test status
Simulation time	74878500 ps
CPU time	172.8 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:29:20 PM PDT 24
Peak memory	277048 kb
Host	smart-5fcedddc-6449-4282-b43a-08d26aa16299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977041701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2977041701
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.1285665196
Short name	T535
Test name
Test status
Simulation time	12282579600 ps
CPU time	182.38 seconds
Started	Jul 10 07:26:27 PM PDT 24
Finished	Jul 10 07:29:30 PM PDT 24
Peak memory	259452 kb
Host	smart-49f37509-4ed6-4ea0-b214-44e89d9f8dcf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285665196 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.flash_ctrl_wo.1285665196
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.3541568774
Short name	T603
Test name
Test status
Simulation time	188772000 ps
CPU time	13.74 seconds
Started	Jul 10 07:26:49 PM PDT 24
Finished	Jul 10 07:27:04 PM PDT 24
Peak memory	258284 kb
Host	smart-e5341612-d396-495b-89d0-c61c68c244a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541568774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 3541568774
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.3340654723
Short name	T880
Test name
Test status
Simulation time	26975100 ps
CPU time	13.37 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:27:02 PM PDT 24
Peak memory	274900 kb
Host	smart-9fe93925-b8fa-4757-9c61-1d2af200bfa3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340654723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3340654723
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.1829389122
Short name	T469
Test name
Test status
Simulation time	30121100 ps
CPU time	21.83 seconds
Started	Jul 10 07:26:40 PM PDT 24
Finished	Jul 10 07:27:03 PM PDT 24
Peak memory	273560 kb
Host	smart-87c70256-db39-4ffd-9b86-2dc60b18847c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829389122 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.1829389122
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1114017526
Short name	T320
Test name
Test status
Simulation time	15143700 ps
CPU time	13.55 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:27:03 PM PDT 24
Peak memory	265000 kb
Host	smart-cb718bbc-b79c-4364-bc00-ee3d9fadab44
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114017526 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1114017526
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1251799352
Short name	T604
Test name
Test status
Simulation time	8647070100 ps
CPU time	227.58 seconds
Started	Jul 10 07:26:40 PM PDT 24
Finished	Jul 10 07:30:29 PM PDT 24
Peak memory	260976 kb
Host	smart-766c7584-0d54-42bb-840e-2aae853865a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251799352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.1251799352
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.2419222880
Short name	T34
Test name
Test status
Simulation time	3423012300 ps
CPU time	240.73 seconds
Started	Jul 10 07:26:43 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	291324 kb
Host	smart-21dc09f8-05db-4cdb-a548-be066392045c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419222880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla sh_ctrl_intr_rd.2419222880
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3032556390
Short name	T569
Test name
Test status
Simulation time	156062135600 ps
CPU time	442.2 seconds
Started	Jul 10 07:26:39 PM PDT 24
Finished	Jul 10 07:34:02 PM PDT 24
Peak memory	290968 kb
Host	smart-d21e91e0-7e18-456b-bad3-e330d49e8019
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032556390 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3032556390
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.2411946379
Short name	T552
Test name
Test status
Simulation time	4555191400 ps
CPU time	57.89 seconds
Started	Jul 10 07:26:40 PM PDT 24
Finished	Jul 10 07:27:39 PM PDT 24
Peak memory	263260 kb
Host	smart-6cb0dad9-790c-4786-8951-daff30bb867b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411946379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2 411946379
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1107161272
Short name	T147
Test name
Test status
Simulation time	44591800 ps
CPU time	13.55 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:27:02 PM PDT 24
Peak memory	265080 kb
Host	smart-80aecb03-7f38-44a7-8485-77d857272c9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107161272 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1107161272
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.812710573
Short name	T142
Test name
Test status
Simulation time	63596374900 ps
CPU time	404.37 seconds
Started	Jul 10 07:26:39 PM PDT 24
Finished	Jul 10 07:33:24 PM PDT 24
Peak memory	274268 kb
Host	smart-0f4e0ff1-bb15-4fcc-9575-9593241d693c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812710573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.812710573
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.3374712135
Short name	T1046
Test name
Test status
Simulation time	43738300 ps
CPU time	131.2 seconds
Started	Jul 10 07:26:38 PM PDT 24
Finished	Jul 10 07:28:50 PM PDT 24
Peak memory	260996 kb
Host	smart-f94b3c6e-d0cc-491a-b4c1-ab05e3138ca1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374712135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.3374712135
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.3005735626
Short name	T1102
Test name
Test status
Simulation time	1396822800 ps
CPU time	555.27 seconds
Started	Jul 10 07:26:38 PM PDT 24
Finished	Jul 10 07:35:55 PM PDT 24
Peak memory	263324 kb
Host	smart-a8a73465-4a94-449f-abeb-435b6620d572
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3005735626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3005735626
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.465560038
Short name	T805
Test name
Test status
Simulation time	4274134500 ps
CPU time	183.47 seconds
Started	Jul 10 07:26:42 PM PDT 24
Finished	Jul 10 07:29:46 PM PDT 24
Peak memory	259956 kb
Host	smart-38d264bf-c572-4b87-970d-86d776c59835
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465560038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.flash_ctrl_prog_reset.465560038
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.2905542360
Short name	T1013
Test name
Test status
Simulation time	2054525400 ps
CPU time	854.49 seconds
Started	Jul 10 07:26:39 PM PDT 24
Finished	Jul 10 07:40:55 PM PDT 24
Peak memory	284728 kb
Host	smart-a42908db-e8ed-444e-9cb1-d4e63cc084aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905542360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2905542360
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.2260773858
Short name	T1048
Test name
Test status
Simulation time	123193900 ps
CPU time	34.62 seconds
Started	Jul 10 07:26:38 PM PDT 24
Finished	Jul 10 07:27:13 PM PDT 24
Peak memory	268512 kb
Host	smart-935667ae-c53a-4550-983a-621ff57e226e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260773858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.2260773858
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.2820915207
Short name	T751
Test name
Test status
Simulation time	1860927900 ps
CPU time	103.86 seconds
Started	Jul 10 07:26:36 PM PDT 24
Finished	Jul 10 07:28:20 PM PDT 24
Peak memory	281232 kb
Host	smart-0294e2b0-599f-42a5-ba63-39237367d070
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820915207 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 14.flash_ctrl_ro.2820915207
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.1061467853
Short name	T737
Test name
Test status
Simulation time	13643811600 ps
CPU time	615.21 seconds
Started	Jul 10 07:26:43 PM PDT 24
Finished	Jul 10 07:36:59 PM PDT 24
Peak memory	314324 kb
Host	smart-dbcc8070-bcd2-419b-8b39-64f64e91bf2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061467853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.1061467853
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.3645400230
Short name	T986
Test name
Test status
Simulation time	121977700 ps
CPU time	31.94 seconds
Started	Jul 10 07:26:37 PM PDT 24
Finished	Jul 10 07:27:10 PM PDT 24
Peak memory	275676 kb
Host	smart-de6d85ac-f805-4d22-bc9c-e9765a16b2e4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645400230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.3645400230
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2395644468
Short name	T638
Test name
Test status
Simulation time	28292100 ps
CPU time	31.21 seconds
Started	Jul 10 07:26:37 PM PDT 24
Finished	Jul 10 07:27:09 PM PDT 24
Peak memory	275668 kb
Host	smart-7226cb52-1e25-4aef-b80d-ee6d71159af2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395644468 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2395644468
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.4077752685
Short name	T499
Test name
Test status
Simulation time	1902195600 ps
CPU time	57.36 seconds
Started	Jul 10 07:26:46 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	263704 kb
Host	smart-b6023eeb-49e8-452f-8f9c-d0c5ae76b0bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077752685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.4077752685
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.1104656471
Short name	T747
Test name
Test status
Simulation time	54767100 ps
CPU time	120.26 seconds
Started	Jul 10 07:26:37 PM PDT 24
Finished	Jul 10 07:28:39 PM PDT 24
Peak memory	276704 kb
Host	smart-ff50556c-ae4b-4c83-bec1-6c35b19d438e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104656471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1104656471
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.2843304210
Short name	T130
Test name
Test status
Simulation time	2208910200 ps
CPU time	179.24 seconds
Started	Jul 10 07:26:41 PM PDT 24
Finished	Jul 10 07:29:41 PM PDT 24
Peak memory	265152 kb
Host	smart-139f258e-14c8-4f4b-8b84-95dd85c995b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843304210 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.2843304210
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.2029101006
Short name	T374
Test name
Test status
Simulation time	51118600 ps
CPU time	14.13 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:27:13 PM PDT 24
Peak memory	265228 kb
Host	smart-67e8374d-262e-4896-89dd-0659304a91b1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029101006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 2029101006
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.2449758061
Short name	T984
Test name
Test status
Simulation time	16172800 ps
CPU time	16.44 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:27:15 PM PDT 24
Peak memory	284332 kb
Host	smart-9bc171df-4a22-4df2-b319-4cf855978363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2449758061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2449758061
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.942851380
Short name	T100
Test name
Test status
Simulation time	30185400 ps
CPU time	22.96 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:27:20 PM PDT 24
Peak memory	265616 kb
Host	smart-c684813d-60c3-4e6b-a912-df941d81dbda
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942851380 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.942851380
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2928179562
Short name	T274
Test name
Test status
Simulation time	10056604900 ps
CPU time	48.46 seconds
Started	Jul 10 07:26:55 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	265488 kb
Host	smart-ef1b0355-1444-4a66-a1ea-fca7e7a5477a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928179562 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2928179562
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3003018345
Short name	T733
Test name
Test status
Simulation time	30058800 ps
CPU time	13.49 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:27:12 PM PDT 24
Peak memory	258688 kb
Host	smart-a0dc3e9e-1916-4440-8582-d07a4a84e8ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003018345 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3003018345
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.1067077338
Short name	T269
Test name
Test status
Simulation time	3267223400 ps
CPU time	144.29 seconds
Started	Jul 10 07:26:49 PM PDT 24
Finished	Jul 10 07:29:14 PM PDT 24
Peak memory	294220 kb
Host	smart-eb6518bc-ba53-4550-86b7-b469ebd1bec7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067077338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.1067077338
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2891005564
Short name	T730
Test name
Test status
Simulation time	5750169700 ps
CPU time	136.14 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:29:06 PM PDT 24
Peak memory	293104 kb
Host	smart-713ea017-b3bb-454c-a231-32c66229956e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891005564 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2891005564
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.3460881998
Short name	T375
Test name
Test status
Simulation time	7773854900 ps
CPU time	75.87 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:28:06 PM PDT 24
Peak memory	262660 kb
Host	smart-f7248e8c-1d05-4916-b726-a3d6bdac96d9
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460881998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3 460881998
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1102769478
Short name	T635
Test name
Test status
Simulation time	31125300 ps
CPU time	13.65 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:27:12 PM PDT 24
Peak memory	260952 kb
Host	smart-8d118801-62fa-4a7c-84a6-6235719671c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102769478 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1102769478
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.1098863964
Short name	T1026
Test name
Test status
Simulation time	10084856000 ps
CPU time	254.36 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:31:03 PM PDT 24
Peak memory	274408 kb
Host	smart-55d90b48-8661-4a84-bdd8-52be30c0c52c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098863964 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1098863964
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.2054210904
Short name	T1096
Test name
Test status
Simulation time	75084800 ps
CPU time	108.17 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:28:36 PM PDT 24
Peak memory	260124 kb
Host	smart-4011b407-1ab9-4e45-85dc-43c06a80800e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054210904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o tp_reset.2054210904
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.2473317166
Short name	T913
Test name
Test status
Simulation time	30630000 ps
CPU time	69.27 seconds
Started	Jul 10 07:27:02 PM PDT 24
Finished	Jul 10 07:28:12 PM PDT 24
Peak memory	263176 kb
Host	smart-f6a4697d-1898-4cc8-be72-618237b5530f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2473317166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2473317166
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.219492317
Short name	T688
Test name
Test status
Simulation time	20533200 ps
CPU time	13.7 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:27:01 PM PDT 24
Peak memory	265128 kb
Host	smart-d129b942-4ac1-4390-9603-b75405614b8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219492317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.flash_ctrl_prog_reset.219492317
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.485326086
Short name	T136
Test name
Test status
Simulation time	863668600 ps
CPU time	822.27 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:40:31 PM PDT 24
Peak memory	287220 kb
Host	smart-536732c4-7dff-45b3-a03f-b38c35c5601e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485326086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.485326086
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.456589623
Short name	T789
Test name
Test status
Simulation time	505420600 ps
CPU time	97.95 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:28:26 PM PDT 24
Peak memory	289996 kb
Host	smart-5366a7f5-9911-4a90-98b6-5e07b043224b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456589623 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.flash_ctrl_ro.456589623
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.1164163000
Short name	T1044
Test name
Test status
Simulation time	14425812100 ps
CPU time	600.78 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:36:51 PM PDT 24
Peak memory	309864 kb
Host	smart-888f13d8-1b70-4152-82c7-7ee4f4f04648
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164163000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.1164163000
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict.178155117
Short name	T761
Test name
Test status
Simulation time	29330300 ps
CPU time	28.6 seconds
Started	Jul 10 07:26:53 PM PDT 24
Finished	Jul 10 07:27:23 PM PDT 24
Peak memory	267524 kb
Host	smart-ea0f6e2c-ae16-4504-ba58-f1e9a1d91f37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178155117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_rw_evict.178155117
Directory	/workspace/15.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.603436271
Short name	T500
Test name
Test status
Simulation time	37481800 ps
CPU time	31.22 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:27:20 PM PDT 24
Peak memory	275660 kb
Host	smart-08c41037-82d9-4f9b-9357-d858dfe7bb3b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603436271 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.603436271
Directory	/workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.3782094294
Short name	T366
Test name
Test status
Simulation time	2107339700 ps
CPU time	68.03 seconds
Started	Jul 10 07:26:56 PM PDT 24
Finished	Jul 10 07:28:05 PM PDT 24
Peak memory	263724 kb
Host	smart-74c987d4-e8ad-4be1-b045-0e9f091a1622
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782094294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3782094294
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.1487835700
Short name	T221
Test name
Test status
Simulation time	71308300 ps
CPU time	52.74 seconds
Started	Jul 10 07:26:47 PM PDT 24
Finished	Jul 10 07:27:42 PM PDT 24
Peak memory	271364 kb
Host	smart-21a5e218-c36f-4191-bb1d-616ffe3edd60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487835700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1487835700
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.2154840405
Short name	T1078
Test name
Test status
Simulation time	7403549000 ps
CPU time	168.4 seconds
Started	Jul 10 07:26:48 PM PDT 24
Finished	Jul 10 07:29:38 PM PDT 24
Peak memory	265308 kb
Host	smart-2f42fffb-2bef-4633-a36b-0a8b18f3d420
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154840405 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.2154840405
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.1787110879
Short name	T762
Test name
Test status
Simulation time	182153000 ps
CPU time	13.96 seconds
Started	Jul 10 07:27:07 PM PDT 24
Finished	Jul 10 07:27:22 PM PDT 24
Peak memory	265192 kb
Host	smart-df9d79fb-4310-4f5e-b418-b6da6de624b7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787110879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test. 1787110879
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.3048923966
Short name	T1051
Test name
Test status
Simulation time	44100400 ps
CPU time	16.5 seconds
Started	Jul 10 07:27:07 PM PDT 24
Finished	Jul 10 07:27:25 PM PDT 24
Peak memory	274964 kb
Host	smart-724793ac-1af6-4c24-a0ea-ccadea8dce63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3048923966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3048923966
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.2705817797
Short name	T946
Test name
Test status
Simulation time	10357100 ps
CPU time	20.76 seconds
Started	Jul 10 07:27:09 PM PDT 24
Finished	Jul 10 07:27:30 PM PDT 24
Peak memory	273680 kb
Host	smart-e712f4ac-c3aa-4ec5-aedd-c863188abbe1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705817797 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.2705817797
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.4013731936
Short name	T985
Test name
Test status
Simulation time	10035698400 ps
CPU time	54.65 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:28:02 PM PDT 24
Peak memory	268636 kb
Host	smart-3e51f97a-ad58-4431-836e-291c078f1eaf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013731936 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.4013731936
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.444961881
Short name	T493
Test name
Test status
Simulation time	46463400 ps
CPU time	13.83 seconds
Started	Jul 10 07:27:08 PM PDT 24
Finished	Jul 10 07:27:23 PM PDT 24
Peak memory	260316 kb
Host	smart-801e6b18-5004-488f-b652-092fd409f197
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444961881 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.444961881
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2275869495
Short name	T952
Test name
Test status
Simulation time	12144078300 ps
CPU time	143.01 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:29:22 PM PDT 24
Peak memory	263168 kb
Host	smart-cef63ad4-ce32-4e61-b808-262b44d7e2d3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275869495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.2275869495
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.2256396635
Short name	T617
Test name
Test status
Simulation time	2866897100 ps
CPU time	145.91 seconds
Started	Jul 10 07:27:16 PM PDT 24
Finished	Jul 10 07:29:42 PM PDT 24
Peak memory	293928 kb
Host	smart-ef12ffec-ef3b-4d5a-b146-defab3b0eb4b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256396635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_intr_rd.2256396635
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.3447803100
Short name	T814
Test name
Test status
Simulation time	10698321000 ps
CPU time	110.23 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:28:49 PM PDT 24
Peak memory	260644 kb
Host	smart-ce278a53-e0c0-4131-842b-4f4ac29dce0f
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447803100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3 447803100
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2833652841
Short name	T780
Test name
Test status
Simulation time	39987400 ps
CPU time	13.59 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:27:20 PM PDT 24
Peak memory	260048 kb
Host	smart-4fb0c3db-8632-415c-970a-3788d566eed8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833652841 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2833652841
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.3984616851
Short name	T162
Test name
Test status
Simulation time	79178100 ps
CPU time	133.64 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:29:12 PM PDT 24
Peak memory	259988 kb
Host	smart-08e95149-b485-4735-8dbb-770df5508dbb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984616851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.3984616851
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.3922960595
Short name	T211
Test name
Test status
Simulation time	2805216500 ps
CPU time	305.42 seconds
Started	Jul 10 07:26:56 PM PDT 24
Finished	Jul 10 07:32:02 PM PDT 24
Peak memory	263104 kb
Host	smart-fd877c02-a1f4-4854-86a3-cfc6221e28d2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3922960595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3922960595
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.3252612775
Short name	T666
Test name
Test status
Simulation time	26779500 ps
CPU time	14.12 seconds
Started	Jul 10 07:27:16 PM PDT 24
Finished	Jul 10 07:27:30 PM PDT 24
Peak memory	265268 kb
Host	smart-1c72b271-2556-41c4-a8d8-71b9f8291a85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252612775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.flash_ctrl_prog_reset.3252612775
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.3848765861
Short name	T532
Test name
Test status
Simulation time	37335400 ps
CPU time	122.84 seconds
Started	Jul 10 07:26:58 PM PDT 24
Finished	Jul 10 07:29:02 PM PDT 24
Peak memory	277876 kb
Host	smart-4da45e57-c05a-461c-a684-56b94f956a8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848765861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3848765861
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.510538157
Short name	T959
Test name
Test status
Simulation time	297638900 ps
CPU time	35.01 seconds
Started	Jul 10 07:27:08 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	273224 kb
Host	smart-454854a4-6009-449c-ad18-f5fcf75f5400
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510538157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla sh_ctrl_re_evict.510538157
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.3849702154
Short name	T419
Test name
Test status
Simulation time	576068900 ps
CPU time	107.19 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	291396 kb
Host	smart-35fa008c-7f49-4432-b98a-fe80908525c9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849702154 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.3849702154
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.2263584273
Short name	T479
Test name
Test status
Simulation time	8195076300 ps
CPU time	599.56 seconds
Started	Jul 10 07:27:08 PM PDT 24
Finished	Jul 10 07:37:09 PM PDT 24
Peak memory	309856 kb
Host	smart-693c30aa-09be-4d57-a2bc-38a3274162c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263584273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.flash_ctrl_rw.2263584273
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict.4018872848
Short name	T867
Test name
Test status
Simulation time	181347500 ps
CPU time	30.86 seconds
Started	Jul 10 07:27:07 PM PDT 24
Finished	Jul 10 07:27:38 PM PDT 24
Peak memory	275712 kb
Host	smart-24c94b17-fe9f-48c2-9974-587485a36093
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018872848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_rw_evict.4018872848
Directory	/workspace/16.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3632947902
Short name	T265
Test name
Test status
Simulation time	80775300 ps
CPU time	28.69 seconds
Started	Jul 10 07:27:10 PM PDT 24
Finished	Jul 10 07:27:40 PM PDT 24
Peak memory	275668 kb
Host	smart-129e28f7-692f-4f70-af0c-0b278336abdc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632947902 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3632947902
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.2767804458
Short name	T564
Test name
Test status
Simulation time	559826500 ps
CPU time	66.2 seconds
Started	Jul 10 07:27:09 PM PDT 24
Finished	Jul 10 07:28:16 PM PDT 24
Peak memory	264008 kb
Host	smart-43acb996-940d-43da-8a14-37c81793d88a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767804458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.2767804458
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.2604077520
Short name	T513
Test name
Test status
Simulation time	84450700 ps
CPU time	100.68 seconds
Started	Jul 10 07:26:57 PM PDT 24
Finished	Jul 10 07:28:38 PM PDT 24
Peak memory	276080 kb
Host	smart-1bfeb154-4ae5-4307-9a8d-e686a3777e2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604077520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2604077520
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.1769208241
Short name	T702
Test name
Test status
Simulation time	8132151000 ps
CPU time	133.95 seconds
Started	Jul 10 07:27:09 PM PDT 24
Finished	Jul 10 07:29:23 PM PDT 24
Peak memory	259408 kb
Host	smart-38f75648-e6fc-4e0c-bbed-1a4d27111428
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769208241 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.1769208241
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.2885887625
Short name	T409
Test name
Test status
Simulation time	115742200 ps
CPU time	13.5 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:27:32 PM PDT 24
Peak memory	258308 kb
Host	smart-5f301694-f8fb-44f6-bdf5-b479c80d7582
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885887625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 2885887625
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.4226507247
Short name	T874
Test name
Test status
Simulation time	25977500 ps
CPU time	15.71 seconds
Started	Jul 10 07:27:19 PM PDT 24
Finished	Jul 10 07:27:36 PM PDT 24
Peak memory	275004 kb
Host	smart-78e9b98c-774f-4e4a-ac77-54ae4fb2bb75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226507247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4226507247
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.1486799919
Short name	T405
Test name
Test status
Simulation time	14847200 ps
CPU time	22.15 seconds
Started	Jul 10 07:27:18 PM PDT 24
Finished	Jul 10 07:27:41 PM PDT 24
Peak memory	273684 kb
Host	smart-a8623594-e24e-4d61-90f8-1af2232d4476
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486799919 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_disable.1486799919
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1115572960
Short name	T159
Test name
Test status
Simulation time	10034451400 ps
CPU time	58.45 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:28:17 PM PDT 24
Peak memory	268556 kb
Host	smart-e1d52928-d580-457a-a011-758be344c8d1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115572960 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1115572960
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.4060406928
Short name	T46
Test name
Test status
Simulation time	81226500 ps
CPU time	13.8 seconds
Started	Jul 10 07:27:18 PM PDT 24
Finished	Jul 10 07:27:33 PM PDT 24
Peak memory	258616 kb
Host	smart-e4a0e00c-a541-4065-93ee-888356596418
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060406928 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.4060406928
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3573178105
Short name	T173
Test name
Test status
Simulation time	160193666500 ps
CPU time	999.13 seconds
Started	Jul 10 07:27:15 PM PDT 24
Finished	Jul 10 07:43:55 PM PDT 24
Peak memory	264300 kb
Host	smart-dd6d7001-89b5-4ab2-9431-36e93aefa0ed
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573178105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.flash_ctrl_hw_rma_reset.3573178105
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2773571684
Short name	T49
Test name
Test status
Simulation time	10227797800 ps
CPU time	225.27 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:30:52 PM PDT 24
Peak memory	263260 kb
Host	smart-47b46a26-b42e-459f-a00a-e127fae7413d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773571684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.2773571684
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.587012473
Short name	T1047
Test name
Test status
Simulation time	6120411600 ps
CPU time	207.88 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:30:47 PM PDT 24
Peak memory	291524 kb
Host	smart-087611e3-89e3-407c-b906-5aa3af8b521d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587012473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flas h_ctrl_intr_rd.587012473
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3493443372
Short name	T300
Test name
Test status
Simulation time	50756636700 ps
CPU time	296.78 seconds
Started	Jul 10 07:27:21 PM PDT 24
Finished	Jul 10 07:32:19 PM PDT 24
Peak memory	291000 kb
Host	smart-801fd7c8-d969-429a-9878-bf4c018005ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493443372 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3493443372
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.2580447724
Short name	T916
Test name
Test status
Simulation time	1642379900 ps
CPU time	67.96 seconds
Started	Jul 10 07:27:19 PM PDT 24
Finished	Jul 10 07:28:28 PM PDT 24
Peak memory	263468 kb
Host	smart-e1c7d21b-941d-4c4c-ad9c-c2c941d0f949
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580447724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2 580447724
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2016381226
Short name	T664
Test name
Test status
Simulation time	17543100 ps
CPU time	13.61 seconds
Started	Jul 10 07:27:20 PM PDT 24
Finished	Jul 10 07:27:34 PM PDT 24
Peak memory	260852 kb
Host	smart-0c585664-7a3f-476b-9d5e-4fd3d560a07d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016381226 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2016381226
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.1012688839
Short name	T998
Test name
Test status
Simulation time	14816054400 ps
CPU time	595.16 seconds
Started	Jul 10 07:27:18 PM PDT 24
Finished	Jul 10 07:37:14 PM PDT 24
Peak memory	274616 kb
Host	smart-852cfdcc-9122-423e-b5a1-470c3ce74782
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012688839 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.1012688839
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.2270168472
Short name	T865
Test name
Test status
Simulation time	232008500 ps
CPU time	133.34 seconds
Started	Jul 10 07:27:09 PM PDT 24
Finished	Jul 10 07:29:23 PM PDT 24
Peak memory	260160 kb
Host	smart-9bd5ac76-c72d-4239-a2b6-3d37d5049c89
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270168472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.2270168472
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.2360576792
Short name	T743
Test name
Test status
Simulation time	4215458900 ps
CPU time	465.48 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:34:53 PM PDT 24
Peak memory	263168 kb
Host	smart-164f4650-94bd-4d25-9ed8-e9b03f4c2270
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2360576792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2360576792
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.796583239
Short name	T731
Test name
Test status
Simulation time	9558389800 ps
CPU time	207.15 seconds
Started	Jul 10 07:27:16 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	260028 kb
Host	smart-9796c163-70d8-49fe-ab8f-d87ab9ac1272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796583239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 17.flash_ctrl_prog_reset.796583239
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.1332120657
Short name	T138
Test name
Test status
Simulation time	1720211400 ps
CPU time	1103.37 seconds
Started	Jul 10 07:27:06 PM PDT 24
Finished	Jul 10 07:45:30 PM PDT 24
Peak memory	285168 kb
Host	smart-29a02393-9276-42d8-ad59-269ec511908f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332120657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1332120657
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.1249265879
Short name	T382
Test name
Test status
Simulation time	118412100 ps
CPU time	31.51 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:27:50 PM PDT 24
Peak memory	275688 kb
Host	smart-1fda8733-ccbf-4e77-892e-fed012854540
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249265879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_re_evict.1249265879
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.1285213059
Short name	T22
Test name
Test status
Simulation time	2171564400 ps
CPU time	126.29 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:29:25 PM PDT 24
Peak memory	291560 kb
Host	smart-9a0613b8-ec75-4682-ab87-ed2cf22ee7be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285213059 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.1285213059
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.4271735670
Short name	T881
Test name
Test status
Simulation time	8015494800 ps
CPU time	546.04 seconds
Started	Jul 10 07:27:18 PM PDT 24
Finished	Jul 10 07:36:25 PM PDT 24
Peak memory	314432 kb
Host	smart-b1541f52-384c-47f1-a6db-45d517d78c0e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271735670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.4271735670
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict.3157040099
Short name	T1039
Test name
Test status
Simulation time	195350800 ps
CPU time	31.38 seconds
Started	Jul 10 07:27:18 PM PDT 24
Finished	Jul 10 07:27:51 PM PDT 24
Peak memory	275660 kb
Host	smart-6d665781-118f-4cc0-a1a8-3c87c097ad53
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157040099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_rw_evict.3157040099
Directory	/workspace/17.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2608307558
Short name	T395
Test name
Test status
Simulation time	33860200 ps
CPU time	29.55 seconds
Started	Jul 10 07:27:20 PM PDT 24
Finished	Jul 10 07:27:51 PM PDT 24
Peak memory	268516 kb
Host	smart-66d4f225-54a4-4ac5-8281-96fcfcbf5245
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608307558 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2608307558
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.2389429025
Short name	T614
Test name
Test status
Simulation time	19956200 ps
CPU time	120.49 seconds
Started	Jul 10 07:27:07 PM PDT 24
Finished	Jul 10 07:29:08 PM PDT 24
Peak memory	277512 kb
Host	smart-6a1bb3d8-403c-4252-a862-9c60e48d6601
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389429025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2389429025
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.1929920532
Short name	T434
Test name
Test status
Simulation time	5087654100 ps
CPU time	227.89 seconds
Started	Jul 10 07:27:20 PM PDT 24
Finished	Jul 10 07:31:09 PM PDT 24
Peak memory	260196 kb
Host	smart-ae52a938-cdef-415a-8f83-c5768b7c665b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929920532 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.1929920532
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.4137587353
Short name	T373
Test name
Test status
Simulation time	555549800 ps
CPU time	14.05 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:27:43 PM PDT 24
Peak memory	265204 kb
Host	smart-16ef7c63-06a5-42c8-9b51-4500aa417a3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137587353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 4137587353
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.3173883377
Short name	T504
Test name
Test status
Simulation time	40460700 ps
CPU time	13.19 seconds
Started	Jul 10 07:27:26 PM PDT 24
Finished	Jul 10 07:27:40 PM PDT 24
Peak memory	274968 kb
Host	smart-c4e4892b-49c2-4e1c-8ab8-4b447df50334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173883377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3173883377
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.541473872
Short name	T1005
Test name
Test status
Simulation time	10011898100 ps
CPU time	106.4 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:29:15 PM PDT 24
Peak memory	307032 kb
Host	smart-affb7a82-fbcd-4d99-97be-44a7cce1e444
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541473872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.541473872
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.2989997237
Short name	T706
Test name
Test status
Simulation time	45886600 ps
CPU time	13.33 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:27:43 PM PDT 24
Peak memory	265000 kb
Host	smart-cc45d8c4-0640-42a7-afd9-9135efc70611
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989997237 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.2989997237
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3521447082
Short name	T933
Test name
Test status
Simulation time	480307155000 ps
CPU time	1176.39 seconds
Started	Jul 10 07:27:30 PM PDT 24
Finished	Jul 10 07:47:08 PM PDT 24
Peak memory	261096 kb
Host	smart-f8aa05ac-cbc3-440d-a9e8-2d47f81332be
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521447082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.3521447082
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2579087236
Short name	T788
Test name
Test status
Simulation time	3326311000 ps
CPU time	38.11 seconds
Started	Jul 10 07:27:27 PM PDT 24
Finished	Jul 10 07:28:07 PM PDT 24
Peak memory	260836 kb
Host	smart-de88468d-4219-4520-bc05-e99c20fc5a50
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579087236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.2579087236
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3847503464
Short name	T480
Test name
Test status
Simulation time	71313147700 ps
CPU time	211.78 seconds
Started	Jul 10 07:27:26 PM PDT 24
Finished	Jul 10 07:30:59 PM PDT 24
Peak memory	293152 kb
Host	smart-60772694-30c6-49a5-90ec-5421ece5560b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847503464 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3847503464
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.892832762
Short name	T975
Test name
Test status
Simulation time	45182600 ps
CPU time	13.5 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:27:42 PM PDT 24
Peak memory	259964 kb
Host	smart-b69cad6c-eee9-4715-ac6d-2f436c25359f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892832762 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.892832762
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.3160496219
Short name	T698
Test name
Test status
Simulation time	2339073300 ps
CPU time	112.77 seconds
Started	Jul 10 07:27:28 PM PDT 24
Finished	Jul 10 07:29:22 PM PDT 24
Peak memory	265136 kb
Host	smart-23f8cb52-fe18-4b23-8815-2df246ccb6a9
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160496219 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.3160496219
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.152534100
Short name	T641
Test name
Test status
Simulation time	50904000 ps
CPU time	195.4 seconds
Started	Jul 10 07:27:16 PM PDT 24
Finished	Jul 10 07:30:33 PM PDT 24
Peak memory	263256 kb
Host	smart-192ed869-4d8b-4f6a-929a-665654206612
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=152534100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.152534100
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.122027281
Short name	T412
Test name
Test status
Simulation time	58686200 ps
CPU time	13.73 seconds
Started	Jul 10 07:27:27 PM PDT 24
Finished	Jul 10 07:27:42 PM PDT 24
Peak memory	265452 kb
Host	smart-aefa4154-1a9e-4cbd-a208-235e8d49f760
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122027281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 18.flash_ctrl_prog_reset.122027281
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.3292470698
Short name	T137
Test name
Test status
Simulation time	243991700 ps
CPU time	486 seconds
Started	Jul 10 07:27:20 PM PDT 24
Finished	Jul 10 07:35:26 PM PDT 24
Peak memory	282264 kb
Host	smart-de67299e-86d9-49a0-a0d9-4e51bef67ae4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292470698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3292470698
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.4170577213
Short name	T84
Test name
Test status
Simulation time	436783100 ps
CPU time	36.66 seconds
Started	Jul 10 07:27:26 PM PDT 24
Finished	Jul 10 07:28:03 PM PDT 24
Peak memory	278952 kb
Host	smart-b862e59c-20cb-4752-a159-205ec78ae0bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170577213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.4170577213
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.1133789458
Short name	T517
Test name
Test status
Simulation time	2480184500 ps
CPU time	102.9 seconds
Started	Jul 10 07:27:31 PM PDT 24
Finished	Jul 10 07:29:15 PM PDT 24
Peak memory	281772 kb
Host	smart-f06afdda-b58a-477d-8abc-d83b63b523b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133789458 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.1133789458
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.487486119
Short name	T674
Test name
Test status
Simulation time	6633381100 ps
CPU time	482 seconds
Started	Jul 10 07:27:27 PM PDT 24
Finished	Jul 10 07:35:30 PM PDT 24
Peak memory	314624 kb
Host	smart-7246d3e4-de5c-4ddd-bbcf-7b92e95ad399
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487486119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.487486119
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict.2470495237
Short name	T900
Test name
Test status
Simulation time	64693300 ps
CPU time	31.1 seconds
Started	Jul 10 07:27:26 PM PDT 24
Finished	Jul 10 07:27:59 PM PDT 24
Peak memory	268544 kb
Host	smart-5281f64f-f5d7-47eb-98d6-104264f28e92
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470495237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_rw_evict.2470495237
Directory	/workspace/18.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.1114116440
Short name	T462
Test name
Test status
Simulation time	70583900 ps
CPU time	123.93 seconds
Started	Jul 10 07:27:17 PM PDT 24
Finished	Jul 10 07:29:22 PM PDT 24
Peak memory	277988 kb
Host	smart-f2350a66-925b-4875-881b-d4e593ef47d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114116440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1114116440
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.1944928400
Short name	T342
Test name
Test status
Simulation time	2107372100 ps
CPU time	182.64 seconds
Started	Jul 10 07:27:27 PM PDT 24
Finished	Jul 10 07:30:31 PM PDT 24
Peak memory	265336 kb
Host	smart-cf3cb688-7f4b-4051-8c62-0d4d9518767b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944928400 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.1944928400
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.1219786364
Short name	T615
Test name
Test status
Simulation time	30402100 ps
CPU time	13.63 seconds
Started	Jul 10 07:27:48 PM PDT 24
Finished	Jul 10 07:28:02 PM PDT 24
Peak memory	258200 kb
Host	smart-faae9723-81e7-48b0-b17b-0e6e4c1ee16c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219786364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 1219786364
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.1829225392
Short name	T963
Test name
Test status
Simulation time	27565700 ps
CPU time	15.98 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:27:55 PM PDT 24
Peak memory	284412 kb
Host	smart-0e1fd9d9-caeb-44cb-9414-bcc8c7563301
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829225392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1829225392
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.93844245
Short name	T354
Test name
Test status
Simulation time	21723900 ps
CPU time	22.31 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:28:02 PM PDT 24
Peak memory	273656 kb
Host	smart-5baff494-6f28-4c77-8b4c-e3633511c0e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93844245 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 19.flash_ctrl_disable.93844245
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3654051512
Short name	T979
Test name
Test status
Simulation time	10035798200 ps
CPU time	60.52 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	271136 kb
Host	smart-5bb76de6-6376-4d0c-a000-d8a35ecb5b53
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654051512 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3654051512
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3091543337
Short name	T450
Test name
Test status
Simulation time	16892800 ps
CPU time	13.4 seconds
Started	Jul 10 07:27:47 PM PDT 24
Finished	Jul 10 07:28:01 PM PDT 24
Peak memory	265052 kb
Host	smart-2308e6d0-2d2f-4071-b195-36155ab2d2fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091543337 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3091543337
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3786895040
Short name	T890
Test name
Test status
Simulation time	100144909600 ps
CPU time	800.85 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:41:00 PM PDT 24
Peak memory	261028 kb
Host	smart-f02f5262-a703-4195-ab52-99f0db78880c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786895040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.3786895040
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1230419807
Short name	T619
Test name
Test status
Simulation time	2700490100 ps
CPU time	91.95 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:29:11 PM PDT 24
Peak memory	263152 kb
Host	smart-ca80468e-1119-439e-b967-4c7459a2946d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230419807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.1230419807
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.2434525684
Short name	T863
Test name
Test status
Simulation time	658200200 ps
CPU time	128.33 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:29:46 PM PDT 24
Peak memory	294216 kb
Host	smart-936557ac-ed36-4a89-a2c6-eebc9bd34bb6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434525684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.2434525684
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.4277943422
Short name	T625
Test name
Test status
Simulation time	11724389000 ps
CPU time	147.91 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:30:07 PM PDT 24
Peak memory	292984 kb
Host	smart-f1a4d506-5625-4cbd-8ebd-91c42e0c3629
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277943422 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.4277943422
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.2847141326
Short name	T279
Test name
Test status
Simulation time	1627138200 ps
CPU time	67.54 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	260620 kb
Host	smart-b73bbf9b-d1a4-44ca-bc52-e800774106d7
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847141326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2 847141326
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1702213612
Short name	T983
Test name
Test status
Simulation time	37758500 ps
CPU time	13.33 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:27:52 PM PDT 24
Peak memory	260084 kb
Host	smart-9728fb1d-d68d-4a7e-983d-73bd45c61525
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702213612 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1702213612
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.1054200639
Short name	T120
Test name
Test status
Simulation time	15103148300 ps
CPU time	1188.93 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:47:28 PM PDT 24
Peak memory	275012 kb
Host	smart-1eb8f2c3-1e6b-47aa-9e6f-c3e37b3b24b9
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054200639 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.1054200639
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.1023939667
Short name	T465
Test name
Test status
Simulation time	39683000 ps
CPU time	131.63 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:29:49 PM PDT 24
Peak memory	264792 kb
Host	smart-8ba1983c-1f1c-447c-a1b1-1fc4d8c80363
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023939667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.1023939667
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.1491601917
Short name	T637
Test name
Test status
Simulation time	13577178400 ps
CPU time	348.31 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:33:27 PM PDT 24
Peak memory	262996 kb
Host	smart-779bcdfd-58bd-492e-a242-2aa3d8fc2576
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1491601917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1491601917
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.2392844072
Short name	T766
Test name
Test status
Simulation time	35581200 ps
CPU time	13.57 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:27:53 PM PDT 24
Peak memory	265452 kb
Host	smart-f9080bf7-25e7-4ff6-8f94-78e35eff2d82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392844072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.2392844072
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.3472110097
Short name	T955
Test name
Test status
Simulation time	2946098800 ps
CPU time	177.28 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	281668 kb
Host	smart-40e0a149-248d-401a-a924-df9b3830f2d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472110097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3472110097
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.606907442
Short name	T841
Test name
Test status
Simulation time	62372200 ps
CPU time	34.54 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:28:13 PM PDT 24
Peak memory	275652 kb
Host	smart-e5c283c6-3009-434d-a37e-36906d0192fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606907442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_re_evict.606907442
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.1904895754
Short name	T667
Test name
Test status
Simulation time	3445529000 ps
CPU time	628.74 seconds
Started	Jul 10 07:27:35 PM PDT 24
Finished	Jul 10 07:38:06 PM PDT 24
Peak memory	310076 kb
Host	smart-5afbba5c-d198-455f-853a-1c51d4f53b28
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904895754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.1904895754
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.2538965709
Short name	T266
Test name
Test status
Simulation time	67527500 ps
CPU time	31.16 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:28:10 PM PDT 24
Peak memory	275668 kb
Host	smart-c2dcab85-f1bd-4ac8-aee7-096912bbd00b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538965709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.2538965709
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1776560172
Short name	T929
Test name
Test status
Simulation time	42183400 ps
CPU time	30.76 seconds
Started	Jul 10 07:27:36 PM PDT 24
Finished	Jul 10 07:28:09 PM PDT 24
Peak memory	267560 kb
Host	smart-69872b9d-2e2f-4b2a-854d-4e2c2a92cd78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776560172 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.1776560172
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.4038855023
Short name	T185
Test name
Test status
Simulation time	2258133600 ps
CPU time	64.17 seconds
Started	Jul 10 07:27:37 PM PDT 24
Finished	Jul 10 07:28:44 PM PDT 24
Peak memory	265060 kb
Host	smart-b926f8f6-b4e8-4c8c-8d73-bb3df6463263
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038855023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.4038855023
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.3121115431
Short name	T586
Test name
Test status
Simulation time	41857300 ps
CPU time	145.11 seconds
Started	Jul 10 07:27:35 PM PDT 24
Finished	Jul 10 07:30:02 PM PDT 24
Peak memory	278984 kb
Host	smart-a61a4900-d9df-46e0-966e-92aab24200b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121115431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3121115431
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.1791866208
Short name	T1077
Test name
Test status
Simulation time	2602056600 ps
CPU time	238.39 seconds
Started	Jul 10 07:27:35 PM PDT 24
Finished	Jul 10 07:31:36 PM PDT 24
Peak memory	260116 kb
Host	smart-785e8eb3-d063-42f8-bd24-e8af461cd3f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791866208 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.1791866208
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.954486327
Short name	T45
Test name
Test status
Simulation time	48713000 ps
CPU time	13.45 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:25:05 PM PDT 24
Peak memory	265412 kb
Host	smart-9ccd8cec-d6ff-41d4-b1e1-94412e0d00c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954486327 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.954486327
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.3252808593
Short name	T855
Test name
Test status
Simulation time	36810700 ps
CPU time	13.82 seconds
Started	Jul 10 07:24:44 PM PDT 24
Finished	Jul 10 07:24:59 PM PDT 24
Peak memory	258292 kb
Host	smart-3da683c2-adc4-42ee-b4ed-9487c0a85353
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252808593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3 252808593
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.732882714
Short name	T772
Test name
Test status
Simulation time	63948600 ps
CPU time	13.65 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:10 PM PDT 24
Peak memory	265024 kb
Host	smart-90065803-004b-4eb9-9b67-f8173c522006
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732882714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. flash_ctrl_config_regwen.732882714
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.943672733
Short name	T630
Test name
Test status
Simulation time	53228600 ps
CPU time	16.01 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:24:56 PM PDT 24
Peak memory	284452 kb
Host	smart-720bffc1-9353-4360-8aef-ea97fac63a01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943672733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.943672733
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.1153857630
Short name	T1012
Test name
Test status
Simulation time	26721800 ps
CPU time	21.22 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:24:53 PM PDT 24
Peak memory	273636 kb
Host	smart-a74856b4-3c1c-44cb-89ba-4abbd5dc4464
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153857630 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.1153857630
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.1478513548
Short name	T976
Test name
Test status
Simulation time	8188676400 ps
CPU time	417.81 seconds
Started	Jul 10 07:24:32 PM PDT 24
Finished	Jul 10 07:31:31 PM PDT 24
Peak memory	263524 kb
Host	smart-6ebd53cb-35ef-4062-ba9a-6464e98cba2e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1478513548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1478513548
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.1577212352
Short name	T646
Test name
Test status
Simulation time	4591907800 ps
CPU time	2193.29 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 08:01:04 PM PDT 24
Peak memory	265244 kb
Host	smart-4eec49a3-bbc5-43f2-ace3-05e6a47f76ba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1577212352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1577212352
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.2264736698
Short name	T89
Test name
Test status
Simulation time	6121429600 ps
CPU time	2404.65 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 08:04:41 PM PDT 24
Peak memory	264868 kb
Host	smart-37b28711-5e70-42e3-8799-c0f623719855
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264736698 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2264736698
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.2901612317
Short name	T960
Test name
Test status
Simulation time	334182100 ps
CPU time	853.71 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:38:52 PM PDT 24
Peak memory	270508 kb
Host	smart-a0ea2a52-b920-4ce9-b5ea-11aba1a338b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901612317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2901612317
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.2489744174
Short name	T686
Test name
Test status
Simulation time	925138100 ps
CPU time	23.41 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:25:14 PM PDT 24
Peak memory	262588 kb
Host	smart-7a9ffca4-d227-4b8a-902a-ada1f2487d08
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489744174 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2489744174
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.662978980
Short name	T388
Test name
Test status
Simulation time	1353941000 ps
CPU time	39.2 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:25:29 PM PDT 24
Peak memory	265336 kb
Host	smart-ca60e223-59fa-4f79-b25c-afc57c6d3bfc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662978980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_fs_sup.662978980
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.436690956
Short name	T127
Test name
Test status
Simulation time	195652939700 ps
CPU time	4304.56 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 08:36:17 PM PDT 24
Peak memory	265120 kb
Host	smart-913d9d32-5d64-4813-b26e-df0ed6326f77
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436690956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_full_mem_access.436690956
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.3071762975
Short name	T1089
Test name
Test status
Simulation time	39463800 ps
CPU time	30.22 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:26 PM PDT 24
Peak memory	268480 kb
Host	smart-36e9b168-0ce4-431e-abde-d9e094a21fb4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071762975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_host_addr_infection.3071762975
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.90601331
Short name	T272
Test name
Test status
Simulation time	10034481400 ps
CPU time	52.84 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:25:32 PM PDT 24
Peak memory	278052 kb
Host	smart-c88e33f3-f0ea-452e-85b4-f94f1a536210
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90601331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.90601331
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1251165349
Short name	T270
Test name
Test status
Simulation time	15327500 ps
CPU time	13.46 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:24:55 PM PDT 24
Peak memory	265040 kb
Host	smart-ab71a0f8-c064-4b41-a746-73f394539085
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251165349 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1251165349
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3377634163
Short name	T170
Test name
Test status
Simulation time	80135527400 ps
CPU time	931.6 seconds
Started	Jul 10 07:24:41 PM PDT 24
Finished	Jul 10 07:40:14 PM PDT 24
Peak memory	261068 kb
Host	smart-35c1764f-f294-4030-93f8-a0b6ab7244d5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377634163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.3377634163
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2332379973
Short name	T444
Test name
Test status
Simulation time	2298637400 ps
CPU time	73.84 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:26:03 PM PDT 24
Peak memory	260944 kb
Host	smart-be5c7ebc-2f6a-45c8-9987-557a9e36aee3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332379973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h w_sec_otp.2332379973
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.1484775410
Short name	T55
Test name
Test status
Simulation time	19278355700 ps
CPU time	665.57 seconds
Started	Jul 10 07:24:32 PM PDT 24
Finished	Jul 10 07:35:39 PM PDT 24
Peak memory	334896 kb
Host	smart-3072e6b7-578b-4e97-95f6-7ce2417c5a67
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484775410 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.1484775410
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.3741128911
Short name	T605
Test name
Test status
Simulation time	5228120600 ps
CPU time	174.71 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:27:27 PM PDT 24
Peak memory	291368 kb
Host	smart-22620d8f-2425-4f09-9e1a-ce6cfc7b32f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741128911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_intr_rd.3741128911
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1413727496
Short name	T415
Test name
Test status
Simulation time	20916918900 ps
CPU time	156.08 seconds
Started	Jul 10 07:24:42 PM PDT 24
Finished	Jul 10 07:27:19 PM PDT 24
Peak memory	293092 kb
Host	smart-10d183d8-36bc-46b3-9040-6d861ae1f83a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413727496 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.1413727496
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.2618921448
Short name	T414
Test name
Test status
Simulation time	27483674600 ps
CPU time	77.49 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:25:50 PM PDT 24
Peak memory	261704 kb
Host	smart-23892409-540f-4fa4-8f5c-446c6e557b01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618921448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.2618921448
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1750205514
Short name	T526
Test name
Test status
Simulation time	75088189500 ps
CPU time	205.36 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:28:21 PM PDT 24
Peak memory	260508 kb
Host	smart-85af5a9a-8d97-42bd-b6fc-88b752fc8308
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175 0205514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1750205514
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.2183313327
Short name	T377
Test name
Test status
Simulation time	23052392400 ps
CPU time	83.53 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:25:56 PM PDT 24
Peak memory	260612 kb
Host	smart-91d62748-3e04-44e4-9274-b1cb050a8cd2
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183313327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2183313327
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3463319791
Short name	T1075
Test name
Test status
Simulation time	26504100 ps
CPU time	13.37 seconds
Started	Jul 10 07:24:39 PM PDT 24
Finished	Jul 10 07:24:54 PM PDT 24
Peak memory	265032 kb
Host	smart-9c779518-3afc-4072-b19e-2403caf44546
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463319791 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3463319791
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.654606397
Short name	T93
Test name
Test status
Simulation time	993922100 ps
CPU time	72.49 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:25:49 PM PDT 24
Peak memory	260496 kb
Host	smart-f0164402-21c9-4adc-94e5-fd66c9df7fc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654606397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.654606397
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.874188153
Short name	T548
Test name
Test status
Simulation time	2324314100 ps
CPU time	120.05 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:26:37 PM PDT 24
Peak memory	265184 kb
Host	smart-f380f9c2-0a1d-4b33-92f5-b10d26d7eba7
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874188153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.874188153
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.3415424501
Short name	T1050
Test name
Test status
Simulation time	288364200 ps
CPU time	110.2 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:26:26 PM PDT 24
Peak memory	260884 kb
Host	smart-0457d17a-bb5c-403b-b42c-80f28340f25d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415424501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot p_reset.3415424501
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.2068612649
Short name	T645
Test name
Test status
Simulation time	5462400400 ps
CPU time	190.74 seconds
Started	Jul 10 07:24:29 PM PDT 24
Finished	Jul 10 07:27:43 PM PDT 24
Peak memory	281816 kb
Host	smart-b1e2370d-6b1e-4c69-a22e-4eed27a983e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068612649 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2068612649
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.3709641768
Short name	T600
Test name
Test status
Simulation time	3071745400 ps
CPU time	482.25 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:32:34 PM PDT 24
Peak memory	262980 kb
Host	smart-b7bb4281-525d-4966-a5e1-84c359af7306
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3709641768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3709641768
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.788365315
Short name	T78
Test name
Test status
Simulation time	755021200 ps
CPU time	16.88 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:25:10 PM PDT 24
Peak memory	265552 kb
Host	smart-fcc59de8-bcec-4356-87f8-2323687d5615
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788365315 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.788365315
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1017612845
Short name	T202
Test name
Test status
Simulation time	47804000 ps
CPU time	13.89 seconds
Started	Jul 10 07:24:41 PM PDT 24
Finished	Jul 10 07:24:56 PM PDT 24
Peak memory	265168 kb
Host	smart-75bf8d0f-52c2-4524-a669-a26fc3b856f6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017612845 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1017612845
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.144143035
Short name	T344
Test name
Test status
Simulation time	9731131900 ps
CPU time	180.39 seconds
Started	Jul 10 07:24:52 PM PDT 24
Finished	Jul 10 07:27:57 PM PDT 24
Peak memory	260620 kb
Host	smart-f6a045aa-deb2-4cfb-8469-b84e71f0994b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144143035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_prog_reset.144143035
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.2529975126
Short name	T139
Test name
Test status
Simulation time	1587080800 ps
CPU time	1003.53 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:41:14 PM PDT 24
Peak memory	286060 kb
Host	smart-dce31cf9-ea43-4480-969a-5f826a68b3df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529975126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2529975126
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1784109096
Short name	T213
Test name
Test status
Simulation time	2811773400 ps
CPU time	149.62 seconds
Started	Jul 10 07:24:30 PM PDT 24
Finished	Jul 10 07:27:02 PM PDT 24
Peak memory	262864 kb
Host	smart-06f39ce4-ca0d-472d-87ca-887e5a6c4f7c
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1784109096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1784109096
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.2304780200
Short name	T196
Test name
Test status
Simulation time	184891000 ps
CPU time	31.31 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:25:30 PM PDT 24
Peak memory	275704 kb
Host	smart-acdf7f4d-ee3d-45b8-a8dd-08ae723ac063
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304780200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.2304780200
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.1068794955
Short name	T143
Test name
Test status
Simulation time	127518600 ps
CPU time	35.12 seconds
Started	Jul 10 07:24:31 PM PDT 24
Finished	Jul 10 07:25:08 PM PDT 24
Peak memory	268508 kb
Host	smart-734a496c-69e4-4dff-b0c2-c676325f9ed7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068794955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_re_evict.1068794955
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1608433311
Short name	T808
Test name
Test status
Simulation time	18078000 ps
CPU time	22.57 seconds
Started	Jul 10 07:24:30 PM PDT 24
Finished	Jul 10 07:24:55 PM PDT 24
Peak memory	265008 kb
Host	smart-5396fb3c-0c6a-466b-8cbf-d599b061309c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608433311 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1608433311
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.3775852382
Short name	T1021
Test name
Test status
Simulation time	41988500 ps
CPU time	22.45 seconds
Started	Jul 10 07:24:32 PM PDT 24
Finished	Jul 10 07:24:56 PM PDT 24
Peak memory	265408 kb
Host	smart-fc3c0bec-e43f-4996-8662-3265c86e97a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775852382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.3775852382
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.4270164093
Short name	T164
Test name
Test status
Simulation time	39747844000 ps
CPU time	927.81 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:40:05 PM PDT 24
Peak memory	261484 kb
Host	smart-0c9316ad-0ba4-4ded-9fb7-2b63d5681205
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270164093 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.4270164093
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.196514556
Short name	T839
Test name
Test status
Simulation time	900766300 ps
CPU time	115.41 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 07:26:31 PM PDT 24
Peak memory	281736 kb
Host	smart-7fc0d8ba-b72e-4239-8a3d-82ffbf47252f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196514556 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.flash_ctrl_ro.196514556
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.2517285144
Short name	T616
Test name
Test status
Simulation time	3038487800 ps
CPU time	173.8 seconds
Started	Jul 10 07:24:39 PM PDT 24
Finished	Jul 10 07:27:34 PM PDT 24
Peak memory	290016 kb
Host	smart-8db2ae0f-0e45-417a-a439-4e71b0bb21f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517285144 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2517285144
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.2522975915
Short name	T777
Test name
Test status
Simulation time	18815185600 ps
CPU time	670.01 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:35:47 PM PDT 24
Peak memory	317652 kb
Host	smart-824f6a9d-ac16-4c5b-bf60-d2f6943e2b8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522975915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.flash_ctrl_rw.2522975915
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict.1044234722
Short name	T550
Test name
Test status
Simulation time	98112000 ps
CPU time	31.18 seconds
Started	Jul 10 07:24:42 PM PDT 24
Finished	Jul 10 07:25:14 PM PDT 24
Peak memory	275692 kb
Host	smart-a449365c-f99b-4351-a2e1-99b395565363
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044234722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla sh_ctrl_rw_evict.1044234722
Directory	/workspace/2.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2486008584
Short name	T502
Test name
Test status
Simulation time	30400300 ps
CPU time	31.44 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:25:21 PM PDT 24
Peak memory	268476 kb
Host	smart-a0a3c9d0-2a61-41de-879f-9e18dffb5c11
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486008584 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2486008584
Directory	/workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_serr.1753517745
Short name	T932
Test name
Test status
Simulation time	7792512900 ps
CPU time	523.32 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:33:24 PM PDT 24
Peak memory	320872 kb
Host	smart-4e1ba609-fcfb-4456-be9f-b9fe8d9516fb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753517745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s err.1753517745
Directory	/workspace/2.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.3066711270
Short name	T17
Test name
Test status
Simulation time	4001949800 ps
CPU time	4910 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 08:46:40 PM PDT 24
Peak memory	285292 kb
Host	smart-bb2c2816-0c36-45a0-9236-a8b05c5a020f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066711270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3066711270
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.571644116
Short name	T357
Test name
Test status
Simulation time	8182582400 ps
CPU time	74.82 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:26:08 PM PDT 24
Peak memory	263600 kb
Host	smart-766c105e-c6cf-4bd9-95b2-7592c8db5951
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571644116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.571644116
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.2201984581
Short name	T563
Test name
Test status
Simulation time	1803486800 ps
CPU time	86.16 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:26:03 PM PDT 24
Peak memory	265456 kb
Host	smart-ad05f5e5-74e4-4ef6-a4b4-00289c890b62
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201984581 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.2201984581
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.3819606589
Short name	T495
Test name
Test status
Simulation time	1046094700 ps
CPU time	66.25 seconds
Started	Jul 10 07:24:52 PM PDT 24
Finished	Jul 10 07:26:04 PM PDT 24
Peak memory	273944 kb
Host	smart-78a6876b-b222-48db-8256-678f6a2f2f16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819606589 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_serr_counter.3819606589
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.2339222828
Short name	T234
Test name
Test status
Simulation time	93664900 ps
CPU time	193.96 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:27:45 PM PDT 24
Peak memory	277672 kb
Host	smart-0b7af532-044a-4acf-8b82-81c26149d011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339222828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2339222828
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.3083766003
Short name	T898
Test name
Test status
Simulation time	29448200 ps
CPU time	26.52 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:24:58 PM PDT 24
Peak memory	259648 kb
Host	smart-ea50d14b-037c-468f-9356-2ac3a84529f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083766003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3083766003
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.3640770000
Short name	T687
Test name
Test status
Simulation time	1796944900 ps
CPU time	866.72 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:39:08 PM PDT 24
Peak memory	286636 kb
Host	smart-7cf01efa-ff42-4199-8e35-6ddba25df4cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640770000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres s_all.3640770000
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.1096419268
Short name	T536
Test name
Test status
Simulation time	89170000 ps
CPU time	24.39 seconds
Started	Jul 10 07:24:28 PM PDT 24
Finished	Jul 10 07:24:54 PM PDT 24
Peak memory	262456 kb
Host	smart-867c7cf3-8268-4eb7-8280-3a80fb499217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1096419268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1096419268
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.3133692572
Short name	T609
Test name
Test status
Simulation time	10637569900 ps
CPU time	222.52 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:28:19 PM PDT 24
Peak memory	265316 kb
Host	smart-fc7708ef-3e71-4cb5-b1f2-5c2dc0fca529
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133692572 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_wo.3133692572
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.3988779112
Short name	T420
Test name
Test status
Simulation time	73962400 ps
CPU time	13.89 seconds
Started	Jul 10 07:27:50 PM PDT 24
Finished	Jul 10 07:28:05 PM PDT 24
Peak memory	265508 kb
Host	smart-658cf49e-064b-42d5-a43f-9ca05f6b06de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988779112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test. 3988779112
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.3466988346
Short name	T817
Test name
Test status
Simulation time	140127600 ps
CPU time	15.87 seconds
Started	Jul 10 07:27:48 PM PDT 24
Finished	Jul 10 07:28:04 PM PDT 24
Peak memory	275036 kb
Host	smart-751da340-40fe-446c-9c30-6a15c78a5382
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466988346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3466988346
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.2444143800
Short name	T340
Test name
Test status
Simulation time	10975600 ps
CPU time	21.99 seconds
Started	Jul 10 07:27:50 PM PDT 24
Finished	Jul 10 07:28:13 PM PDT 24
Peak memory	264044 kb
Host	smart-4d5a1150-c5ad-4da0-a786-b2dcec26a4e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444143800 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.2444143800
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2486323931
Short name	T670
Test name
Test status
Simulation time	3426161400 ps
CPU time	261.81 seconds
Started	Jul 10 07:27:47 PM PDT 24
Finished	Jul 10 07:32:10 PM PDT 24
Peak memory	263208 kb
Host	smart-192a1a15-1a88-40eb-b9e9-c06995275112
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486323931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.2486323931
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.1305464429
Short name	T308
Test name
Test status
Simulation time	1467399500 ps
CPU time	190.15 seconds
Started	Jul 10 07:27:50 PM PDT 24
Finished	Jul 10 07:31:01 PM PDT 24
Peak memory	291760 kb
Host	smart-b6f18302-73e2-454f-a03a-9ef7ff7e6e3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305464429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.1305464429
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1165894151
Short name	T912
Test name
Test status
Simulation time	5798490800 ps
CPU time	138.58 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:30:06 PM PDT 24
Peak memory	292908 kb
Host	smart-ca4fd39a-baf2-4ad0-a453-967c340d4021
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165894151 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1165894151
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.2224231647
Short name	T151
Test name
Test status
Simulation time	85768100 ps
CPU time	129.42 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	260984 kb
Host	smart-ef50dcb0-b850-4b67-b490-708af682e87c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224231647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o tp_reset.2224231647
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.4241667139
Short name	T208
Test name
Test status
Simulation time	4228317400 ps
CPU time	177.57 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:30:44 PM PDT 24
Peak memory	265256 kb
Host	smart-e602f577-4259-4b79-b12e-8bb9684fad52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241667139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.4241667139
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict.3559911230
Short name	T754
Test name
Test status
Simulation time	28674900 ps
CPU time	31.28 seconds
Started	Jul 10 07:27:47 PM PDT 24
Finished	Jul 10 07:28:19 PM PDT 24
Peak memory	268540 kb
Host	smart-15b4785c-e7b3-414b-b450-5e1ce6f1f35c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559911230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl ash_ctrl_rw_evict.3559911230
Directory	/workspace/20.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.1972662729
Short name	T593
Test name
Test status
Simulation time	18292720600 ps
CPU time	82.53 seconds
Started	Jul 10 07:27:51 PM PDT 24
Finished	Jul 10 07:29:15 PM PDT 24
Peak memory	264220 kb
Host	smart-efb2b887-d990-4657-8eb5-2f723f1a2b64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972662729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1972662729
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.490933333
Short name	T809
Test name
Test status
Simulation time	28713700 ps
CPU time	76.47 seconds
Started	Jul 10 07:27:46 PM PDT 24
Finished	Jul 10 07:29:03 PM PDT 24
Peak memory	275648 kb
Host	smart-086062b4-ee26-48f1-b812-14b7638a8885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490933333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.490933333
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.2913531313
Short name	T1023
Test name
Test status
Simulation time	87515900 ps
CPU time	13.72 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:28:16 PM PDT 24
Peak memory	265316 kb
Host	smart-810d818c-93e9-4b3e-bff6-bcea2994c370
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913531313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 2913531313
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.4052205785
Short name	T1098
Test name
Test status
Simulation time	18701000 ps
CPU time	15.98 seconds
Started	Jul 10 07:28:00 PM PDT 24
Finished	Jul 10 07:28:18 PM PDT 24
Peak memory	274964 kb
Host	smart-defd910f-204b-4be9-ab42-755a62dda504
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052205785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.4052205785
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1483049798
Short name	T914
Test name
Test status
Simulation time	2255251200 ps
CPU time	77.9 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:29:20 PM PDT 24
Peak memory	263272 kb
Host	smart-3be63bfc-d331-44a8-bdec-be23f7196d8d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483049798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.1483049798
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.235350066
Short name	T897
Test name
Test status
Simulation time	713628600 ps
CPU time	138.12 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:30:20 PM PDT 24
Peak memory	294100 kb
Host	smart-31390a0a-6d5c-46e2-987d-0fd2209c37ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235350066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas h_ctrl_intr_rd.235350066
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2256979815
Short name	T557
Test name
Test status
Simulation time	35775947900 ps
CPU time	178.56 seconds
Started	Jul 10 07:27:59 PM PDT 24
Finished	Jul 10 07:30:59 PM PDT 24
Peak memory	293004 kb
Host	smart-1d8e4afc-4438-4b5d-b23e-1e05383dae3b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256979815 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2256979815
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.2263415894
Short name	T1018
Test name
Test status
Simulation time	55388000 ps
CPU time	111.01 seconds
Started	Jul 10 07:28:00 PM PDT 24
Finished	Jul 10 07:29:52 PM PDT 24
Peak memory	261940 kb
Host	smart-482a4598-2d15-4d12-a682-7905f0704bf7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263415894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.2263415894
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.1921546862
Short name	T940
Test name
Test status
Simulation time	34340054700 ps
CPU time	184.75 seconds
Started	Jul 10 07:28:00 PM PDT 24
Finished	Jul 10 07:31:05 PM PDT 24
Peak memory	260556 kb
Host	smart-55f002b6-a111-4c9f-9289-1a06160fce01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921546862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.1921546862
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.4208979204
Short name	T24
Test name
Test status
Simulation time	28841600 ps
CPU time	28.87 seconds
Started	Jul 10 07:27:59 PM PDT 24
Finished	Jul 10 07:28:28 PM PDT 24
Peak memory	267504 kb
Host	smart-f859df25-bff9-4a8c-a54b-725b134c4bba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208979204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl ash_ctrl_rw_evict.4208979204
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1703427413
Short name	T671
Test name
Test status
Simulation time	202702700 ps
CPU time	29.52 seconds
Started	Jul 10 07:28:00 PM PDT 24
Finished	Jul 10 07:28:30 PM PDT 24
Peak memory	275728 kb
Host	smart-6e183f07-cdeb-448e-b0d6-06e800728e5f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703427413 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.1703427413
Directory	/workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.4202553712
Short name	T1111
Test name
Test status
Simulation time	1361331700 ps
CPU time	55.63 seconds
Started	Jul 10 07:28:02 PM PDT 24
Finished	Jul 10 07:28:59 PM PDT 24
Peak memory	265128 kb
Host	smart-ca6423c3-4b32-4542-b190-0737a1cd7521
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202553712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.4202553712
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.3127535417
Short name	T534
Test name
Test status
Simulation time	19104600 ps
CPU time	121.92 seconds
Started	Jul 10 07:27:47 PM PDT 24
Finished	Jul 10 07:29:50 PM PDT 24
Peak memory	277416 kb
Host	smart-08c9db5b-417b-48e4-b72c-78bfceecf490
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127535417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3127535417
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.141038344
Short name	T529
Test name
Test status
Simulation time	50014200 ps
CPU time	13.45 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:28:29 PM PDT 24
Peak memory	258312 kb
Host	smart-18fdf2e8-b52b-418c-b9b6-cee547e8bb77
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141038344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.141038344
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.968901890
Short name	T559
Test name
Test status
Simulation time	50237100 ps
CPU time	16.39 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:31 PM PDT 24
Peak memory	274948 kb
Host	smart-3a97da08-c997-408d-8da0-b21c32f8de37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968901890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.968901890
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.3604570758
Short name	T80
Test name
Test status
Simulation time	16197200 ps
CPU time	20.35 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:28:23 PM PDT 24
Peak memory	273628 kb
Host	smart-1a06e569-b26b-4812-92b4-2ef9a0549fdf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604570758 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.3604570758
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1702366963
Short name	T472
Test name
Test status
Simulation time	8375365600 ps
CPU time	179.35 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:31:01 PM PDT 24
Peak memory	260960 kb
Host	smart-e7f35996-bf1b-4998-b4c1-aaf8d78a6a31
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702366963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.1702366963
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.4288239532
Short name	T748
Test name
Test status
Simulation time	8293888500 ps
CPU time	185.48 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:31:08 PM PDT 24
Peak memory	284880 kb
Host	smart-61f92aec-03d2-4982-9613-1ce599dd297f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288239532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.4288239532
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.883991450
Short name	T1049
Test name
Test status
Simulation time	22621621200 ps
CPU time	139.02 seconds
Started	Jul 10 07:27:59 PM PDT 24
Finished	Jul 10 07:30:19 PM PDT 24
Peak memory	292616 kb
Host	smart-cf0fea7b-4d56-4ba3-863f-8cab17b03e4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883991450 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.883991450
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.1038196056
Short name	T973
Test name
Test status
Simulation time	80198100 ps
CPU time	131.07 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:30:14 PM PDT 24
Peak memory	261064 kb
Host	smart-366f1787-9388-41fe-88a2-ce2e47a35b74
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038196056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.1038196056
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.1462039621
Short name	T602
Test name
Test status
Simulation time	70199500 ps
CPU time	13.62 seconds
Started	Jul 10 07:28:00 PM PDT 24
Finished	Jul 10 07:28:15 PM PDT 24
Peak memory	259196 kb
Host	smart-af77229d-f348-49dc-baaf-13382bcf4f13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462039621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.1462039621
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.2217589320
Short name	T199
Test name
Test status
Simulation time	78908600 ps
CPU time	30.55 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:28:33 PM PDT 24
Peak memory	275692 kb
Host	smart-903b6990-4e18-4d02-95dc-679217c30fab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217589320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.2217589320
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.72053590
Short name	T988
Test name
Test status
Simulation time	67202100 ps
CPU time	28.03 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:28:31 PM PDT 24
Peak memory	275712 kb
Host	smart-9c537988-e801-4d9c-8f57-e9b47a34fd7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72053590 -assert nopostproc +UVM_TESTNAME=fl ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.72053590
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.744488316
Short name	T806
Test name
Test status
Simulation time	5055449000 ps
CPU time	77.85 seconds
Started	Jul 10 07:28:01 PM PDT 24
Finished	Jul 10 07:29:20 PM PDT 24
Peak memory	263784 kb
Host	smart-326d9edf-e2a8-4632-959b-87fca4e3a46e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744488316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.744488316
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.562637303
Short name	T565
Test name
Test status
Simulation time	33675400 ps
CPU time	146.96 seconds
Started	Jul 10 07:28:02 PM PDT 24
Finished	Jul 10 07:30:30 PM PDT 24
Peak memory	277128 kb
Host	smart-94fbc911-bdd5-45a8-bd51-abb0b2d29f8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562637303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.562637303
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.2567351867
Short name	T1112
Test name
Test status
Simulation time	58957100 ps
CPU time	13.68 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:28 PM PDT 24
Peak memory	258228 kb
Host	smart-4c29643a-c9c5-431a-a7e2-c4cb0f07c2f6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567351867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test. 2567351867
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.2527321345
Short name	T485
Test name
Test status
Simulation time	15379400 ps
CPU time	16.02 seconds
Started	Jul 10 07:28:15 PM PDT 24
Finished	Jul 10 07:28:33 PM PDT 24
Peak memory	274996 kb
Host	smart-b01f563b-d2fd-4374-b7c3-843ce0feae0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527321345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2527321345
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.3922939080
Short name	T1080
Test name
Test status
Simulation time	10173700 ps
CPU time	20.45 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:36 PM PDT 24
Peak memory	273628 kb
Host	smart-6a5238d1-348f-4f78-b016-db41b6a2c491
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922939080 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.3922939080
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1004492384
Short name	T972
Test name
Test status
Simulation time	8807363500 ps
CPU time	143.62 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:30:38 PM PDT 24
Peak memory	262788 kb
Host	smart-8d1c70b9-02b6-4684-9406-c29405acd6b5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004492384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ hw_sec_otp.1004492384
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.419225058
Short name	T314
Test name
Test status
Simulation time	2572941900 ps
CPU time	111.94 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:30:08 PM PDT 24
Peak memory	294560 kb
Host	smart-4151e075-8f1f-4cbd-a6b6-83ea402eb3f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419225058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas h_ctrl_intr_rd.419225058
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.40639632
Short name	T416
Test name
Test status
Simulation time	5902195600 ps
CPU time	126.26 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:30:22 PM PDT 24
Peak memory	293092 kb
Host	smart-d3714428-067d-4c3e-878a-9741502f8d75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.40639632
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.2468667797
Short name	T467
Test name
Test status
Simulation time	79242700 ps
CPU time	130.45 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:30:26 PM PDT 24
Peak memory	260028 kb
Host	smart-3418e410-8365-43ed-ad14-eb389d3c8ba2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468667797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o tp_reset.2468667797
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.2731956088
Short name	T655
Test name
Test status
Simulation time	4271025600 ps
CPU time	160.19 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:30:54 PM PDT 24
Peak memory	261112 kb
Host	smart-4063f7df-5950-4bbe-bac0-f42f7cda7854
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731956088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.2731956088
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.1777621680
Short name	T895
Test name
Test status
Simulation time	94827000 ps
CPU time	31.61 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:46 PM PDT 24
Peak memory	275672 kb
Host	smart-189595fa-b49d-4577-b9bc-73d168c88866
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777621680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.1777621680
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3933944303
Short name	T758
Test name
Test status
Simulation time	74494700 ps
CPU time	32.43 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:48 PM PDT 24
Peak memory	275656 kb
Host	smart-9d3251c0-c44f-43d5-b9e0-95a8f55dcb30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933944303 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3933944303
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.2821045019
Short name	T799
Test name
Test status
Simulation time	14852477300 ps
CPU time	71.69 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:29:27 PM PDT 24
Peak memory	263772 kb
Host	smart-87652a67-142b-47bc-84bc-343996a92816
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821045019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2821045019
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.785312695
Short name	T792
Test name
Test status
Simulation time	3980011100 ps
CPU time	235.78 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:32:09 PM PDT 24
Peak memory	281556 kb
Host	smart-59c989c3-2a64-486f-ae84-a28e5bcc1065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785312695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.785312695
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.3163046846
Short name	T742
Test name
Test status
Simulation time	158997300 ps
CPU time	13.63 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:28:27 PM PDT 24
Peak memory	265288 kb
Host	smart-39831700-f53f-4bf6-9764-229258f7c7cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163046846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test. 3163046846
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.1287120315
Short name	T804
Test name
Test status
Simulation time	15011200 ps
CPU time	16.04 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:28:32 PM PDT 24
Peak memory	284360 kb
Host	smart-2d2d0f06-0567-468b-b24d-8dbb977f0780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287120315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1287120315
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.2003634132
Short name	T70
Test name
Test status
Simulation time	41944800 ps
CPU time	21.94 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:28:35 PM PDT 24
Peak memory	274048 kb
Host	smart-0b11d1b7-64a4-4a82-bfa4-403b824b5911
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003634132 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.2003634132
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1605985189
Short name	T618
Test name
Test status
Simulation time	4211794800 ps
CPU time	43.58 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:28:59 PM PDT 24
Peak memory	263316 kb
Host	smart-e6dec6f3-4d51-4748-b6d0-23303f2319e4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605985189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.1605985189
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.1635143735
Short name	T850
Test name
Test status
Simulation time	10907434400 ps
CPU time	216.31 seconds
Started	Jul 10 07:28:15 PM PDT 24
Finished	Jul 10 07:31:53 PM PDT 24
Peak memory	291388 kb
Host	smart-419d97f2-e0ad-4ae3-a1d0-5132ef5ffda0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635143735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_intr_rd.1635143735
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.968582427
Short name	T819
Test name
Test status
Simulation time	13461746000 ps
CPU time	272.78 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:32:48 PM PDT 24
Peak memory	291928 kb
Host	smart-c9efb2b1-48a9-4858-b91e-c2632373cec5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968582427 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.968582427
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.1960714357
Short name	T1045
Test name
Test status
Simulation time	132776100 ps
CPU time	131.43 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:30:27 PM PDT 24
Peak memory	261188 kb
Host	smart-849c4479-1e2f-4c95-83ec-18cbfbbddcbe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960714357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.1960714357
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.1680555549
Short name	T891
Test name
Test status
Simulation time	20105700 ps
CPU time	13.41 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:28:28 PM PDT 24
Peak memory	259528 kb
Host	smart-8a154986-3ce9-4c34-bb2b-12de41d1245b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680555549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.1680555549
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict.3156636647
Short name	T721
Test name
Test status
Simulation time	111425900 ps
CPU time	29.23 seconds
Started	Jul 10 07:28:11 PM PDT 24
Finished	Jul 10 07:28:42 PM PDT 24
Peak memory	275708 kb
Host	smart-3add630e-ed0b-403c-afb9-32734fec07d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156636647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl ash_ctrl_rw_evict.3156636647
Directory	/workspace/24.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.637219758
Short name	T468
Test name
Test status
Simulation time	88314500 ps
CPU time	27.84 seconds
Started	Jul 10 07:28:14 PM PDT 24
Finished	Jul 10 07:28:44 PM PDT 24
Peak memory	267584 kb
Host	smart-e5807efe-4928-41ed-9731-a8a5e84b6bfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637219758 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.637219758
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.1624156010
Short name	T700
Test name
Test status
Simulation time	49739700 ps
CPU time	148.45 seconds
Started	Jul 10 07:28:13 PM PDT 24
Finished	Jul 10 07:30:44 PM PDT 24
Peak memory	278296 kb
Host	smart-8b0e0db4-931d-4534-aeeb-862031729dc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624156010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1624156010
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.1798088433
Short name	T949
Test name
Test status
Simulation time	55774900 ps
CPU time	13.96 seconds
Started	Jul 10 07:28:27 PM PDT 24
Finished	Jul 10 07:28:41 PM PDT 24
Peak memory	258216 kb
Host	smart-e264fc12-1feb-4021-b7c1-31e8470b22c0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798088433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 1798088433
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.605682056
Short name	T1107
Test name
Test status
Simulation time	27313300 ps
CPU time	16.06 seconds
Started	Jul 10 07:34:30 PM PDT 24
Finished	Jul 10 07:34:47 PM PDT 24
Peak memory	284396 kb
Host	smart-aa13f230-84fd-4fff-b117-028ea5b0da07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=605682056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.605682056
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3210161848
Short name	T621
Test name
Test status
Simulation time	20410357800 ps
CPU time	102.19 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	263368 kb
Host	smart-e2444792-851d-470c-a0c5-666eafa70d2d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210161848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.3210161848
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.642464787
Short name	T303
Test name
Test status
Simulation time	73651100 ps
CPU time	131.33 seconds
Started	Jul 10 07:28:09 PM PDT 24
Finished	Jul 10 07:30:22 PM PDT 24
Peak memory	260332 kb
Host	smart-767fed65-aa6b-465d-bb13-2567055213f2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642464787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ot p_reset.642464787
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.25789511
Short name	T842
Test name
Test status
Simulation time	21912300 ps
CPU time	14.35 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:28:39 PM PDT 24
Peak memory	265224 kb
Host	smart-8129e0bc-4498-4054-b419-134cdc715c45
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25789511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.flash_ctrl_prog_reset.25789511
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.1856315251
Short name	T626
Test name
Test status
Simulation time	85749800 ps
CPU time	31.73 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	275648 kb
Host	smart-14a58c41-c3dd-414e-9e14-99ea4b8f8552
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856315251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl ash_ctrl_rw_evict.1856315251
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3658969427
Short name	T383
Test name
Test status
Simulation time	32627700 ps
CPU time	31.4 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	275628 kb
Host	smart-83cb319b-7d31-4137-91a2-9866844f2da7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658969427 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.3658969427
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.248600903
Short name	T1070
Test name
Test status
Simulation time	6535584100 ps
CPU time	71.24 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:29:33 PM PDT 24
Peak memory	263808 kb
Host	smart-65e8ad42-2d0a-43c5-bc6b-7796a2d16874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248600903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.248600903
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.1280334424
Short name	T980
Test name
Test status
Simulation time	141866500 ps
CPU time	124.31 seconds
Started	Jul 10 07:28:12 PM PDT 24
Finished	Jul 10 07:30:17 PM PDT 24
Peak memory	276492 kb
Host	smart-8e6eba31-15e2-48cc-aa94-5a6ddec57042
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280334424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1280334424
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.2809030496
Short name	T521
Test name
Test status
Simulation time	78641100 ps
CPU time	15.87 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:28:40 PM PDT 24
Peak memory	284300 kb
Host	smart-ed7ee2e0-0b70-4e80-9f51-f5c08bba5eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809030496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2809030496
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.4030164067
Short name	T43
Test name
Test status
Simulation time	16130200 ps
CPU time	21.86 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	273592 kb
Host	smart-be5717a6-cca1-4c6a-8358-4f4d020e9210
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030164067 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.4030164067
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2444196401
Short name	T509
Test name
Test status
Simulation time	14811068300 ps
CPU time	204.23 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:31:50 PM PDT 24
Peak memory	260948 kb
Host	smart-d2db551d-0a82-4889-9298-4d449bdaf105
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444196401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.2444196401
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.2682534073
Short name	T735
Test name
Test status
Simulation time	1615634300 ps
CPU time	197.73 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:31:42 PM PDT 24
Peak memory	291548 kb
Host	smart-13372c4b-7372-4cdc-ab76-330c0276a67f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682534073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.2682534073
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1630933785
Short name	T691
Test name
Test status
Simulation time	24484402700 ps
CPU time	265.38 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:32:50 PM PDT 24
Peak memory	291100 kb
Host	smart-d53f6960-1b2c-4183-842f-6bdab715e7c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630933785 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1630933785
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.329373915
Short name	T161
Test name
Test status
Simulation time	170325200 ps
CPU time	112.16 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:30:16 PM PDT 24
Peak memory	260400 kb
Host	smart-ee392881-1acb-40fa-90e6-35fc2c6b2b16
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329373915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot p_reset.329373915
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.3293469644
Short name	T580
Test name
Test status
Simulation time	8308001200 ps
CPU time	145.83 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:30:49 PM PDT 24
Peak memory	259992 kb
Host	smart-150db58c-0a1f-4d4c-91da-9af3ff6c5433
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293469644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 26.flash_ctrl_prog_reset.3293469644
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.2172847111
Short name	T1019
Test name
Test status
Simulation time	28122900 ps
CPU time	31.66 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:28:55 PM PDT 24
Peak memory	275876 kb
Host	smart-5c48f22a-4d6b-4fa4-9d45-c5961e3285cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172847111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.2172847111
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3385791194
Short name	T1032
Test name
Test status
Simulation time	174350900 ps
CPU time	28.4 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	268496 kb
Host	smart-5a7c1709-c338-479a-89e4-05ae223bcfa8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385791194 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3385791194
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.3972099530
Short name	T729
Test name
Test status
Simulation time	860625600 ps
CPU time	75.66 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:29:41 PM PDT 24
Peak memory	264596 kb
Host	smart-00a09dfe-a122-4379-9e0f-24e388a847cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972099530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3972099530
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.569907193
Short name	T878
Test name
Test status
Simulation time	241098000 ps
CPU time	124.76 seconds
Started	Jul 10 07:28:21 PM PDT 24
Finished	Jul 10 07:30:27 PM PDT 24
Peak memory	276664 kb
Host	smart-3d3bcedc-669d-4de8-8b7f-83dbefeb4c10
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569907193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.569907193
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.3202555486
Short name	T572
Test name
Test status
Simulation time	222757800 ps
CPU time	13.65 seconds
Started	Jul 10 07:28:34 PM PDT 24
Finished	Jul 10 07:28:48 PM PDT 24
Peak memory	265224 kb
Host	smart-46bcae5e-4377-4a22-89fe-7f5d6963581b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202555486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 3202555486
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.3538839757
Short name	T554
Test name
Test status
Simulation time	17354600 ps
CPU time	13.53 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:28:38 PM PDT 24
Peak memory	274876 kb
Host	smart-66ed9f1f-11e2-4ff8-abdc-01480d210554
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538839757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3538839757
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.3063522575
Short name	T427
Test name
Test status
Simulation time	26931500 ps
CPU time	22.54 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:28:46 PM PDT 24
Peak memory	273612 kb
Host	smart-0a7d4f97-3f61-425b-93d2-8fd2e8adad93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063522575 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.3063522575
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3074934969
Short name	T639
Test name
Test status
Simulation time	6116298000 ps
CPU time	99.66 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:30:03 PM PDT 24
Peak memory	262804 kb
Host	smart-12c492fc-8e08-4d0c-a290-f30b2cb1ca97
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074934969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ hw_sec_otp.3074934969
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2942709477
Short name	T588
Test name
Test status
Simulation time	4458195100 ps
CPU time	132.16 seconds
Started	Jul 10 07:28:23 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	292800 kb
Host	smart-43dc8d43-bbc2-4e8f-94fb-cfa3d38ffb5c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942709477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2942709477
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3096740221
Short name	T575
Test name
Test status
Simulation time	20951686700 ps
CPU time	150.38 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:30:55 PM PDT 24
Peak memory	292996 kb
Host	smart-48b84d6d-038a-47bb-a81d-1a454fde3548
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096740221 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.3096740221
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.112975548
Short name	T712
Test name
Test status
Simulation time	205637800 ps
CPU time	133.81 seconds
Started	Jul 10 07:28:24 PM PDT 24
Finished	Jul 10 07:30:39 PM PDT 24
Peak memory	260104 kb
Host	smart-9853da7e-f190-43c8-8f9a-664513ed5011
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112975548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot p_reset.112975548
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.614431452
Short name	T906
Test name
Test status
Simulation time	4743512100 ps
CPU time	243.13 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:32:26 PM PDT 24
Peak memory	265168 kb
Host	smart-cbf5fd42-71c7-4d74-a4ab-fca2ed47ab4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614431452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.flash_ctrl_prog_reset.614431452
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.1299715466
Short name	T771
Test name
Test status
Simulation time	30582100 ps
CPU time	31.88 seconds
Started	Jul 10 07:28:25 PM PDT 24
Finished	Jul 10 07:28:58 PM PDT 24
Peak memory	275668 kb
Host	smart-5d557584-e724-4a27-891a-08c7cf161eaa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299715466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.1299715466
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.3204752527
Short name	T662
Test name
Test status
Simulation time	1075012100 ps
CPU time	67.75 seconds
Started	Jul 10 07:28:25 PM PDT 24
Finished	Jul 10 07:29:33 PM PDT 24
Peak memory	263832 kb
Host	smart-a224999a-6bad-4b39-8dbb-8f04e6597655
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204752527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3204752527
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.4125226267
Short name	T1007
Test name
Test status
Simulation time	24616200 ps
CPU time	146.21 seconds
Started	Jul 10 07:28:22 PM PDT 24
Finished	Jul 10 07:30:50 PM PDT 24
Peak memory	279292 kb
Host	smart-5fea8e00-33a6-4286-acb7-de015cd41e7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4125226267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.4125226267
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.954602343
Short name	T807
Test name
Test status
Simulation time	108030200 ps
CPU time	14.21 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	264892 kb
Host	smart-2f53d313-f314-483e-ad66-5d6449baa7e3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954602343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.954602343
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.1942539762
Short name	T431
Test name
Test status
Simulation time	17246400 ps
CPU time	15.76 seconds
Started	Jul 10 07:28:36 PM PDT 24
Finished	Jul 10 07:28:52 PM PDT 24
Peak memory	275044 kb
Host	smart-b4ab3a5d-c015-4141-8e5d-d1ebb553e385
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942539762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1942539762
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.3973693654
Short name	T915
Test name
Test status
Simulation time	13751700 ps
CPU time	20.68 seconds
Started	Jul 10 07:28:35 PM PDT 24
Finished	Jul 10 07:28:57 PM PDT 24
Peak memory	273652 kb
Host	smart-9e1c4fa4-4b94-4d77-8108-320d33dbc83d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973693654 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.3973693654
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1846275953
Short name	T301
Test name
Test status
Simulation time	7716466600 ps
CPU time	219.61 seconds
Started	Jul 10 07:28:36 PM PDT 24
Finished	Jul 10 07:32:17 PM PDT 24
Peak memory	263360 kb
Host	smart-c0cdb293-31ed-4d72-aca8-8243dbf82633
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846275953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.1846275953
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.3795747705
Short name	T967
Test name
Test status
Simulation time	6602680800 ps
CPU time	243.61 seconds
Started	Jul 10 07:28:34 PM PDT 24
Finished	Jul 10 07:32:39 PM PDT 24
Peak memory	291504 kb
Host	smart-fd2b5406-8613-485e-a088-af4288da0e70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795747705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.3795747705
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3717024379
Short name	T407
Test name
Test status
Simulation time	23640378300 ps
CPU time	159.63 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:31:12 PM PDT 24
Peak memory	293136 kb
Host	smart-9562c5a6-dc39-4b29-b056-47c5034c66b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717024379 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3717024379
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.1752758167
Short name	T348
Test name
Test status
Simulation time	137639800 ps
CPU time	132.84 seconds
Started	Jul 10 07:28:35 PM PDT 24
Finished	Jul 10 07:30:49 PM PDT 24
Peak memory	265064 kb
Host	smart-ff58b951-3e2b-40c5-bacc-755bb1c9dfed
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752758167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.1752758167
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.2457206573
Short name	T398
Test name
Test status
Simulation time	22773300 ps
CPU time	13.54 seconds
Started	Jul 10 07:28:40 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	259772 kb
Host	smart-af4d77fe-2e13-48e5-9cae-03f5095593fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457206573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.2457206573
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.1084996904
Short name	T945
Test name
Test status
Simulation time	35041500 ps
CPU time	28.38 seconds
Started	Jul 10 07:28:39 PM PDT 24
Finished	Jul 10 07:29:09 PM PDT 24
Peak memory	275676 kb
Host	smart-63d47065-c050-4617-9c3a-53aa40ffcfcc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084996904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.1084996904
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3724501497
Short name	T135
Test name
Test status
Simulation time	90710300 ps
CPU time	30.81 seconds
Started	Jul 10 07:28:35 PM PDT 24
Finished	Jul 10 07:29:07 PM PDT 24
Peak memory	275672 kb
Host	smart-c427330b-4bf3-40b2-97d2-3529ea51516e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724501497 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3724501497
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.1799227879
Short name	T1028
Test name
Test status
Simulation time	3255449800 ps
CPU time	72.82 seconds
Started	Jul 10 07:28:33 PM PDT 24
Finished	Jul 10 07:29:46 PM PDT 24
Peak memory	263152 kb
Host	smart-72aba98f-e633-4c79-bb96-85a09510e255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799227879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1799227879
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.2371581027
Short name	T1084
Test name
Test status
Simulation time	79586100 ps
CPU time	95.11 seconds
Started	Jul 10 07:28:40 PM PDT 24
Finished	Jul 10 07:30:16 PM PDT 24
Peak memory	276012 kb
Host	smart-1c742054-f108-44b8-a937-b60c04d071ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371581027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2371581027
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.599765768
Short name	T690
Test name
Test status
Simulation time	63318300 ps
CPU time	13.47 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:28:46 PM PDT 24
Peak memory	265276 kb
Host	smart-6ec90df8-d9dc-4f69-8a1e-d8a6aea86751
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599765768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.599765768
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.2356722518
Short name	T507
Test name
Test status
Simulation time	54102200 ps
CPU time	16.23 seconds
Started	Jul 10 07:28:33 PM PDT 24
Finished	Jul 10 07:28:50 PM PDT 24
Peak memory	284372 kb
Host	smart-91bc812e-7444-4caa-9fcb-b4becc4178ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356722518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2356722518
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.2597175944
Short name	T1093
Test name
Test status
Simulation time	39464900 ps
CPU time	21.52 seconds
Started	Jul 10 07:28:34 PM PDT 24
Finished	Jul 10 07:28:56 PM PDT 24
Peak memory	273616 kb
Host	smart-35924909-6d32-4ed7-9b55-dfb01963ab2f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597175944 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.2597175944
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1504188166
Short name	T928
Test name
Test status
Simulation time	15911185700 ps
CPU time	165.75 seconds
Started	Jul 10 07:28:33 PM PDT 24
Finished	Jul 10 07:31:20 PM PDT 24
Peak memory	262104 kb
Host	smart-24bf68fc-9e4f-40bd-a741-b17536c8b4c9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504188166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.1504188166
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.4210294494
Short name	T1057
Test name
Test status
Simulation time	11685872700 ps
CPU time	281 seconds
Started	Jul 10 07:28:40 PM PDT 24
Finished	Jul 10 07:33:22 PM PDT 24
Peak memory	284964 kb
Host	smart-3387f250-850a-41e9-84ca-d61d1405a8ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210294494 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.4210294494
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.985689821
Short name	T830
Test name
Test status
Simulation time	133554400 ps
CPU time	110.17 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:30:23 PM PDT 24
Peak memory	261116 kb
Host	smart-e41b6135-8285-43ee-ba4f-ef5a0b55fd46
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985689821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot p_reset.985689821
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.2692858687
Short name	T1022
Test name
Test status
Simulation time	62073600 ps
CPU time	13.93 seconds
Started	Jul 10 07:28:40 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	259724 kb
Host	smart-b81f020e-e58e-4af5-b10c-88bd061c62e5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692858687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.flash_ctrl_prog_reset.2692858687
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict.595311811
Short name	T773
Test name
Test status
Simulation time	30018900 ps
CPU time	28.37 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:29:02 PM PDT 24
Peak memory	275696 kb
Host	smart-2dec407b-c1bf-4830-91c5-7d5a1928f672
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595311811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_rw_evict.595311811
Directory	/workspace/29.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1937926423
Short name	T740
Test name
Test status
Simulation time	83712600 ps
CPU time	31.07 seconds
Started	Jul 10 07:28:34 PM PDT 24
Finished	Jul 10 07:29:06 PM PDT 24
Peak memory	275728 kb
Host	smart-d31dd967-216e-4b32-bedc-51385647896c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937926423 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1937926423
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.4162841701
Short name	T607
Test name
Test status
Simulation time	2250575100 ps
CPU time	57.93 seconds
Started	Jul 10 07:28:39 PM PDT 24
Finished	Jul 10 07:29:38 PM PDT 24
Peak memory	263736 kb
Host	smart-ba1a212d-221f-403f-a2a7-a8f1197b49cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162841701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.4162841701
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.290245448
Short name	T578
Test name
Test status
Simulation time	92275100 ps
CPU time	120.29 seconds
Started	Jul 10 07:28:33 PM PDT 24
Finished	Jul 10 07:30:34 PM PDT 24
Peak memory	276412 kb
Host	smart-8a75cfc9-640a-49c2-ad6e-39e51da2973d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290245448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.290245448
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.2804579363
Short name	T1101
Test name
Test status
Simulation time	102601400 ps
CPU time	13.63 seconds
Started	Jul 10 07:24:44 PM PDT 24
Finished	Jul 10 07:24:59 PM PDT 24
Peak memory	258272 kb
Host	smart-829a6039-1801-45a1-8065-259db443e633
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804579363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2 804579363
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.3428366768
Short name	T332
Test name
Test status
Simulation time	23660600 ps
CPU time	13.71 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:24:55 PM PDT 24
Peak memory	265048 kb
Host	smart-fba662b2-3850-418a-b187-2faa7d0ede8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428366768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.3428366768
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.4172105914
Short name	T402
Test name
Test status
Simulation time	15288400 ps
CPU time	15.76 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:25:05 PM PDT 24
Peak memory	284416 kb
Host	smart-9ecba425-895a-4aa0-aff3-421470f039c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172105914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.4172105914
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.1959530618
Short name	T168
Test name
Test status
Simulation time	144185700 ps
CPU time	22 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:25:20 PM PDT 24
Peak memory	265540 kb
Host	smart-6f1c1f12-24d5-4fb3-ba78-9e3eade8cf4a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959530618 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.1959530618
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.231901788
Short name	T73
Test name
Test status
Simulation time	15732830400 ps
CPU time	438.63 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:32:00 PM PDT 24
Peak memory	263480 kb
Host	smart-d3c4430f-29c0-4137-b642-b66e9ad88821
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=231901788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.231901788
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.1742508770
Short name	T280
Test name
Test status
Simulation time	19323119600 ps
CPU time	2285.8 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 08:03:02 PM PDT 24
Peak memory	264496 kb
Host	smart-e38d2bf6-cb2c-4095-abae-3f661750b2bd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1742508770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1742508770
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.1780664239
Short name	T281
Test name
Test status
Simulation time	1524104100 ps
CPU time	988.88 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:41:16 PM PDT 24
Peak memory	273428 kb
Host	smart-12ec5214-c92e-4003-98bd-12dd1132528f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780664239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1780664239
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.1706813082
Short name	T439
Test name
Test status
Simulation time	639979100 ps
CPU time	23.56 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:25:10 PM PDT 24
Peak memory	262620 kb
Host	smart-66c172bb-45da-4e91-b40d-d57aeb61a835
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706813082 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1706813082
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.495560842
Short name	T724
Test name
Test status
Simulation time	630197100 ps
CPU time	37.53 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:25:17 PM PDT 24
Peak memory	265364 kb
Host	smart-5044e484-e93d-4025-a5c0-2ffc3e47a847
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495560842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_fs_sup.495560842
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.1996673203
Short name	T141
Test name
Test status
Simulation time	180973957600 ps
CPU time	4569.82 seconds
Started	Jul 10 07:24:33 PM PDT 24
Finished	Jul 10 08:40:45 PM PDT 24
Peak memory	263072 kb
Host	smart-c641f481-efe6-4859-8adc-8f5064505553
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996673203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.1996673203
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2065103970
Short name	T194
Test name
Test status
Simulation time	280918160000 ps
CPU time	2560 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 08:07:15 PM PDT 24
Peak memory	265324 kb
Host	smart-84594ec6-d470-4d75-bf77-0397c79d6ff8
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065103970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.2065103970
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.470034603
Short name	T715
Test name
Test status
Simulation time	70563700 ps
CPU time	90.77 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:26:23 PM PDT 24
Peak memory	265216 kb
Host	smart-c4d75336-aac7-43c2-802c-4de8bae5eb5f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=470034603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.470034603
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2927244834
Short name	T1027
Test name
Test status
Simulation time	10022657000 ps
CPU time	71.76 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:25:58 PM PDT 24
Peak memory	311360 kb
Host	smart-062836ae-56a8-4f97-83c1-822107c1166b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927244834 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2927244834
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1842097190
Short name	T711
Test name
Test status
Simulation time	99750900 ps
CPU time	13.59 seconds
Started	Jul 10 07:24:59 PM PDT 24
Finished	Jul 10 07:25:17 PM PDT 24
Peak memory	258556 kb
Host	smart-90546584-d06c-49bb-acad-8695d647ea95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842097190 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1842097190
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.1490324949
Short name	T957
Test name
Test status
Simulation time	60127304100 ps
CPU time	891.37 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:39:44 PM PDT 24
Peak memory	260988 kb
Host	smart-bec1cc63-0d9d-49fe-900f-5c0ca481ac82
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490324949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.1490324949
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1550955123
Short name	T449
Test name
Test status
Simulation time	13297493100 ps
CPU time	119.75 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:26:56 PM PDT 24
Peak memory	260920 kb
Host	smart-8aaa9637-6256-4170-83b3-d45ce29ffbb0
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550955123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.1550955123
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_integrity.4248070188
Short name	T231
Test name
Test status
Simulation time	14107351700 ps
CPU time	731.59 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:37:04 PM PDT 24
Peak memory	327500 kb
Host	smart-24889b02-ab1e-4206-94ea-50d304ca3a7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248070188 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_integrity.4248070188
Directory	/workspace/3.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.2502070453
Short name	T1054
Test name
Test status
Simulation time	4152513800 ps
CPU time	233.68 seconds
Started	Jul 10 07:24:34 PM PDT 24
Finished	Jul 10 07:28:29 PM PDT 24
Peak memory	291500 kb
Host	smart-161111d5-21c2-4c9c-a2a0-de0eaffed197
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502070453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.2502070453
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1305405417
Short name	T312
Test name
Test status
Simulation time	46563654900 ps
CPU time	287.81 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:29:28 PM PDT 24
Peak memory	291988 kb
Host	smart-8a37c1d2-dcd7-4e0d-969f-1fcdbf870595
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305405417 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1305405417
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.1210202540
Short name	T453
Test name
Test status
Simulation time	2256905300 ps
CPU time	67.45 seconds
Started	Jul 10 07:24:42 PM PDT 24
Finished	Jul 10 07:25:50 PM PDT 24
Peak memory	265264 kb
Host	smart-47afed10-c9ae-4e91-99f2-cf745fbd7ddd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210202540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.1210202540
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.49028572
Short name	T725
Test name
Test status
Simulation time	125695656100 ps
CPU time	240.1 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:28:53 PM PDT 24
Peak memory	265192 kb
Host	smart-7cc05a52-8242-40b3-8d0d-f17fd1cbdec0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490 28572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.49028572
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.3118333515
Short name	T378
Test name
Test status
Simulation time	4952163900 ps
CPU time	67.02 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:25:47 PM PDT 24
Peak memory	263792 kb
Host	smart-c844a499-1c5c-4c52-a1d6-641874ab0bea
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118333515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3118333515
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3334852693
Short name	T278
Test name
Test status
Simulation time	26155500 ps
CPU time	13.37 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:24:52 PM PDT 24
Peak memory	265016 kb
Host	smart-f9a8911c-b5ef-4110-801a-978cff60e99a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334852693 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3334852693
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.99521011
Short name	T95
Test name
Test status
Simulation time	2660752000 ps
CPU time	75.09 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:26:11 PM PDT 24
Peak memory	260536 kb
Host	smart-d9f341de-be2f-4fb7-ac39-497a74fce4e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99521011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.99521011
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.2247249539
Short name	T140
Test name
Test status
Simulation time	20341137200 ps
CPU time	266.28 seconds
Started	Jul 10 07:24:40 PM PDT 24
Finished	Jul 10 07:29:08 PM PDT 24
Peak memory	274804 kb
Host	smart-364d2cb4-e21b-4cb2-81da-555d3e67a72b
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247249539 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.2247249539
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.3059408615
Short name	T152
Test name
Test status
Simulation time	109673200 ps
CPU time	132.35 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:27:09 PM PDT 24
Peak memory	260168 kb
Host	smart-787c0ef6-f334-48bb-9b58-13c91558e65b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059408615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.3059408615
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.573085580
Short name	T42
Test name
Test status
Simulation time	996548000 ps
CPU time	145.19 seconds
Started	Jul 10 07:24:39 PM PDT 24
Finished	Jul 10 07:27:06 PM PDT 24
Peak memory	290332 kb
Host	smart-146d6e74-1cb4-4f0c-8acf-530048252378
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573085580 -assert nop ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.573085580
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.3755591590
Short name	T822
Test name
Test status
Simulation time	7157744600 ps
CPU time	366.62 seconds
Started	Jul 10 07:24:43 PM PDT 24
Finished	Jul 10 07:30:50 PM PDT 24
Peak memory	263272 kb
Host	smart-cec8efe3-2658-46d0-add7-e3918ee2484e
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3755591590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3755591590
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.4164992027
Short name	T399
Test name
Test status
Simulation time	14658500 ps
CPU time	14.23 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:24:54 PM PDT 24
Peak memory	265088 kb
Host	smart-82772b99-3bdb-416c-b6c2-75f8c2cc99c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164992027 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.4164992027
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.2011578809
Short name	T486
Test name
Test status
Simulation time	34986900 ps
CPU time	13.71 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:24:53 PM PDT 24
Peak memory	259044 kb
Host	smart-0aea5379-276e-4b20-bbf8-ed2a9ab1848d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011578809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 3.flash_ctrl_prog_reset.2011578809
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.1920252042
Short name	T922
Test name
Test status
Simulation time	202545300 ps
CPU time	1223.34 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:45:02 PM PDT 24
Peak memory	286648 kb
Host	smart-88072cee-42dc-4d73-a2f7-a919ef936602
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920252042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1920252042
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.464245651
Short name	T644
Test name
Test status
Simulation time	5735807800 ps
CPU time	142.01 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:27:17 PM PDT 24
Peak memory	262800 kb
Host	smart-d4c25c75-aff8-4ace-8df9-ba27c9624ba2
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=464245651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.464245651
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.342936560
Short name	T380
Test name
Test status
Simulation time	76047000 ps
CPU time	31.54 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:25:25 PM PDT 24
Peak memory	275688 kb
Host	smart-86716ea6-e7f7-4185-96fb-4aaa8f8fbe4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342936560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_re_evict.342936560
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.118282997
Short name	T191
Test name
Test status
Simulation time	19385200 ps
CPU time	21.89 seconds
Started	Jul 10 07:24:37 PM PDT 24
Finished	Jul 10 07:25:01 PM PDT 24
Peak memory	265404 kb
Host	smart-7e28d9bd-189f-4141-9631-b648dcb2d58e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118282997 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.118282997
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3431618271
Short name	T767
Test name
Test status
Simulation time	76812900 ps
CPU time	21.37 seconds
Started	Jul 10 07:24:42 PM PDT 24
Finished	Jul 10 07:25:04 PM PDT 24
Peak memory	265076 kb
Host	smart-5f1b313f-c87e-4e05-aa21-0735cf3cf874
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431618271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_read_word_sweep_serr.3431618271
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.2930317579
Short name	T907
Test name
Test status
Simulation time	9491895100 ps
CPU time	122.34 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	297416 kb
Host	smart-502ea9d7-ed53-44d0-8d75-b2f7071a7079
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930317579 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_ro.2930317579
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.2466655206
Short name	T918
Test name
Test status
Simulation time	2673333100 ps
CPU time	153.9 seconds
Started	Jul 10 07:24:41 PM PDT 24
Finished	Jul 10 07:27:16 PM PDT 24
Peak memory	283032 kb
Host	smart-7ee12cac-4886-4753-bf74-a961cfe95fe9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2466655206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2466655206
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.3567351788
Short name	T263
Test name
Test status
Simulation time	654345600 ps
CPU time	130.62 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:26:47 PM PDT 24
Peak memory	290012 kb
Host	smart-82c24c7e-36bb-4046-877f-c2e3ae12babf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567351788 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.3567351788
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.1666739101
Short name	T701
Test name
Test status
Simulation time	3907115500 ps
CPU time	519.97 seconds
Started	Jul 10 07:24:39 PM PDT 24
Finished	Jul 10 07:33:21 PM PDT 24
Peak memory	310028 kb
Host	smart-9531cb48-6f69-4a8f-bc3c-758a90d3d820
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666739101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.1666739101
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.1107039573
Short name	T741
Test name
Test status
Simulation time	17095443100 ps
CPU time	688.9 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:36:18 PM PDT 24
Peak memory	341476 kb
Host	smart-ae8be5e8-29bf-442e-9c11-727adac0f042
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107039573 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_rw_derr.1107039573
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.1806261563
Short name	T681
Test name
Test status
Simulation time	41841500 ps
CPU time	30.3 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:25:18 PM PDT 24
Peak memory	275732 kb
Host	smart-1e4218ec-3c24-414c-8407-5b43abc6f36c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806261563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_rw_evict.1806261563
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1827844235
Short name	T440
Test name
Test status
Simulation time	96627500 ps
CPU time	28.56 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:26 PM PDT 24
Peak memory	275712 kb
Host	smart-af54e503-2fec-40ed-8369-62f859d91962
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827844235 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1827844235
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.2786998850
Short name	T636
Test name
Test status
Simulation time	4394267400 ps
CPU time	526.88 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:33:38 PM PDT 24
Peak memory	320984 kb
Host	smart-09ef81a0-6e72-40e7-97f6-7c4f93a848b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786998850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s err.2786998850
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.4207689960
Short name	T62
Test name
Test status
Simulation time	1044569700 ps
CPU time	5045.27 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 08:49:02 PM PDT 24
Peak memory	285372 kb
Host	smart-081165c9-d7cb-473a-a0fb-bab12bf9ad6d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207689960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4207689960
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.419262493
Short name	T359
Test name
Test status
Simulation time	2336978900 ps
CPU time	78.75 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:26:14 PM PDT 24
Peak memory	263668 kb
Host	smart-aac0472e-fe45-4d5f-a0d6-fe13f72c0f85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419262493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.419262493
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.4153057467
Short name	T784
Test name
Test status
Simulation time	3018814600 ps
CPU time	83.28 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:26:20 PM PDT 24
Peak memory	265432 kb
Host	smart-2930cc2b-50f5-47b8-af27-3bf450288d76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153057467 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.4153057467
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.2650584068
Short name	T20
Test name
Test status
Simulation time	2393687500 ps
CPU time	70.74 seconds
Started	Jul 10 07:24:36 PM PDT 24
Finished	Jul 10 07:25:48 PM PDT 24
Peak memory	276444 kb
Host	smart-3cebba70-23dc-4176-9fd0-80422fb8f7f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650584068 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_serr_counter.2650584068
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.2507603902
Short name	T833
Test name
Test status
Simulation time	16105700 ps
CPU time	100.02 seconds
Started	Jul 10 07:24:35 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	277292 kb
Host	smart-35cf4f68-df76-4cbc-b354-9f999cceae58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507603902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2507603902
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.1672023685
Short name	T1000
Test name
Test status
Simulation time	27159100 ps
CPU time	26.95 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:25:15 PM PDT 24
Peak memory	259640 kb
Host	smart-3c9d67f5-bbd7-497b-b3e2-3e9de4a354bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672023685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1672023685
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.3571461930
Short name	T520
Test name
Test status
Simulation time	312653400 ps
CPU time	629.83 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:35:09 PM PDT 24
Peak memory	280428 kb
Host	smart-1e128a51-82a4-4529-b367-30bc3e38c57d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571461930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.3571461930
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.555322539
Short name	T1061
Test name
Test status
Simulation time	145039300 ps
CPU time	26.65 seconds
Started	Jul 10 07:24:38 PM PDT 24
Finished	Jul 10 07:25:07 PM PDT 24
Peak memory	262384 kb
Host	smart-5582f2fe-24b3-4040-905c-84062f9c0316
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555322539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.555322539
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.1699188474
Short name	T451
Test name
Test status
Simulation time	8771948300 ps
CPU time	153.91 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:27:25 PM PDT 24
Peak memory	265304 kb
Host	smart-ba53fd1e-6a10-4c04-b5cf-975666e2d0d6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699188474 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.1699188474
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.2125567785
Short name	T884
Test name
Test status
Simulation time	104973800 ps
CPU time	14.1 seconds
Started	Jul 10 07:28:43 PM PDT 24
Finished	Jul 10 07:28:58 PM PDT 24
Peak memory	265184 kb
Host	smart-c0906a3a-4be8-40cb-ac22-3ceba67d3cb5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125567785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test. 2125567785
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.3734609194
Short name	T786
Test name
Test status
Simulation time	18702800 ps
CPU time	16.69 seconds
Started	Jul 10 07:28:44 PM PDT 24
Finished	Jul 10 07:29:01 PM PDT 24
Peak memory	284348 kb
Host	smart-87cd5872-77cc-4f94-b6b8-272314686fc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734609194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3734609194
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.3458228700
Short name	T355
Test name
Test status
Simulation time	10946400 ps
CPU time	20.7 seconds
Started	Jul 10 07:28:45 PM PDT 24
Finished	Jul 10 07:29:07 PM PDT 24
Peak memory	273624 kb
Host	smart-c78f916b-17db-482b-abf1-68a737ac42ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458228700 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.3458228700
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2381136288
Short name	T295
Test name
Test status
Simulation time	13221154600 ps
CPU time	100.59 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:30:14 PM PDT 24
Peak memory	263352 kb
Host	smart-24f0477c-ad1a-40f2-98e8-c4c6cd9878a1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381136288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ hw_sec_otp.2381136288
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.1399551782
Short name	T695
Test name
Test status
Simulation time	1317433500 ps
CPU time	143.54 seconds
Started	Jul 10 07:28:44 PM PDT 24
Finished	Jul 10 07:31:08 PM PDT 24
Peak memory	294680 kb
Host	smart-c7db1149-21db-49d3-a55e-e4250d97f9bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399551782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla sh_ctrl_intr_rd.1399551782
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.565395691
Short name	T421
Test name
Test status
Simulation time	5922818800 ps
CPU time	127.4 seconds
Started	Jul 10 07:28:45 PM PDT 24
Finished	Jul 10 07:30:54 PM PDT 24
Peak memory	293052 kb
Host	smart-70519e78-de22-4a58-8d8c-56c62e350b7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565395691 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.565395691
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.3613321344
Short name	T951
Test name
Test status
Simulation time	113463900 ps
CPU time	132.4 seconds
Started	Jul 10 07:28:45 PM PDT 24
Finished	Jul 10 07:30:58 PM PDT 24
Peak memory	259992 kb
Host	smart-6f785cd8-ab1d-4422-82d7-16e3161de41a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613321344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o tp_reset.3613321344
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.3278339617
Short name	T389
Test name
Test status
Simulation time	31199200 ps
CPU time	29.27 seconds
Started	Jul 10 07:28:44 PM PDT 24
Finished	Jul 10 07:29:14 PM PDT 24
Peak memory	268592 kb
Host	smart-fb20640c-9feb-4857-b366-aa51b3f83115
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278339617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl ash_ctrl_rw_evict.3278339617
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3598975068
Short name	T838
Test name
Test status
Simulation time	29037600 ps
CPU time	31.25 seconds
Started	Jul 10 07:28:46 PM PDT 24
Finished	Jul 10 07:29:18 PM PDT 24
Peak memory	275656 kb
Host	smart-b9908c38-b369-45cd-b719-66e38e3d4af2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598975068 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3598975068
Directory	/workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.4007693345
Short name	T369
Test name
Test status
Simulation time	7111716200 ps
CPU time	68.77 seconds
Started	Jul 10 07:28:42 PM PDT 24
Finished	Jul 10 07:29:51 PM PDT 24
Peak memory	263196 kb
Host	smart-20bcb00d-74a5-4f60-8e9f-0daaf6c37612
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007693345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.4007693345
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.456269239
Short name	T39
Test name
Test status
Simulation time	75979700 ps
CPU time	123.42 seconds
Started	Jul 10 07:28:32 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	277920 kb
Host	smart-ff67b240-103c-411e-a5be-8d4b5a1f346d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456269239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.456269239
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.2021761072
Short name	T524
Test name
Test status
Simulation time	77017200 ps
CPU time	13.67 seconds
Started	Jul 10 07:28:52 PM PDT 24
Finished	Jul 10 07:29:07 PM PDT 24
Peak memory	265308 kb
Host	smart-75df98d0-74be-467b-a453-5a1ee2ab90eb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021761072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 2021761072
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.3222210094
Short name	T487
Test name
Test status
Simulation time	26693400 ps
CPU time	15.84 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:29:10 PM PDT 24
Peak memory	275004 kb
Host	smart-6e5b3548-42c3-4114-907d-98da1552275f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222210094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3222210094
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.742987221
Short name	T849
Test name
Test status
Simulation time	16884500 ps
CPU time	22.12 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:29:16 PM PDT 24
Peak memory	273552 kb
Host	smart-3987765c-54b8-4bda-82c9-d996165c303e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742987221 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.742987221
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.42082533
Short name	T862
Test name
Test status
Simulation time	4180448200 ps
CPU time	129.26 seconds
Started	Jul 10 07:28:43 PM PDT 24
Finished	Jul 10 07:30:53 PM PDT 24
Peak memory	262812 kb
Host	smart-845e5d7a-c1d6-47f1-b6ea-d707eab1273a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw _sec_otp.42082533
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.1880005953
Short name	T581
Test name
Test status
Simulation time	2441806000 ps
CPU time	145.81 seconds
Started	Jul 10 07:28:42 PM PDT 24
Finished	Jul 10 07:31:09 PM PDT 24
Peak memory	291532 kb
Host	smart-2479a31a-2cf2-468a-b656-62688ac2338a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880005953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.1880005953
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3323582438
Short name	T460
Test name
Test status
Simulation time	51704297300 ps
CPU time	336.64 seconds
Started	Jul 10 07:28:45 PM PDT 24
Finished	Jul 10 07:34:23 PM PDT 24
Peak memory	284856 kb
Host	smart-55d9a0ec-6578-4c03-9251-493156bc9c1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323582438 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3323582438
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.3960275847
Short name	T166
Test name
Test status
Simulation time	45000700 ps
CPU time	109.68 seconds
Started	Jul 10 07:28:45 PM PDT 24
Finished	Jul 10 07:30:35 PM PDT 24
Peak memory	260408 kb
Host	smart-0ba3939a-b980-4b2b-89a8-900c7ca5e78c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960275847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.3960275847
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.243317486
Short name	T958
Test name
Test status
Simulation time	7114428700 ps
CPU time	74.79 seconds
Started	Jul 10 07:28:58 PM PDT 24
Finished	Jul 10 07:30:14 PM PDT 24
Peak memory	263112 kb
Host	smart-773500a5-8e35-46ca-8aab-7160a10cd4c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243317486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.243317486
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.2154363239
Short name	T925
Test name
Test status
Simulation time	91501900 ps
CPU time	191.02 seconds
Started	Jul 10 07:28:44 PM PDT 24
Finished	Jul 10 07:31:56 PM PDT 24
Peak memory	277588 kb
Host	smart-b2de9d4e-a57e-49a2-939f-03695959a96f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2154363239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2154363239
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.2444892251
Short name	T522
Test name
Test status
Simulation time	169634500 ps
CPU time	14.07 seconds
Started	Jul 10 07:29:01 PM PDT 24
Finished	Jul 10 07:29:15 PM PDT 24
Peak memory	265324 kb
Host	smart-43c081d3-229c-4884-a53a-af820972fcf0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444892251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 2444892251
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.2555372384
Short name	T693
Test name
Test status
Simulation time	72156100 ps
CPU time	16.01 seconds
Started	Jul 10 07:28:54 PM PDT 24
Finished	Jul 10 07:29:11 PM PDT 24
Peak memory	274980 kb
Host	smart-f7f16edb-5b21-44f0-9699-bcf4db67ad4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555372384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2555372384
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.3319414748
Short name	T790
Test name
Test status
Simulation time	12688600 ps
CPU time	21.79 seconds
Started	Jul 10 07:28:54 PM PDT 24
Finished	Jul 10 07:29:17 PM PDT 24
Peak memory	273652 kb
Host	smart-e7413dd4-c90f-463e-9967-a4588fc699ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319414748 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.3319414748
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1115851218
Short name	T727
Test name
Test status
Simulation time	7804972800 ps
CPU time	70.28 seconds
Started	Jul 10 07:28:59 PM PDT 24
Finished	Jul 10 07:30:10 PM PDT 24
Peak memory	262600 kb
Host	smart-7756e101-5996-4484-8c04-398945b19a89
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115851218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.1115851218
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.3361187691
Short name	T207
Test name
Test status
Simulation time	2014142300 ps
CPU time	153.18 seconds
Started	Jul 10 07:28:52 PM PDT 24
Finished	Jul 10 07:31:26 PM PDT 24
Peak memory	294056 kb
Host	smart-c636bb30-6932-4f58-abf1-b10d9f19700f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361187691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.3361187691
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1618837468
Short name	T309
Test name
Test status
Simulation time	24075963500 ps
CPU time	158.2 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:31:32 PM PDT 24
Peak memory	291504 kb
Host	smart-65c32e1b-d1d6-4e1c-9cfc-2089bd2901a1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618837468 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1618837468
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.1725761349
Short name	T408
Test name
Test status
Simulation time	213633000 ps
CPU time	110.5 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	260048 kb
Host	smart-886d30dd-809d-4624-a2de-510b4faa375c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725761349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o tp_reset.1725761349
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict.1818742747
Short name	T1079
Test name
Test status
Simulation time	107120200 ps
CPU time	31.31 seconds
Started	Jul 10 07:28:55 PM PDT 24
Finished	Jul 10 07:29:26 PM PDT 24
Peak memory	275672 kb
Host	smart-469730cb-f538-4a6c-8f9e-16792deb1ec8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818742747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl ash_ctrl_rw_evict.1818742747
Directory	/workspace/32.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.2802496666
Short name	T989
Test name
Test status
Simulation time	69964300 ps
CPU time	28.87 seconds
Started	Jul 10 07:28:59 PM PDT 24
Finished	Jul 10 07:29:29 PM PDT 24
Peak memory	267556 kb
Host	smart-0286d097-a571-4864-9054-4e85fa766502
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802496666 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2802496666
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.4037042748
Short name	T361
Test name
Test status
Simulation time	1017726500 ps
CPU time	61.8 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:29:55 PM PDT 24
Peak memory	264632 kb
Host	smart-0b4192ff-2f08-4fad-bbef-00704cf15a3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037042748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.4037042748
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.2512915039
Short name	T812
Test name
Test status
Simulation time	238007800 ps
CPU time	72.98 seconds
Started	Jul 10 07:28:52 PM PDT 24
Finished	Jul 10 07:30:05 PM PDT 24
Peak memory	275568 kb
Host	smart-c857d2d1-e858-4bf4-8555-ca2d62772981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512915039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2512915039
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.1056158642
Short name	T454
Test name
Test status
Simulation time	64740900 ps
CPU time	13.65 seconds
Started	Jul 10 07:29:04 PM PDT 24
Finished	Jul 10 07:29:19 PM PDT 24
Peak memory	265176 kb
Host	smart-fe5c64a4-4b5f-4586-8677-2d5b13febe92
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056158642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 1056158642
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.3447473308
Short name	T676
Test name
Test status
Simulation time	41291300 ps
CPU time	13.31 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:29:17 PM PDT 24
Peak memory	274912 kb
Host	smart-2adf1dd1-5e96-4879-aac9-8e2c606b475a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447473308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3447473308
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.874793822
Short name	T1069
Test name
Test status
Simulation time	26821000 ps
CPU time	21.05 seconds
Started	Jul 10 07:29:05 PM PDT 24
Finished	Jul 10 07:29:27 PM PDT 24
Peak memory	273812 kb
Host	smart-8427fe4a-d2fb-4f74-9a52-f5ee925bdf8c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874793822 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.874793822
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4149715204
Short name	T6
Test name
Test status
Simulation time	3889812600 ps
CPU time	113.11 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:30:48 PM PDT 24
Peak memory	260532 kb
Host	smart-98b56dac-700e-4a05-9809-afa32b971a26
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149715204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ hw_sec_otp.4149715204
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.1721252197
Short name	T31
Test name
Test status
Simulation time	2030257400 ps
CPU time	152.91 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:31:37 PM PDT 24
Peak memory	294960 kb
Host	smart-51a58ee9-ca03-4a53-939b-7a3617cd2b3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721252197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.1721252197
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1911601888
Short name	T490
Test name
Test status
Simulation time	11240435600 ps
CPU time	135.16 seconds
Started	Jul 10 07:29:01 PM PDT 24
Finished	Jul 10 07:31:17 PM PDT 24
Peak memory	294088 kb
Host	smart-648f3055-cd29-4445-b3d0-394beecf752d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911601888 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1911601888
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.1209084751
Short name	T108
Test name
Test status
Simulation time	39224000 ps
CPU time	109.71 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:30:54 PM PDT 24
Peak memory	260156 kb
Host	smart-2112bbfe-c8a4-4c49-806f-763cd6ec255c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209084751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.1209084751
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.1522305327
Short name	T530
Test name
Test status
Simulation time	15436823200 ps
CPU time	69.7 seconds
Started	Jul 10 07:29:02 PM PDT 24
Finished	Jul 10 07:30:13 PM PDT 24
Peak memory	262616 kb
Host	smart-d9dd92be-f90e-4d7b-ad5e-658ed2085a62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1522305327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1522305327
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.3805596462
Short name	T1040
Test name
Test status
Simulation time	39397600 ps
CPU time	97.6 seconds
Started	Jul 10 07:28:53 PM PDT 24
Finished	Jul 10 07:30:31 PM PDT 24
Peak memory	276000 kb
Host	smart-f0c2d669-fef2-4ff1-9ce3-453fbd8c3838
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805596462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3805596462
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.2551442296
Short name	T1036
Test name
Test status
Simulation time	347719400 ps
CPU time	14 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:29:18 PM PDT 24
Peak memory	258340 kb
Host	smart-6fc9d969-b456-414f-bc9d-2f9dad7fb358
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551442296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 2551442296
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.3489035686
Short name	T574
Test name
Test status
Simulation time	42318700 ps
CPU time	16.09 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:29:20 PM PDT 24
Peak memory	274976 kb
Host	smart-0244f95f-2f87-434c-9f50-125ff19dd7ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489035686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3489035686
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.1793473546
Short name	T79
Test name
Test status
Simulation time	9903000 ps
CPU time	21.89 seconds
Started	Jul 10 07:29:04 PM PDT 24
Finished	Jul 10 07:29:27 PM PDT 24
Peak memory	273616 kb
Host	smart-34725985-bf10-496f-8365-238a04972c16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793473546 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.1793473546
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.696366478
Short name	T970
Test name
Test status
Simulation time	1782460200 ps
CPU time	144.87 seconds
Started	Jul 10 07:29:04 PM PDT 24
Finished	Jul 10 07:31:29 PM PDT 24
Peak memory	260980 kb
Host	smart-0116dbe6-924e-42c1-a5d1-ae8aafa115b2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696366478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_h w_sec_otp.696366478
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.2866307627
Short name	T306
Test name
Test status
Simulation time	5738956300 ps
CPU time	227.32 seconds
Started	Jul 10 07:29:06 PM PDT 24
Finished	Jul 10 07:32:54 PM PDT 24
Peak memory	291688 kb
Host	smart-57dd95a6-b5cd-4130-8592-6a1a187860b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866307627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.2866307627
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1324319324
Short name	T964
Test name
Test status
Simulation time	5958154300 ps
CPU time	132.93 seconds
Started	Jul 10 07:29:01 PM PDT 24
Finished	Jul 10 07:31:14 PM PDT 24
Peak memory	293004 kb
Host	smart-2b8c6cb8-d055-456c-8d04-3c246e178b13
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324319324 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1324319324
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.1909039189
Short name	T1003
Test name
Test status
Simulation time	36245100 ps
CPU time	129.71 seconds
Started	Jul 10 07:29:02 PM PDT 24
Finished	Jul 10 07:31:12 PM PDT 24
Peak memory	264348 kb
Host	smart-7b73ba7c-bbf6-4e00-88e5-03d978edcf99
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909039189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.1909039189
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict.1639231084
Short name	T260
Test name
Test status
Simulation time	31378200 ps
CPU time	32.64 seconds
Started	Jul 10 07:29:02 PM PDT 24
Finished	Jul 10 07:29:36 PM PDT 24
Peak memory	275660 kb
Host	smart-c45abf82-742e-41d3-bda7-b1f0d24d0b31
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639231084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl ash_ctrl_rw_evict.1639231084
Directory	/workspace/34.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1680426078
Short name	T910
Test name
Test status
Simulation time	30760200 ps
CPU time	28.43 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:29:33 PM PDT 24
Peak memory	268508 kb
Host	smart-8cff5cb1-9886-49a3-aa30-9582df8642d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680426078 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1680426078
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.3474566398
Short name	T372
Test name
Test status
Simulation time	772360300 ps
CPU time	51.75 seconds
Started	Jul 10 07:29:03 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	263228 kb
Host	smart-1c6d0f54-82e6-4d41-bb7d-5f1234f9bd47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474566398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3474566398
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.3390201974
Short name	T770
Test name
Test status
Simulation time	1015846300 ps
CPU time	235.46 seconds
Started	Jul 10 07:29:01 PM PDT 24
Finished	Jul 10 07:32:57 PM PDT 24
Peak memory	281496 kb
Host	smart-d85d00ff-7fb1-430c-baa9-732161899627
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390201974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3390201974
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.2615055424
Short name	T782
Test name
Test status
Simulation time	73758200 ps
CPU time	13.84 seconds
Started	Jul 10 07:29:17 PM PDT 24
Finished	Jul 10 07:29:32 PM PDT 24
Peak memory	258312 kb
Host	smart-a04a18f5-b0ce-4b77-bfeb-462dbca9bd32
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615055424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 2615055424
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.2600607098
Short name	T612
Test name
Test status
Simulation time	25404500 ps
CPU time	16.05 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:29:28 PM PDT 24
Peak memory	274848 kb
Host	smart-176ace82-cc98-49f3-a689-98f7c3585b81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600607098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2600607098
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.3405159749
Short name	T69
Test name
Test status
Simulation time	21555400 ps
CPU time	20.76 seconds
Started	Jul 10 07:29:08 PM PDT 24
Finished	Jul 10 07:29:30 PM PDT 24
Peak memory	273668 kb
Host	smart-482cbbb4-493a-43c2-b6ba-6a2ec2b75580
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405159749 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.3405159749
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3267376749
Short name	T746
Test name
Test status
Simulation time	7493092100 ps
CPU time	167.23 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:31:59 PM PDT 24
Peak memory	263268 kb
Host	smart-f39ac5f1-23e3-4fa4-a8a1-bff17ab93637
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267376749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.3267376749
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.4012008280
Short name	T33
Test name
Test status
Simulation time	2597291300 ps
CPU time	130.44 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:31:24 PM PDT 24
Peak memory	294968 kb
Host	smart-02314739-3b26-4641-8c0a-d78106f20528
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012008280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla sh_ctrl_intr_rd.4012008280
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.2928751343
Short name	T870
Test name
Test status
Simulation time	15704062700 ps
CPU time	146.37 seconds
Started	Jul 10 07:29:10 PM PDT 24
Finished	Jul 10 07:31:37 PM PDT 24
Peak memory	293148 kb
Host	smart-2ac842ec-7d8b-42d4-b621-90970253a0bc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928751343 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.2928751343
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.788143437
Short name	T948
Test name
Test status
Simulation time	40941000 ps
CPU time	109.35 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:31:03 PM PDT 24
Peak memory	261112 kb
Host	smart-1374a745-79e9-430e-9bca-0e08f28187c4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788143437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot p_reset.788143437
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.3432191469
Short name	T392
Test name
Test status
Simulation time	71762300 ps
CPU time	31.05 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:29:44 PM PDT 24
Peak memory	275668 kb
Host	smart-98927924-4e3a-4b73-8570-fa8b7dc828f7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432191469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.3432191469
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1540739608
Short name	T956
Test name
Test status
Simulation time	43142800 ps
CPU time	30.81 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:29:44 PM PDT 24
Peak memory	275704 kb
Host	smart-8241a146-6b9e-497b-a340-c3bd8c16e1b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540739608 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1540739608
Directory	/workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.3294825649
Short name	T978
Test name
Test status
Simulation time	2327012400 ps
CPU time	60.27 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:30:13 PM PDT 24
Peak memory	263092 kb
Host	smart-b35ed54e-a2f3-4127-b872-053f486972ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294825649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3294825649
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.2137009388
Short name	T591
Test name
Test status
Simulation time	98861400 ps
CPU time	146.12 seconds
Started	Jul 10 07:29:02 PM PDT 24
Finished	Jul 10 07:31:29 PM PDT 24
Peak memory	277088 kb
Host	smart-8e10b929-116f-4aee-8a17-eb5ad960f05e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137009388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2137009388
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.3655813462
Short name	T968
Test name
Test status
Simulation time	81520900 ps
CPU time	14.32 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:29:27 PM PDT 24
Peak memory	265232 kb
Host	smart-1f56a5aa-428a-4b08-8d9d-7f1292106816
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655813462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test. 3655813462
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.345706946
Short name	T50
Test name
Test status
Simulation time	30235600 ps
CPU time	13.97 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:29:26 PM PDT 24
Peak memory	284268 kb
Host	smart-7bc6d876-612f-4066-9494-8bcf563a3582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=345706946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.345706946
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.2367427914
Short name	T977
Test name
Test status
Simulation time	46924000 ps
CPU time	21.84 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:29:35 PM PDT 24
Peak memory	273628 kb
Host	smart-72b4011b-5863-470e-a94f-bc2bf7e03073
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367427914 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.2367427914
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1573354803
Short name	T406
Test name
Test status
Simulation time	3477398200 ps
CPU time	147.38 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:31:39 PM PDT 24
Peak memory	260904 kb
Host	smart-9e18af21-d3f8-4db6-a287-ead257398c26
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573354803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.1573354803
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.3152049520
Short name	T264
Test name
Test status
Simulation time	1481022600 ps
CPU time	137.07 seconds
Started	Jul 10 07:29:17 PM PDT 24
Finished	Jul 10 07:31:35 PM PDT 24
Peak memory	291564 kb
Host	smart-e120d6a5-4ee7-464b-bfc1-4a304d3d08a2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152049520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.3152049520
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1247267390
Short name	T931
Test name
Test status
Simulation time	13842556500 ps
CPU time	280.8 seconds
Started	Jul 10 07:29:16 PM PDT 24
Finished	Jul 10 07:33:58 PM PDT 24
Peak memory	284964 kb
Host	smart-1c69d1e1-2323-47b1-af0e-6435781f6c20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247267390 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1247267390
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.2587737396
Short name	T750
Test name
Test status
Simulation time	69996700 ps
CPU time	131.03 seconds
Started	Jul 10 07:29:10 PM PDT 24
Finished	Jul 10 07:31:22 PM PDT 24
Peak memory	265264 kb
Host	smart-c80e1df1-b2b6-4d5d-a07b-239db7bf5cc9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587737396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.2587737396
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.120398507
Short name	T892
Test name
Test status
Simulation time	26436100 ps
CPU time	30.56 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:29:44 PM PDT 24
Peak memory	275688 kb
Host	smart-de8bbc78-9eac-405e-ad3a-a1f112b17ba0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120398507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_rw_evict.120398507
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.503154840
Short name	T38
Test name
Test status
Simulation time	28173900 ps
CPU time	28.94 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:29:41 PM PDT 24
Peak memory	267580 kb
Host	smart-4c056c81-f9f2-4708-a908-05c5d3575baa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503154840 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.503154840
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.4273527605
Short name	T1010
Test name
Test status
Simulation time	10350950800 ps
CPU time	83.41 seconds
Started	Jul 10 07:29:12 PM PDT 24
Finished	Jul 10 07:30:37 PM PDT 24
Peak memory	264668 kb
Host	smart-9bbea4a1-55f1-4a35-bba5-71d38823b70c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273527605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.4273527605
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.3224632178
Short name	T971
Test name
Test status
Simulation time	62801500 ps
CPU time	99.18 seconds
Started	Jul 10 07:29:14 PM PDT 24
Finished	Jul 10 07:30:54 PM PDT 24
Peak memory	276080 kb
Host	smart-3ee2b137-ad48-47e7-957f-9d565f40857f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224632178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3224632178
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.3357805009
Short name	T756
Test name
Test status
Simulation time	327630800 ps
CPU time	13.58 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:29:35 PM PDT 24
Peak memory	265232 kb
Host	smart-bb97ab52-8e8e-44d0-9cab-33a82fa50bc7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357805009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 3357805009
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.1084213528
Short name	T935
Test name
Test status
Simulation time	56055200 ps
CPU time	15.68 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:29:39 PM PDT 24
Peak memory	275100 kb
Host	smart-109eff7b-feab-4ff5-8b1b-95442624a65d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084213528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1084213528
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.18313490
Short name	T673
Test name
Test status
Simulation time	12321900 ps
CPU time	22.1 seconds
Started	Jul 10 07:29:22 PM PDT 24
Finished	Jul 10 07:29:45 PM PDT 24
Peak memory	273696 kb
Host	smart-6bb13245-9b4c-4709-b150-bfbf91dbf5e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18313490 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 37.flash_ctrl_disable.18313490
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1294827930
Short name	T831
Test name
Test status
Simulation time	20673469500 ps
CPU time	67.61 seconds
Started	Jul 10 07:29:16 PM PDT 24
Finished	Jul 10 07:30:24 PM PDT 24
Peak memory	262796 kb
Host	smart-071371cd-8ecd-4440-bc73-66abd9823423
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294827930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.1294827930
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1278665787
Short name	T1060
Test name
Test status
Simulation time	12006172800 ps
CPU time	156.16 seconds
Started	Jul 10 07:29:23 PM PDT 24
Finished	Jul 10 07:32:01 PM PDT 24
Peak memory	291104 kb
Host	smart-702b0171-2cee-442f-bb4a-da1720931de7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278665787 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1278665787
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.231296073
Short name	T764
Test name
Test status
Simulation time	41235900 ps
CPU time	112.12 seconds
Started	Jul 10 07:29:23 PM PDT 24
Finished	Jul 10 07:31:17 PM PDT 24
Peak memory	264920 kb
Host	smart-ceead314-ffad-4aad-bc74-6112a6f1d30e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231296073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ot p_reset.231296073
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.2916413737
Short name	T56
Test name
Test status
Simulation time	40406300 ps
CPU time	31.45 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:29:53 PM PDT 24
Peak memory	268496 kb
Host	smart-d7954482-b523-4062-b768-534a3fd19215
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916413737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl ash_ctrl_rw_evict.2916413737
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.430941401
Short name	T834
Test name
Test status
Simulation time	26590900 ps
CPU time	29 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:29:52 PM PDT 24
Peak memory	268464 kb
Host	smart-4db9d4ff-919c-4e06-bd00-a843f6071a82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430941401 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.430941401
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.1252963061
Short name	T430
Test name
Test status
Simulation time	37442500 ps
CPU time	120.53 seconds
Started	Jul 10 07:29:11 PM PDT 24
Finished	Jul 10 07:31:12 PM PDT 24
Peak memory	276436 kb
Host	smart-b87d7de9-eafd-4e67-9728-402bd44bbc89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252963061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1252963061
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.2785886607
Short name	T864
Test name
Test status
Simulation time	45853000 ps
CPU time	13.78 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:29:46 PM PDT 24
Peak memory	265196 kb
Host	smart-563ad9af-abe6-44bf-9a76-cc78f42cc466
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785886607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 2785886607
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.323104587
Short name	T441
Test name
Test status
Simulation time	14076000 ps
CPU time	13.36 seconds
Started	Jul 10 07:29:19 PM PDT 24
Finished	Jul 10 07:29:33 PM PDT 24
Peak memory	284536 kb
Host	smart-f12049dd-6725-4ab5-8091-db4f8da06d2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323104587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.323104587
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.3031271010
Short name	T350
Test name
Test status
Simulation time	63593200 ps
CPU time	22.12 seconds
Started	Jul 10 07:29:20 PM PDT 24
Finished	Jul 10 07:29:43 PM PDT 24
Peak memory	273604 kb
Host	smart-da7a3a88-4e1c-46a9-9143-81e2234deb4d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031271010 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.3031271010
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.930075559
Short name	T1035
Test name
Test status
Simulation time	16253461700 ps
CPU time	126.55 seconds
Started	Jul 10 07:29:24 PM PDT 24
Finished	Jul 10 07:31:32 PM PDT 24
Peak memory	260912 kb
Host	smart-9b46eeea-1cd3-498d-82bf-2a2574697fcf
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930075559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h w_sec_otp.930075559
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.3801991927
Short name	T35
Test name
Test status
Simulation time	1481200100 ps
CPU time	189.51 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:32:32 PM PDT 24
Peak memory	291412 kb
Host	smart-bb41ec21-d74d-43cb-8735-ca0fe0e6873f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801991927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.3801991927
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1683534072
Short name	T525
Test name
Test status
Simulation time	23039604200 ps
CPU time	148.03 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:31:51 PM PDT 24
Peak memory	293148 kb
Host	smart-03a248b0-b681-4c84-8fad-4b83dba5bce1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683534072 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1683534072
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.3817903377
Short name	T349
Test name
Test status
Simulation time	72634300 ps
CPU time	110.31 seconds
Started	Jul 10 07:29:22 PM PDT 24
Finished	Jul 10 07:31:14 PM PDT 24
Peak memory	261224 kb
Host	smart-57a50d2c-f206-4d3c-a250-e4d05b56b644
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817903377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o tp_reset.3817903377
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.2843585329
Short name	T193
Test name
Test status
Simulation time	29779800 ps
CPU time	31.41 seconds
Started	Jul 10 07:29:20 PM PDT 24
Finished	Jul 10 07:29:53 PM PDT 24
Peak memory	268500 kb
Host	smart-947daf00-ce4f-43b0-b11f-cc3c8cb02b91
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843585329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl ash_ctrl_rw_evict.2843585329
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.525355448
Short name	T188
Test name
Test status
Simulation time	49372700 ps
CPU time	30.5 seconds
Started	Jul 10 07:29:20 PM PDT 24
Finished	Jul 10 07:29:51 PM PDT 24
Peak memory	268512 kb
Host	smart-9ad0bfb8-edf2-4a1c-b667-91840f583d8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525355448 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.525355448
Directory	/workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.3876093470
Short name	T364
Test name
Test status
Simulation time	21737793200 ps
CPU time	97.21 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:31:00 PM PDT 24
Peak memory	263636 kb
Host	smart-5c2acdc9-10a8-4b48-825d-44ca5d9d4c17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876093470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3876093470
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.4111732720
Short name	T942
Test name
Test status
Simulation time	184137100 ps
CPU time	170.79 seconds
Started	Jul 10 07:29:21 PM PDT 24
Finished	Jul 10 07:32:13 PM PDT 24
Peak memory	277560 kb
Host	smart-64d34f28-091f-4b61-ae9b-fdb4137c9bfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111732720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.4111732720
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.3826543873
Short name	T622
Test name
Test status
Simulation time	75500900 ps
CPU time	13.92 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:29:47 PM PDT 24
Peak memory	258352 kb
Host	smart-3c44bdee-279d-4aa9-a8d8-1a9109a89fde
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826543873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 3826543873
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.3808983873
Short name	T1110
Test name
Test status
Simulation time	14661700 ps
CPU time	13.56 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:29:45 PM PDT 24
Peak memory	274848 kb
Host	smart-bfeec07d-6a05-4bff-8f7e-93a082b89444
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808983873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3808983873
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.3191848650
Short name	T501
Test name
Test status
Simulation time	31875200 ps
CPU time	22.83 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:29:55 PM PDT 24
Peak memory	273616 kb
Host	smart-4d8e7135-0dfe-4fc7-860c-8b3fe2ae01a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191848650 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.3191848650
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3994197014
Short name	T298
Test name
Test status
Simulation time	16282231500 ps
CPU time	219.46 seconds
Started	Jul 10 07:29:29 PM PDT 24
Finished	Jul 10 07:33:09 PM PDT 24
Peak memory	262404 kb
Host	smart-fd640fd9-589c-4b96-b3de-45de7b421558
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994197014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ hw_sec_otp.3994197014
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.2849919126
Short name	T307
Test name
Test status
Simulation time	3075316300 ps
CPU time	215.75 seconds
Started	Jul 10 07:29:33 PM PDT 24
Finished	Jul 10 07:33:10 PM PDT 24
Peak memory	291424 kb
Host	smart-12d81f65-51d3-488b-88a9-4a59eaf74250
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849919126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.2849919126
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4219522341
Short name	T668
Test name
Test status
Simulation time	6073766700 ps
CPU time	154.04 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:32:07 PM PDT 24
Peak memory	294340 kb
Host	smart-f066561a-973a-4624-92c9-56e8c30001db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219522341 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.4219522341
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.3879680964
Short name	T503
Test name
Test status
Simulation time	41026100 ps
CPU time	129.52 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:31:42 PM PDT 24
Peak memory	260016 kb
Host	smart-92e6aa1a-55ec-4167-ad3f-bbac645b79e9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879680964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.3879680964
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.1442012073
Short name	T131
Test name
Test status
Simulation time	154058300 ps
CPU time	31.64 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:30:04 PM PDT 24
Peak memory	275676 kb
Host	smart-e138e9d0-1b1c-4c6d-a99b-b72fe5ab207d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442012073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl ash_ctrl_rw_evict.1442012073
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.459935985
Short name	T848
Test name
Test status
Simulation time	126070400 ps
CPU time	30.8 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:30:04 PM PDT 24
Peak memory	268496 kb
Host	smart-41fc9cab-e2b7-4c9c-80fb-6b80a9e8d266
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459935985 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.459935985
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.656596973
Short name	T1068
Test name
Test status
Simulation time	17544495400 ps
CPU time	85.79 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:30:58 PM PDT 24
Peak memory	263664 kb
Host	smart-08b53f48-57f1-4e1f-ba9b-42b2733fab3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656596973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.656596973
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.1961794058
Short name	T429
Test name
Test status
Simulation time	28738500 ps
CPU time	120.13 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:31:31 PM PDT 24
Peak memory	276456 kb
Host	smart-288d1402-bf36-48af-8c1f-ab74efe863e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961794058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1961794058
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.840861859
Short name	T570
Test name
Test status
Simulation time	180285200 ps
CPU time	13.81 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:25:15 PM PDT 24
Peak memory	265220 kb
Host	smart-58629c4a-4ca5-4e5f-98f7-af3a43ea9266
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840861859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.840861859
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.1634416785
Short name	T936
Test name
Test status
Simulation time	43083800 ps
CPU time	13.93 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 07:25:19 PM PDT 24
Peak memory	261684 kb
Host	smart-ad269ff0-691f-4240-9536-1ae8e199fb87
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634416785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.1634416785
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.2695014180
Short name	T869
Test name
Test status
Simulation time	45881100 ps
CPU time	15.97 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:13 PM PDT 24
Peak memory	284392 kb
Host	smart-ecb63fb3-4b0e-41a2-ad91-cd30c4895681
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695014180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.2695014180
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.2227602066
Short name	T1083
Test name
Test status
Simulation time	31908000 ps
CPU time	21.74 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:19 PM PDT 24
Peak memory	273648 kb
Host	smart-7f404a04-5023-41b9-be09-9c07573be5a1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227602066 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.2227602066
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.3731041040
Short name	T714
Test name
Test status
Simulation time	5187108200 ps
CPU time	2251.47 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 08:02:28 PM PDT 24
Peak memory	265116 kb
Host	smart-11b128fe-03f0-4e4b-ad31-17acd7b8469d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3731041040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.3731041040
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.1441909191
Short name	T826
Test name
Test status
Simulation time	4639638700 ps
CPU time	3271.7 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 08:19:38 PM PDT 24
Peak memory	265240 kb
Host	smart-e63fcd36-868e-42b7-82c1-1def2bb308d4
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441909191 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1441909191
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.1056114458
Short name	T183
Test name
Test status
Simulation time	637449300 ps
CPU time	759.5 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:37:37 PM PDT 24
Peak memory	273428 kb
Host	smart-f2af4541-147d-49c6-96c0-dbb4a671d589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056114458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1056114458
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.2546571556
Short name	T488
Test name
Test status
Simulation time	110943400 ps
CPU time	22.46 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:25:26 PM PDT 24
Peak memory	263596 kb
Host	smart-0ce6b80d-d69c-49be-99b9-353f131dd770
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546571556 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2546571556
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.1297620234
Short name	T36
Test name
Test status
Simulation time	737269400 ps
CPU time	42.14 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:25:45 PM PDT 24
Peak memory	263064 kb
Host	smart-770a0794-f990-4a71-9877-2c0277c6af8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297620234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.1297620234
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.2488171898
Short name	T904
Test name
Test status
Simulation time	50871332500 ps
CPU time	4280.89 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 08:36:13 PM PDT 24
Peak memory	265080 kb
Host	smart-566f1236-7e76-4d7d-8178-29eb839729fc
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488171898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.2488171898
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3361985645
Short name	T82
Test name
Test status
Simulation time	377911540700 ps
CPU time	2458.02 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 08:05:47 PM PDT 24
Peak memory	265312 kb
Host	smart-0953430f-2014-466c-a073-6958b7330a10
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361985645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.3361985645
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.1872675616
Short name	T845
Test name
Test status
Simulation time	55157600 ps
CPU time	34.69 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:25:22 PM PDT 24
Peak memory	265264 kb
Host	smart-6c4af56d-1af3-40da-a61f-d097101117a4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1872675616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1872675616
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3607447001
Short name	T696
Test name
Test status
Simulation time	10019622100 ps
CPU time	76.42 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:26:17 PM PDT 24
Peak memory	287684 kb
Host	smart-738566eb-fbf0-4a18-9596-5d5313bea4ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607447001 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3607447001
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3164691378
Short name	T512
Test name
Test status
Simulation time	52725000 ps
CPU time	14.18 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:25:14 PM PDT 24
Peak memory	260296 kb
Host	smart-15aa5e6b-3428-471d-ae62-67a476d8a067
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164691378 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3164691378
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2792272728
Short name	T171
Test name
Test status
Simulation time	160175991700 ps
CPU time	826.85 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:38:41 PM PDT 24
Peak memory	263956 kb
Host	smart-c94481b8-f81c-4112-b47b-64c1313cf514
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792272728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.2792272728
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2425878538
Short name	T48
Test name
Test status
Simulation time	1557951700 ps
CPU time	57.99 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:25:51 PM PDT 24
Peak memory	262540 kb
Host	smart-14ac762c-25ee-492e-b796-af7e8fb60931
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425878538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.2425878538
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.1068500660
Short name	T1017
Test name
Test status
Simulation time	20596291800 ps
CPU time	583.45 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:34:46 PM PDT 24
Peak memory	336876 kb
Host	smart-be9273af-fdbb-4021-bb68-904cc6207705
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068500660 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.1068500660
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.455769963
Short name	T1053
Test name
Test status
Simulation time	1616643000 ps
CPU time	135.81 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:27:05 PM PDT 24
Peak memory	291376 kb
Host	smart-ba63a651-10f5-45b2-955d-cc42dbb72fd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455769963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_intr_rd.455769963
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3491618122
Short name	T909
Test name
Test status
Simulation time	48154146600 ps
CPU time	304.3 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:30:05 PM PDT 24
Peak memory	291100 kb
Host	smart-34838a48-c7d5-40b8-95d3-b8dcbf08af88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491618122 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3491618122
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.1005031146
Short name	T456
Test name
Test status
Simulation time	10044366500 ps
CPU time	81.25 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	265332 kb
Host	smart-e484ea79-a15a-49e2-9089-41faab0079ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005031146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.1005031146
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2219684072
Short name	T26
Test name
Test status
Simulation time	20869489500 ps
CPU time	166.02 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:27:34 PM PDT 24
Peak memory	260428 kb
Host	smart-9309ecb7-b9b3-4e25-a69c-040d05885025
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221 9684072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2219684072
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.475678269
Short name	T83
Test name
Test status
Simulation time	4225725400 ps
CPU time	72.36 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:26:11 PM PDT 24
Peak memory	260608 kb
Host	smart-0f481c84-8167-47a9-b89a-56578aee27d1
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475678269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.475678269
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.717149574
Short name	T148
Test name
Test status
Simulation time	46178400 ps
CPU time	13.27 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:25:13 PM PDT 24
Peak memory	260940 kb
Host	smart-ab2be720-57d2-4a38-a668-d37a885a21ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717149574 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.717149574
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.4070381747
Short name	T125
Test name
Test status
Simulation time	11485654500 ps
CPU time	897.9 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:39:52 PM PDT 24
Peak memory	274872 kb
Host	smart-70a372a3-36a6-4721-b58c-696b62366c9f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070381747 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.4070381747
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.3112129821
Short name	T343
Test name
Test status
Simulation time	2601973400 ps
CPU time	172.71 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:27:43 PM PDT 24
Peak memory	281812 kb
Host	smart-8e5f1e39-908c-4183-be39-fc0d31d0b4ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112129821 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3112129821
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3215357470
Short name	T63
Test name
Test status
Simulation time	15528400 ps
CPU time	14.21 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:25:15 PM PDT 24
Peak memory	276964 kb
Host	smart-74afd99a-d996-44ea-ba51-f132b4125efc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3215357470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3215357470
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.2983358479
Short name	T571
Test name
Test status
Simulation time	373757900 ps
CPU time	449.08 seconds
Started	Jul 10 07:24:50 PM PDT 24
Finished	Jul 10 07:32:24 PM PDT 24
Peak memory	263300 kb
Host	smart-f0583276-dcc0-4f06-bcb2-1af0e0159b91
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2983358479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2983358479
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2907539979
Short name	T75
Test name
Test status
Simulation time	780194200 ps
CPU time	21.12 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:25:12 PM PDT 24
Peak memory	265148 kb
Host	smart-389a0f69-7512-4ca3-a0cd-c4afa2301ed0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907539979 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2907539979
Directory	/workspace/4.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.760926701
Short name	T882
Test name
Test status
Simulation time	53429500 ps
CPU time	14.49 seconds
Started	Jul 10 07:24:54 PM PDT 24
Finished	Jul 10 07:25:13 PM PDT 24
Peak memory	262864 kb
Host	smart-9f5dcd3f-339f-4d69-87a7-b7f730c0f5b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760926701 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.760926701
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.844201102
Short name	T647
Test name
Test status
Simulation time	62039900 ps
CPU time	13.67 seconds
Started	Jul 10 07:24:51 PM PDT 24
Finished	Jul 10 07:25:11 PM PDT 24
Peak memory	259168 kb
Host	smart-cd3f8116-7c6c-47b4-9b0f-d6e0ed4e78e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844201102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.flash_ctrl_prog_reset.844201102
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.295009613
Short name	T720
Test name
Test status
Simulation time	409966800 ps
CPU time	803.03 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:38:21 PM PDT 24
Peak memory	285228 kb
Host	smart-f0354541-6b6a-4309-b57d-96def8fe317f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295009613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.295009613
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.4115891090
Short name	T585
Test name
Test status
Simulation time	130011100 ps
CPU time	101.97 seconds
Started	Jul 10 07:24:57 PM PDT 24
Finished	Jul 10 07:26:44 PM PDT 24
Peak memory	262900 kb
Host	smart-d24c9354-31bb-4197-a380-cc3a92259b82
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4115891090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.4115891090
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.3804577669
Short name	T133
Test name
Test status
Simulation time	77786400 ps
CPU time	31.68 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:25:30 PM PDT 24
Peak memory	273632 kb
Host	smart-474d32ea-3a4a-48b3-a101-76c4aa01cc3c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804577669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_re_evict.3804577669
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.374355716
Short name	T1097
Test name
Test status
Simulation time	33956700 ps
CPU time	21.4 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:25:21 PM PDT 24
Peak memory	265464 kb
Host	smart-4e67879f-2779-4c20-bedc-9cc799fcb6f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374355716 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.374355716
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2224197036
Short name	T902
Test name
Test status
Simulation time	47638700 ps
CPU time	22.87 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:25:17 PM PDT 24
Peak memory	265440 kb
Host	smart-8cbe2c8f-2d40-451f-8349-c2901cd647ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224197036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.2224197036
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.195959708
Short name	T719
Test name
Test status
Simulation time	1152281500 ps
CPU time	143.85 seconds
Started	Jul 10 07:24:52 PM PDT 24
Finished	Jul 10 07:27:22 PM PDT 24
Peak memory	290024 kb
Host	smart-c040d8fb-3a41-467a-a5e0-b1b49a196f1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195959708 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.flash_ctrl_ro.195959708
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.737225465
Short name	T1094
Test name
Test status
Simulation time	2230801500 ps
CPU time	155.49 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:27:23 PM PDT 24
Peak memory	281860 kb
Host	smart-9c5ec367-169c-4894-8d5f-913f797c6f79
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 737225465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.737225465
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.1606961636
Short name	T597
Test name
Test status
Simulation time	2761975800 ps
CPU time	112.57 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:26:44 PM PDT 24
Peak memory	281820 kb
Host	smart-8ab69e34-c2a5-4890-8bc4-d0d483b4ef78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606961636 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1606961636
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.387374189
Short name	T394
Test name
Test status
Simulation time	3840742400 ps
CPU time	547.06 seconds
Started	Jul 10 07:24:46 PM PDT 24
Finished	Jul 10 07:33:56 PM PDT 24
Peak memory	317796 kb
Host	smart-6d2faaf2-8f9c-43c1-bba6-382036ea256c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387374189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.387374189
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.967470791
Short name	T1034
Test name
Test status
Simulation time	69979000 ps
CPU time	30.73 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:25:17 PM PDT 24
Peak memory	275752 kb
Host	smart-380733cc-cddf-49a1-a532-d704370c1a9e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967470791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_rw_evict.967470791
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2882866732
Short name	T969
Test name
Test status
Simulation time	53930600 ps
CPU time	30.46 seconds
Started	Jul 10 07:24:54 PM PDT 24
Finished	Jul 10 07:25:29 PM PDT 24
Peak memory	268504 kb
Host	smart-cd36afe8-8357-477d-8a06-fc6781bdd15c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882866732 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2882866732
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_serr.2013680614
Short name	T99
Test name
Test status
Simulation time	10515886300 ps
CPU time	564.65 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 07:34:16 PM PDT 24
Peak memory	313204 kb
Host	smart-a715f261-27c3-4b01-a9d1-488820e98265
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013680614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s err.2013680614
Directory	/workspace/4.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.1827811463
Short name	T118
Test name
Test status
Simulation time	1074872800 ps
CPU time	4903.2 seconds
Started	Jul 10 07:24:48 PM PDT 24
Finished	Jul 10 08:46:35 PM PDT 24
Peak memory	283860 kb
Host	smart-eaeaea86-4f9b-4690-b28b-7462c166f09f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827811463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.1827811463
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.3291993503
Short name	T556
Test name
Test status
Simulation time	1781747700 ps
CPU time	100.81 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:26:30 PM PDT 24
Peak memory	273712 kb
Host	smart-923f5d50-a8f1-41ee-813a-2e8729d9e945
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291993503 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 4.flash_ctrl_serr_address.3291993503
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.2219255014
Short name	T944
Test name
Test status
Simulation time	846931500 ps
CPU time	84.81 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:26:23 PM PDT 24
Peak memory	273668 kb
Host	smart-98232b00-8ac5-4c40-a51f-12de6be238f8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219255014 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.2219255014
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.864611008
Short name	T422
Test name
Test status
Simulation time	47052700 ps
CPU time	52.11 seconds
Started	Jul 10 07:24:49 PM PDT 24
Finished	Jul 10 07:25:46 PM PDT 24
Peak memory	271428 kb
Host	smart-3e5f590e-e3d6-4a02-a2b6-e3720bcb9871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864611008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.864611008
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.3224900721
Short name	T677
Test name
Test status
Simulation time	51099900 ps
CPU time	23.62 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:25:28 PM PDT 24
Peak memory	259648 kb
Host	smart-6572b5de-20a5-43aa-8bbb-f594a18997c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224900721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3224900721
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.4268861577
Short name	T734
Test name
Test status
Simulation time	117626600 ps
CPU time	624.2 seconds
Started	Jul 10 07:24:45 PM PDT 24
Finished	Jul 10 07:35:11 PM PDT 24
Peak memory	283608 kb
Host	smart-0f86f72f-e2cf-4df1-b28e-837bcc756987
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268861577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.4268861577
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.1386258511
Short name	T653
Test name
Test status
Simulation time	165937800 ps
CPU time	26.55 seconds
Started	Jul 10 07:24:47 PM PDT 24
Finished	Jul 10 07:25:17 PM PDT 24
Peak memory	262316 kb
Host	smart-c7604ab1-b999-4e73-b9d3-82a2ba4ebc63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1386258511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1386258511
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.1896829303
Short name	T692
Test name
Test status
Simulation time	2645850200 ps
CPU time	224.97 seconds
Started	Jul 10 07:24:52 PM PDT 24
Finished	Jul 10 07:28:43 PM PDT 24
Peak memory	265316 kb
Host	smart-ec384533-c1a2-4764-84bc-1c2c45c51eed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896829303 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.1896829303
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.1780024304
Short name	T437
Test name
Test status
Simulation time	71794500 ps
CPU time	13.7 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:29:47 PM PDT 24
Peak memory	265260 kb
Host	smart-95e1ce22-3065-446b-86a0-03d8135056f5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780024304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 1780024304
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.905256478
Short name	T216
Test name
Test status
Simulation time	97813800 ps
CPU time	16.09 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:29:50 PM PDT 24
Peak memory	274988 kb
Host	smart-d22dcc3b-c8a1-4928-bdf2-23f9b63ab467
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905256478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.905256478
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.620325286
Short name	T85
Test name
Test status
Simulation time	36254800 ps
CPU time	21.51 seconds
Started	Jul 10 07:29:34 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	273696 kb
Host	smart-d1b320f6-1d3a-4118-996f-22bc3563defe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620325286 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.620325286
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.761106832
Short name	T736
Test name
Test status
Simulation time	4435124500 ps
CPU time	112.56 seconds
Started	Jul 10 07:29:30 PM PDT 24
Finished	Jul 10 07:31:24 PM PDT 24
Peak memory	260876 kb
Host	smart-124ce176-b4a0-4593-aacb-c0f1163491ab
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761106832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h w_sec_otp.761106832
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.1410526978
Short name	T710
Test name
Test status
Simulation time	149627900 ps
CPU time	132.39 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:31:44 PM PDT 24
Peak memory	265300 kb
Host	smart-8835c752-461b-4f90-8dff-21ce814ff5e5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410526978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o tp_reset.1410526978
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.1409907885
Short name	T1073
Test name
Test status
Simulation time	6725674300 ps
CPU time	80.82 seconds
Started	Jul 10 07:29:33 PM PDT 24
Finished	Jul 10 07:30:55 PM PDT 24
Peak memory	263792 kb
Host	smart-ad42b5b9-a475-47f4-bc3b-73ae3d8cf5ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409907885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1409907885
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.2990700263
Short name	T1099
Test name
Test status
Simulation time	87023400 ps
CPU time	75.69 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:30:49 PM PDT 24
Peak memory	276864 kb
Host	smart-d5f0aaf5-b24f-4f46-af5e-e29b5b9c7ef5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990700263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2990700263
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.1254292293
Short name	T919
Test name
Test status
Simulation time	80176400 ps
CPU time	14.13 seconds
Started	Jul 10 07:29:33 PM PDT 24
Finished	Jul 10 07:29:48 PM PDT 24
Peak memory	258312 kb
Host	smart-0b6b929e-9f01-4841-8e68-97781b115129
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254292293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 1254292293
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.2591675853
Short name	T1042
Test name
Test status
Simulation time	37001700 ps
CPU time	13.35 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:29:47 PM PDT 24
Peak memory	274804 kb
Host	smart-5641bdb0-9773-4eb0-946e-6162f37fa975
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591675853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2591675853
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.199494351
Short name	T338
Test name
Test status
Simulation time	14868200 ps
CPU time	21.78 seconds
Started	Jul 10 07:29:33 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	273612 kb
Host	smart-2f28bae4-9f1a-4b5c-b2b7-f8c0fec8dffa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199494351 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.199494351
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3526118031
Short name	T796
Test name
Test status
Simulation time	8475697500 ps
CPU time	164.68 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:32:17 PM PDT 24
Peak memory	261896 kb
Host	smart-b52b0344-9e51-422d-911d-e272f19b5d8f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526118031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.3526118031
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.4155031318
Short name	T672
Test name
Test status
Simulation time	142637800 ps
CPU time	133.35 seconds
Started	Jul 10 07:29:31 PM PDT 24
Finished	Jul 10 07:31:45 PM PDT 24
Peak memory	261144 kb
Host	smart-1603eebe-2248-4804-a49c-e9c34742fb00
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155031318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o tp_reset.4155031318
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.4013921170
Short name	T680
Test name
Test status
Simulation time	1638329300 ps
CPU time	61.63 seconds
Started	Jul 10 07:29:30 PM PDT 24
Finished	Jul 10 07:30:33 PM PDT 24
Peak memory	264892 kb
Host	smart-813dec8e-0a69-4492-ab7c-dc01028efa6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013921170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.4013921170
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.15953113
Short name	T481
Test name
Test status
Simulation time	21079000 ps
CPU time	51.74 seconds
Started	Jul 10 07:29:34 PM PDT 24
Finished	Jul 10 07:30:27 PM PDT 24
Peak memory	271492 kb
Host	smart-fefec700-94e2-41f0-8cae-06cee779182a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=15953113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.15953113
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.341980204
Short name	T836
Test name
Test status
Simulation time	44008600 ps
CPU time	13.92 seconds
Started	Jul 10 07:29:41 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	258292 kb
Host	smart-523a2d34-fcfc-46a4-8f5e-6a9dc86bfdff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341980204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.341980204
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.2268679957
Short name	T606
Test name
Test status
Simulation time	61230700 ps
CPU time	16.02 seconds
Started	Jul 10 07:29:41 PM PDT 24
Finished	Jul 10 07:29:58 PM PDT 24
Peak memory	274916 kb
Host	smart-9919a247-bcd8-4955-943c-3e839c4ae0d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268679957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2268679957
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.2033334855
Short name	T334
Test name
Test status
Simulation time	38947000 ps
CPU time	22.17 seconds
Started	Jul 10 07:29:46 PM PDT 24
Finished	Jul 10 07:30:09 PM PDT 24
Peak memory	274216 kb
Host	smart-23d4bbcb-f522-4671-8872-322bb13ee613
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033334855 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.2033334855
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3457660340
Short name	T847
Test name
Test status
Simulation time	2284539400 ps
CPU time	51.29 seconds
Started	Jul 10 07:29:33 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	262424 kb
Host	smart-f4a87f86-e81b-455b-8fab-5b7c9ee8bc06
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457660340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ hw_sec_otp.3457660340
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.4065579916
Short name	T347
Test name
Test status
Simulation time	79947400 ps
CPU time	130.68 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:31:54 PM PDT 24
Peak memory	260132 kb
Host	smart-63cc11f4-5c67-485e-a277-35631fc611c5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065579916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.4065579916
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.2987539748
Short name	T1092
Test name
Test status
Simulation time	9571916300 ps
CPU time	73.87 seconds
Started	Jul 10 07:29:40 PM PDT 24
Finished	Jul 10 07:30:55 PM PDT 24
Peak memory	263780 kb
Host	smart-312447d4-f9bd-49cd-8f74-8f5df07fcce5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987539748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2987539748
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.745361699
Short name	T445
Test name
Test status
Simulation time	71710200 ps
CPU time	143.62 seconds
Started	Jul 10 07:29:32 PM PDT 24
Finished	Jul 10 07:31:57 PM PDT 24
Peak memory	277124 kb
Host	smart-488218b6-9002-499d-9f3f-290c61d12ad5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745361699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.745361699
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.1787179525
Short name	T699
Test name
Test status
Simulation time	24826000 ps
CPU time	14.28 seconds
Started	Jul 10 07:29:41 PM PDT 24
Finished	Jul 10 07:29:57 PM PDT 24
Peak memory	258404 kb
Host	smart-60299985-07ac-463c-87be-a6f7fa7e0031
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787179525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 1787179525
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.725324015
Short name	T474
Test name
Test status
Simulation time	17318000 ps
CPU time	14.26 seconds
Started	Jul 10 07:29:46 PM PDT 24
Finished	Jul 10 07:30:01 PM PDT 24
Peak memory	284392 kb
Host	smart-2acc3c59-f420-40f1-bd52-9bf25574ef53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725324015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.725324015
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.2903144101
Short name	T755
Test name
Test status
Simulation time	99600800 ps
CPU time	22.3 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:30:05 PM PDT 24
Peak memory	265528 kb
Host	smart-9cffd0d3-b961-49b7-8437-1c98c208b0a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903144101 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.2903144101
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.4111703183
Short name	T993
Test name
Test status
Simulation time	8206430100 ps
CPU time	165.19 seconds
Started	Jul 10 07:29:44 PM PDT 24
Finished	Jul 10 07:32:30 PM PDT 24
Peak memory	261032 kb
Host	smart-8eadc609-a36d-4a83-ada6-5703a9a4d76b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111703183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.4111703183
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.2672442119
Short name	T774
Test name
Test status
Simulation time	41593200 ps
CPU time	131.46 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:31:55 PM PDT 24
Peak memory	260980 kb
Host	smart-8a3ceb73-8008-4dd7-a112-9dbeb0ee7aec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672442119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.2672442119
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.3240771516
Short name	T368
Test name
Test status
Simulation time	736362900 ps
CPU time	78.94 seconds
Started	Jul 10 07:29:44 PM PDT 24
Finished	Jul 10 07:31:03 PM PDT 24
Peak memory	263712 kb
Host	smart-0c813cda-8c70-42c5-b97e-82a28000b408
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240771516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3240771516
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.905350337
Short name	T1088
Test name
Test status
Simulation time	23837900 ps
CPU time	76.05 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:30:58 PM PDT 24
Peak memory	275556 kb
Host	smart-135c52bf-d355-44cc-b3ae-64b0470bf122
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905350337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.905350337
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.2407008128
Short name	T757
Test name
Test status
Simulation time	421235500 ps
CPU time	14.62 seconds
Started	Jul 10 07:29:41 PM PDT 24
Finished	Jul 10 07:29:56 PM PDT 24
Peak memory	265276 kb
Host	smart-185b4aa8-b21d-4dea-85f2-6114d048f256
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407008128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test. 2407008128
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.4182296332
Short name	T116
Test name
Test status
Simulation time	41730500 ps
CPU time	16.54 seconds
Started	Jul 10 07:29:43 PM PDT 24
Finished	Jul 10 07:30:00 PM PDT 24
Peak memory	274844 kb
Host	smart-4ea282e9-e27f-411e-b066-469617441809
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182296332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.4182296332
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.3583694643
Short name	T938
Test name
Test status
Simulation time	20900400 ps
CPU time	20.84 seconds
Started	Jul 10 07:29:43 PM PDT 24
Finished	Jul 10 07:30:04 PM PDT 24
Peak memory	273552 kb
Host	smart-b17e707b-18ae-4cac-86e7-eac735c6f751
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583694643 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.3583694643
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3209056959
Short name	T458
Test name
Test status
Simulation time	6893799400 ps
CPU time	113.47 seconds
Started	Jul 10 07:29:40 PM PDT 24
Finished	Jul 10 07:31:34 PM PDT 24
Peak memory	262948 kb
Host	smart-8d6dad7f-4030-4449-8daf-b33fee0e2866
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209056959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.3209056959
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.4017145622
Short name	T448
Test name
Test status
Simulation time	174761400 ps
CPU time	130.81 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:31:54 PM PDT 24
Peak memory	261072 kb
Host	smart-16171e06-7b1c-4b23-b09a-e92e57200458
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017145622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o tp_reset.4017145622
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.3288088007
Short name	T187
Test name
Test status
Simulation time	5553481000 ps
CPU time	70.74 seconds
Started	Jul 10 07:29:47 PM PDT 24
Finished	Jul 10 07:30:59 PM PDT 24
Peak memory	263172 kb
Host	smart-62436cde-c7d7-4d3c-8349-e35e8e291d73
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288088007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3288088007
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.813600872
Short name	T551
Test name
Test status
Simulation time	58247000 ps
CPU time	97.71 seconds
Started	Jul 10 07:29:45 PM PDT 24
Finished	Jul 10 07:31:23 PM PDT 24
Peak memory	276124 kb
Host	smart-aef631ef-18ba-4105-90ac-e6ad3131c722
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813600872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.813600872
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.50111209
Short name	T859
Test name
Test status
Simulation time	46506000 ps
CPU time	13.55 seconds
Started	Jul 10 07:29:46 PM PDT 24
Finished	Jul 10 07:30:01 PM PDT 24
Peak memory	258300 kb
Host	smart-2287e101-0d36-477d-8c0d-5802a564fb2a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50111209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.50111209
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.2631541176
Short name	T608
Test name
Test status
Simulation time	20388200 ps
CPU time	16.39 seconds
Started	Jul 10 07:29:45 PM PDT 24
Finished	Jul 10 07:30:02 PM PDT 24
Peak memory	284384 kb
Host	smart-77499f73-6ada-4cf3-8cba-ebc69c5271c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631541176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2631541176
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.3265906642
Short name	T336
Test name
Test status
Simulation time	13192900 ps
CPU time	21.92 seconds
Started	Jul 10 07:29:44 PM PDT 24
Finished	Jul 10 07:30:07 PM PDT 24
Peak memory	273652 kb
Host	smart-0d81340a-b6b5-4be6-8a8e-29e115353938
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265906642 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.3265906642
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.3097538233
Short name	T302
Test name
Test status
Simulation time	2801245700 ps
CPU time	88.98 seconds
Started	Jul 10 07:29:42 PM PDT 24
Finished	Jul 10 07:31:12 PM PDT 24
Peak memory	263284 kb
Host	smart-bf6c0bcd-648c-4871-a47e-8d17837ecd87
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097538233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.3097538233
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.2112414581
Short name	T109
Test name
Test status
Simulation time	40851100 ps
CPU time	133.34 seconds
Started	Jul 10 07:29:43 PM PDT 24
Finished	Jul 10 07:31:57 PM PDT 24
Peak memory	261188 kb
Host	smart-be4deca6-5f2c-4eb6-8013-4f8be3471cc7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112414581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.2112414581
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.1730028368
Short name	T356
Test name
Test status
Simulation time	383657000 ps
CPU time	57 seconds
Started	Jul 10 07:29:40 PM PDT 24
Finished	Jul 10 07:30:38 PM PDT 24
Peak memory	263784 kb
Host	smart-f563e266-6e96-4587-bf42-7d6c33eab90c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730028368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1730028368
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.1516113505
Short name	T537
Test name
Test status
Simulation time	95597200 ps
CPU time	99.13 seconds
Started	Jul 10 07:29:41 PM PDT 24
Finished	Jul 10 07:31:21 PM PDT 24
Peak memory	276416 kb
Host	smart-ebdd8254-0055-4464-bb72-3124738c8847
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516113505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1516113505
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.4024916293
Short name	T543
Test name
Test status
Simulation time	78525000 ps
CPU time	14.4 seconds
Started	Jul 10 07:29:50 PM PDT 24
Finished	Jul 10 07:30:05 PM PDT 24
Peak memory	258336 kb
Host	smart-944ac4e5-ed73-4d0a-a9fa-7cd30a0f66d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024916293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 4024916293
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.1915089920
Short name	T627
Test name
Test status
Simulation time	120703800 ps
CPU time	13.38 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:30:06 PM PDT 24
Peak memory	284312 kb
Host	smart-474f76e6-f5ac-402c-be08-087fbebb34f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915089920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1915089920
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.39615792
Short name	T351
Test name
Test status
Simulation time	26764100 ps
CPU time	21.87 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:30:14 PM PDT 24
Peak memory	273580 kb
Host	smart-110f235c-9cea-40c0-95d3-bde75de6c1ac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39615792 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 46.flash_ctrl_disable.39615792
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2187559584
Short name	T717
Test name
Test status
Simulation time	5913671300 ps
CPU time	113.67 seconds
Started	Jul 10 07:29:54 PM PDT 24
Finished	Jul 10 07:31:48 PM PDT 24
Peak memory	263292 kb
Host	smart-50b394da-3101-4d64-a247-ee43db7c164a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187559584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ hw_sec_otp.2187559584
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.1834672110
Short name	T549
Test name
Test status
Simulation time	42100200 ps
CPU time	133.23 seconds
Started	Jul 10 07:29:51 PM PDT 24
Finished	Jul 10 07:32:05 PM PDT 24
Peak memory	260152 kb
Host	smart-4ea895ad-370a-4ac0-9110-82a11a0999d3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834672110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.1834672110
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.3727273059
Short name	T589
Test name
Test status
Simulation time	1569027100 ps
CPU time	54.79 seconds
Started	Jul 10 07:29:50 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	264168 kb
Host	smart-3a34bba6-5a8a-4f4b-8622-ba5cbe1a4c5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727273059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3727273059
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.1137424008
Short name	T475
Test name
Test status
Simulation time	37649500 ps
CPU time	75.21 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:31:08 PM PDT 24
Peak memory	276676 kb
Host	smart-fd0a2b85-3c1b-4abe-88b6-80e5c4378de1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137424008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1137424008
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.3188866722
Short name	T823
Test name
Test status
Simulation time	18945400 ps
CPU time	13.64 seconds
Started	Jul 10 07:29:53 PM PDT 24
Finished	Jul 10 07:30:08 PM PDT 24
Peak memory	265232 kb
Host	smart-e8e013eb-309b-4456-aa3b-ba5bc2dffd4c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188866722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 3188866722
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.1657474671
Short name	T896
Test name
Test status
Simulation time	14547500 ps
CPU time	16.09 seconds
Started	Jul 10 07:29:51 PM PDT 24
Finished	Jul 10 07:30:08 PM PDT 24
Peak memory	284360 kb
Host	smart-a726589e-5944-4c00-9637-3908d4a2f123
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657474671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1657474671
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.2412774393
Short name	T1063
Test name
Test status
Simulation time	13870400 ps
CPU time	22.11 seconds
Started	Jul 10 07:29:53 PM PDT 24
Finished	Jul 10 07:30:16 PM PDT 24
Peak memory	275000 kb
Host	smart-c69334a5-0e6f-4889-9e36-aa156ce41bfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412774393 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.2412774393
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.447334951
Short name	T883
Test name
Test status
Simulation time	4487546200 ps
CPU time	52.51 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	260940 kb
Host	smart-fd76d93c-b2cf-4159-beac-ae82992d0cb5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447334951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_h w_sec_otp.447334951
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.2310171641
Short name	T943
Test name
Test status
Simulation time	164089500 ps
CPU time	109.75 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:31:43 PM PDT 24
Peak memory	260156 kb
Host	smart-555a2e65-ebcd-417d-8efb-4bd6b47f9500
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310171641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o tp_reset.2310171641
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.1851015690
Short name	T370
Test name
Test status
Simulation time	1361225100 ps
CPU time	66.18 seconds
Started	Jul 10 07:29:53 PM PDT 24
Finished	Jul 10 07:31:00 PM PDT 24
Peak memory	263280 kb
Host	smart-2b2435e7-ff64-4aab-b846-1c140374329e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851015690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1851015690
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.4226316031
Short name	T232
Test name
Test status
Simulation time	174865400 ps
CPU time	122.88 seconds
Started	Jul 10 07:29:51 PM PDT 24
Finished	Jul 10 07:31:54 PM PDT 24
Peak memory	276516 kb
Host	smart-c6468ec3-c84e-4613-ac4a-a57072142cf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226316031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.4226316031
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.3911540517
Short name	T424
Test name
Test status
Simulation time	34093500 ps
CPU time	13.72 seconds
Started	Jul 10 07:30:11 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	258340 kb
Host	smart-f1acfa43-3080-4062-afa4-1b0e2a7c0c76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911540517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test. 3911540517
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.2573112985
Short name	T117
Test name
Test status
Simulation time	14290300 ps
CPU time	15.54 seconds
Started	Jul 10 07:30:08 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	274764 kb
Host	smart-8787e523-6d43-4103-8728-28080a961783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573112985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2573112985
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.4083042874
Short name	T728
Test name
Test status
Simulation time	14521642600 ps
CPU time	123.3 seconds
Started	Jul 10 07:29:54 PM PDT 24
Finished	Jul 10 07:31:58 PM PDT 24
Peak memory	260988 kb
Host	smart-16616d53-0e80-44ee-b588-9d0868721221
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083042874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ hw_sec_otp.4083042874
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.3188916100
Short name	T400
Test name
Test status
Simulation time	147928200 ps
CPU time	134.53 seconds
Started	Jul 10 07:29:52 PM PDT 24
Finished	Jul 10 07:32:07 PM PDT 24
Peak memory	261200 kb
Host	smart-68f54f5f-c56a-4924-a7c4-458f4beb59ab
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188916100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o tp_reset.3188916100
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.1964466336
Short name	T908
Test name
Test status
Simulation time	3020643800 ps
CPU time	70.5 seconds
Started	Jul 10 07:30:06 PM PDT 24
Finished	Jul 10 07:31:18 PM PDT 24
Peak memory	263716 kb
Host	smart-c7b46af4-fed1-449c-b4f0-c3812775c844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964466336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1964466336
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.3156152075
Short name	T599
Test name
Test status
Simulation time	113146800 ps
CPU time	125.66 seconds
Started	Jul 10 07:29:51 PM PDT 24
Finished	Jul 10 07:31:58 PM PDT 24
Peak memory	278096 kb
Host	smart-d1901b6c-89bf-4ad2-b246-88831366e39e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156152075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3156152075
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.52692473
Short name	T447
Test name
Test status
Simulation time	173413600 ps
CPU time	13.95 seconds
Started	Jul 10 07:30:11 PM PDT 24
Finished	Jul 10 07:30:26 PM PDT 24
Peak memory	265448 kb
Host	smart-1258a2a2-a083-4d93-a4fe-bf8f5c280ea6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52692473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.52692473
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.387393019
Short name	T598
Test name
Test status
Simulation time	15245700 ps
CPU time	16.02 seconds
Started	Jul 10 07:30:08 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	284380 kb
Host	smart-4a1987f8-9f85-4a01-a893-17ad46832b7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387393019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.387393019
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.2639728896
Short name	T101
Test name
Test status
Simulation time	20554700 ps
CPU time	20.52 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:30:29 PM PDT 24
Peak memory	273556 kb
Host	smart-336fcc97-6fe8-405f-bfcd-7470b6391a18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639728896 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.2639728896
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.700748276
Short name	T531
Test name
Test status
Simulation time	1855764900 ps
CPU time	78.2 seconds
Started	Jul 10 07:30:09 PM PDT 24
Finished	Jul 10 07:31:28 PM PDT 24
Peak memory	263232 kb
Host	smart-f77f9fad-4fb6-4330-b9a8-ebe503e1061c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700748276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h w_sec_otp.700748276
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.2615859031
Short name	T1002
Test name
Test status
Simulation time	152796100 ps
CPU time	131.92 seconds
Started	Jul 10 07:30:12 PM PDT 24
Finished	Jul 10 07:32:25 PM PDT 24
Peak memory	260552 kb
Host	smart-fbd424c3-6b09-42b9-8d32-50184951e63d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615859031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.2615859031
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.1902664497
Short name	T341
Test name
Test status
Simulation time	5112053800 ps
CPU time	71.93 seconds
Started	Jul 10 07:30:06 PM PDT 24
Finished	Jul 10 07:31:19 PM PDT 24
Peak memory	264860 kb
Host	smart-6112791a-41fc-4ccc-a2eb-60c1f0c3d4dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902664497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.1902664497
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.3611291096
Short name	T682
Test name
Test status
Simulation time	39034800 ps
CPU time	195.78 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:33:24 PM PDT 24
Peak memory	277804 kb
Host	smart-e98ccaeb-7815-4835-a294-2d697183dd78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611291096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3611291096
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.3427594370
Short name	T466
Test name
Test status
Simulation time	36178200 ps
CPU time	13.65 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:25:16 PM PDT 24
Peak memory	258168 kb
Host	smart-f883dd53-71ed-4baf-b54a-f3ffc6ec444f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427594370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3 427594370
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.3207927759
Short name	T1081
Test name
Test status
Simulation time	50736300 ps
CPU time	13.22 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:25:16 PM PDT 24
Peak memory	284404 kb
Host	smart-d5395d44-bcc5-4c60-a865-97de91cffb66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207927759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3207927759
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.3218849391
Short name	T518
Test name
Test status
Simulation time	10743400 ps
CPU time	21.77 seconds
Started	Jul 10 07:24:57 PM PDT 24
Finished	Jul 10 07:25:24 PM PDT 24
Peak memory	265628 kb
Host	smart-d353d389-d60c-4e9b-808f-da6e87f6885b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218849391 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.3218849391
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.2182651074
Short name	T1082
Test name
Test status
Simulation time	5837465300 ps
CPU time	2290.52 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 08:03:13 PM PDT 24
Peak memory	262948 kb
Host	smart-bb735f7c-1ed1-49d1-aa58-161b043a481e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2182651074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.2182651074
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.138827144
Short name	T233
Test name
Test status
Simulation time	2918857300 ps
CPU time	853.43 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:39:14 PM PDT 24
Peak memory	270564 kb
Host	smart-163f3313-9000-4754-afae-8fba3203d3b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138827144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.138827144
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.1510547562
Short name	T52
Test name
Test status
Simulation time	710261000 ps
CPU time	27.1 seconds
Started	Jul 10 07:24:57 PM PDT 24
Finished	Jul 10 07:25:29 PM PDT 24
Peak memory	262568 kb
Host	smart-186333c3-7fd3-4969-9323-141b46507dd6
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510547562 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1510547562
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2102969810
Short name	T177
Test name
Test status
Simulation time	50637000 ps
CPU time	13.61 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 07:25:19 PM PDT 24
Peak memory	258560 kb
Host	smart-e102f4cf-11fb-4e76-9507-4e3a20c73e36
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102969810 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2102969810
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2935123243
Short name	T697
Test name
Test status
Simulation time	190210166700 ps
CPU time	875.51 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:39:37 PM PDT 24
Peak memory	260988 kb
Host	smart-b1a25738-88e8-46dd-8c88-9eefae8ac98c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935123243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_hw_rma_reset.2935123243
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.425900262
Short name	T296
Test name
Test status
Simulation time	12065846300 ps
CPU time	140.98 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:27:24 PM PDT 24
Peak memory	260944 kb
Host	smart-9a9cc85c-dd98-45dd-b3ef-6626fd350818
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425900262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw _sec_otp.425900262
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.2922247562
Short name	T515
Test name
Test status
Simulation time	3291860400 ps
CPU time	211.27 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:28:35 PM PDT 24
Peak memory	291408 kb
Host	smart-caa4bfd5-adff-49f6-a5f1-49f4c99ed38a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922247562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas h_ctrl_intr_rd.2922247562
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.142336577
Short name	T305
Test name
Test status
Simulation time	12225478200 ps
CPU time	338.35 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:30:41 PM PDT 24
Peak memory	291040 kb
Host	smart-25616be9-7a9c-48f6-a814-4588447a0640
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142336577 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.142336577
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.1053703243
Short name	T917
Test name
Test status
Simulation time	4289894200 ps
CPU time	72.23 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:26:13 PM PDT 24
Peak memory	260612 kb
Host	smart-061e58f8-0b1a-4fc1-9a7c-48361cc7b70b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053703243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_wr.1053703243
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3463558722
Short name	T827
Test name
Test status
Simulation time	114024871400 ps
CPU time	280.85 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:29:42 PM PDT 24
Peak memory	260428 kb
Host	smart-591de16b-a027-43d1-906b-4143d254d7ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346 3558722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3463558722
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.3601253963
Short name	T713
Test name
Test status
Simulation time	12355133200 ps
CPU time	101.27 seconds
Started	Jul 10 07:24:54 PM PDT 24
Finished	Jul 10 07:26:41 PM PDT 24
Peak memory	260604 kb
Host	smart-db67edde-1f97-4aa6-84c9-7b5d0a37e556
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601253963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3601253963
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3303087320
Short name	T583
Test name
Test status
Simulation time	15285600 ps
CPU time	13.56 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:25:18 PM PDT 24
Peak memory	260064 kb
Host	smart-2ebd592c-d1f8-49b9-8f8d-2f636690c717
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303087320 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3303087320
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.3965827809
Short name	T923
Test name
Test status
Simulation time	11861008300 ps
CPU time	366.88 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:31:07 PM PDT 24
Peak memory	274784 kb
Host	smart-6506dca1-7493-4bca-a8a6-ee4834beb8d9
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965827809 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.3965827809
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.844363209
Short name	T1076
Test name
Test status
Simulation time	171368000 ps
CPU time	131.97 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:27:15 PM PDT 24
Peak memory	264880 kb
Host	smart-ef9d2a12-fbfd-48da-b611-7174a4e1b995
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844363209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp _reset.844363209
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.1516062754
Short name	T787
Test name
Test status
Simulation time	4325263800 ps
CPU time	498.99 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:33:20 PM PDT 24
Peak memory	263200 kb
Host	smart-e65dfd76-0389-421c-8597-1c119d321950
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1516062754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1516062754
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.2978982188
Short name	T464
Test name
Test status
Simulation time	22485900 ps
CPU time	13.5 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:25:12 PM PDT 24
Peak memory	265264 kb
Host	smart-aa76c45a-bd67-4b96-8909-7909d17ed2cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978982188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.flash_ctrl_prog_reset.2978982188
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.32327197
Short name	T654
Test name
Test status
Simulation time	811317100 ps
CPU time	580.21 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:34:44 PM PDT 24
Peak memory	282280 kb
Host	smart-f6340873-5b4d-4e45-aa73-27fbf2b62387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32327197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.32327197
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.1600280011
Short name	T267
Test name
Test status
Simulation time	1014128900 ps
CPU time	31.47 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:25:34 PM PDT 24
Peak memory	273636 kb
Host	smart-7b57f6bf-4451-42b2-9bb0-3032af5110af
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600280011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.1600280011
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.3582598282
Short name	T562
Test name
Test status
Simulation time	453721000 ps
CPU time	123.7 seconds
Started	Jul 10 07:24:53 PM PDT 24
Finished	Jul 10 07:27:02 PM PDT 24
Peak memory	291300 kb
Host	smart-d31edd41-f441-40cf-823c-1f1bd7916373
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582598282 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.3582598282
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.261481880
Short name	T230
Test name
Test status
Simulation time	1163705500 ps
CPU time	169.17 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:27:50 PM PDT 24
Peak memory	281900 kb
Host	smart-4d7fb4f2-c4fd-4f80-82b8-d76ed263c768
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 261481880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.261481880
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.148266267
Short name	T547
Test name
Test status
Simulation time	453027500 ps
CPU time	134.93 seconds
Started	Jul 10 07:24:59 PM PDT 24
Finished	Jul 10 07:27:18 PM PDT 24
Peak memory	295188 kb
Host	smart-399e7150-9d15-4347-a1d4-676b11a82cae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148266267 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.148266267
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.221048800
Short name	T129
Test name
Test status
Simulation time	7525447400 ps
CPU time	544.07 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:34:05 PM PDT 24
Peak memory	310084 kb
Host	smart-82101d6b-a95d-4ab3-9085-925bcbae6d4c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221048800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.221048800
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.3738735355
Short name	T705
Test name
Test status
Simulation time	9662656800 ps
CPU time	768.47 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:37:52 PM PDT 24
Peak memory	343628 kb
Host	smart-cf20a557-d508-41ba-a805-46415a78e053
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738735355 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_rw_derr.3738735355
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2674068170
Short name	T528
Test name
Test status
Simulation time	52346800 ps
CPU time	30.96 seconds
Started	Jul 10 07:24:55 PM PDT 24
Finished	Jul 10 07:25:32 PM PDT 24
Peak memory	275660 kb
Host	smart-c5f0de9d-9117-4202-b810-d981f94b5f88
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674068170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2674068170
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3542091125
Short name	T1100
Test name
Test status
Simulation time	39851500 ps
CPU time	30.95 seconds
Started	Jul 10 07:24:54 PM PDT 24
Finished	Jul 10 07:25:31 PM PDT 24
Peak memory	273628 kb
Host	smart-11932d22-55ba-4ea1-8604-6895c57a5ed6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542091125 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3542091125
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.1632043829
Short name	T363
Test name
Test status
Simulation time	2175960500 ps
CPU time	64.84 seconds
Started	Jul 10 07:24:57 PM PDT 24
Finished	Jul 10 07:26:06 PM PDT 24
Peak memory	264768 kb
Host	smart-caf09c19-a8ec-415d-853f-ef96928be88c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1632043829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1632043829
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.1986668710
Short name	T718
Test name
Test status
Simulation time	136991200 ps
CPU time	217.2 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 07:28:43 PM PDT 24
Peak memory	279200 kb
Host	smart-a10293e9-1844-4dfb-a727-0512f8748ab0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986668710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1986668710
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.3445284996
Short name	T893
Test name
Test status
Simulation time	2403629700 ps
CPU time	221.74 seconds
Started	Jul 10 07:25:06 PM PDT 24
Finished	Jul 10 07:28:49 PM PDT 24
Peak memory	260088 kb
Host	smart-72834dcb-7406-4460-ad04-1fbc2717f262
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445284996 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.3445284996
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.2697745511
Short name	T426
Test name
Test status
Simulation time	14923000 ps
CPU time	16.28 seconds
Started	Jul 10 07:30:06 PM PDT 24
Finished	Jul 10 07:30:23 PM PDT 24
Peak memory	274932 kb
Host	smart-d38feb54-ba94-415c-a661-9a7cbd4a9493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2697745511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2697745511
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.627567559
Short name	T825
Test name
Test status
Simulation time	150109500 ps
CPU time	131.05 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:32:20 PM PDT 24
Peak memory	260316 kb
Host	smart-4b20e748-229d-42cc-afe2-b8a31d70f317
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627567559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot p_reset.627567559
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.2904234570
Short name	T304
Test name
Test status
Simulation time	27598500 ps
CPU time	16.22 seconds
Started	Jul 10 07:30:11 PM PDT 24
Finished	Jul 10 07:30:28 PM PDT 24
Peak memory	274872 kb
Host	smart-97c177e7-cd67-4d7a-afe3-ec7c088ce37e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904234570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2904234570
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.1700526401
Short name	T962
Test name
Test status
Simulation time	38023400 ps
CPU time	133.63 seconds
Started	Jul 10 07:30:08 PM PDT 24
Finished	Jul 10 07:32:23 PM PDT 24
Peak memory	260152 kb
Host	smart-e9f1f0a4-950a-4f28-98a0-82a8d1b02bf2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700526401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.1700526401
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.3243389247
Short name	T19
Test name
Test status
Simulation time	80443000 ps
CPU time	13.46 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:30:21 PM PDT 24
Peak memory	284440 kb
Host	smart-c2000aa9-4d5c-4296-8581-8ed1833045fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243389247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3243389247
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.2990749788
Short name	T511
Test name
Test status
Simulation time	133737800 ps
CPU time	132.57 seconds
Started	Jul 10 07:30:09 PM PDT 24
Finished	Jul 10 07:32:23 PM PDT 24
Peak memory	260164 kb
Host	smart-d9c2d90e-eaf6-42a6-90ce-ed7aca2386ba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990749788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o tp_reset.2990749788
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.1163038053
Short name	T452
Test name
Test status
Simulation time	241770800 ps
CPU time	13.68 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:30:21 PM PDT 24
Peak memory	275008 kb
Host	smart-c841ff51-1b5c-49a8-8d3c-0f70821e555d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163038053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1163038053
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.3396164829
Short name	T961
Test name
Test status
Simulation time	35654800 ps
CPU time	130.47 seconds
Started	Jul 10 07:30:10 PM PDT 24
Finished	Jul 10 07:32:21 PM PDT 24
Peak memory	264744 kb
Host	smart-bb068e95-c15f-44a6-845a-ab1a8ab8e123
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396164829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o tp_reset.3396164829
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.1880698120
Short name	T648
Test name
Test status
Simulation time	52875300 ps
CPU time	16.02 seconds
Started	Jul 10 07:30:11 PM PDT 24
Finished	Jul 10 07:30:28 PM PDT 24
Peak memory	284400 kb
Host	smart-a3343947-1c06-4569-ba29-9f8d9fc02bd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880698120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1880698120
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.2165887518
Short name	T1065
Test name
Test status
Simulation time	150518200 ps
CPU time	109.89 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:31:59 PM PDT 24
Peak memory	261024 kb
Host	smart-d2962c88-9ce4-42c9-9e40-bca0eb5a4f91
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165887518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.2165887518
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.3742571206
Short name	T868
Test name
Test status
Simulation time	26761400 ps
CPU time	15.88 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:30:25 PM PDT 24
Peak memory	274852 kb
Host	smart-df734a21-9242-4b13-bf0b-118d92884d0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742571206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3742571206
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.140572859
Short name	T153
Test name
Test status
Simulation time	69846200 ps
CPU time	133.97 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:32:22 PM PDT 24
Peak memory	260052 kb
Host	smart-3af60660-f811-4906-bb2b-184062939aa9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140572859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot p_reset.140572859
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.419294685
Short name	T875
Test name
Test status
Simulation time	47394600 ps
CPU time	15.97 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:30:24 PM PDT 24
Peak memory	284328 kb
Host	smart-adfc3579-c9a3-40f4-bd10-59f3b65a59e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=419294685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.419294685
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.3587847281
Short name	T658
Test name
Test status
Simulation time	43786500 ps
CPU time	110.1 seconds
Started	Jul 10 07:30:09 PM PDT 24
Finished	Jul 10 07:32:00 PM PDT 24
Peak memory	260008 kb
Host	smart-249031f7-a47c-4e88-b261-47b450a0046d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587847281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.3587847281
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.4000166207
Short name	T579
Test name
Test status
Simulation time	13290500 ps
CPU time	15.7 seconds
Started	Jul 10 07:30:06 PM PDT 24
Finished	Jul 10 07:30:23 PM PDT 24
Peak memory	274876 kb
Host	smart-62ef08f5-8d17-47fc-bacb-53e7afad0656
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000166207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.4000166207
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.2601810608
Short name	T982
Test name
Test status
Simulation time	151287700 ps
CPU time	129.99 seconds
Started	Jul 10 07:30:07 PM PDT 24
Finished	Jul 10 07:32:19 PM PDT 24
Peak memory	265064 kb
Host	smart-f7ff17ee-369e-48e0-9a33-2db023616ca3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601810608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o tp_reset.2601810608
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.2424170446
Short name	T1041
Test name
Test status
Simulation time	70327300 ps
CPU time	13.26 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:30:35 PM PDT 24
Peak memory	284252 kb
Host	smart-85bd5df6-052c-4986-bc1b-aee718a13d3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424170446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2424170446
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.3416897409
Short name	T1016
Test name
Test status
Simulation time	37705600 ps
CPU time	131.45 seconds
Started	Jul 10 07:30:08 PM PDT 24
Finished	Jul 10 07:32:21 PM PDT 24
Peak memory	260960 kb
Host	smart-1b817e01-668e-4326-a7a5-fd97325bf47d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416897409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o tp_reset.3416897409
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.2639416952
Short name	T533
Test name
Test status
Simulation time	38451800 ps
CPU time	15.71 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:30:37 PM PDT 24
Peak memory	284364 kb
Host	smart-9e78fab5-990f-4284-ba0d-f1a6f5b32a77
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639416952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2639416952
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.1074353991
Short name	T854
Test name
Test status
Simulation time	70055100 ps
CPU time	131.59 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:32:33 PM PDT 24
Peak memory	261060 kb
Host	smart-a8b0ad61-6629-49a8-af60-b4967ee7d4a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074353991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.1074353991
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.1801183295
Short name	T924
Test name
Test status
Simulation time	26508300 ps
CPU time	14.03 seconds
Started	Jul 10 07:25:03 PM PDT 24
Finished	Jul 10 07:25:20 PM PDT 24
Peak memory	258296 kb
Host	smart-782371ef-7225-48bb-a7ca-4e50b0ef754b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801183295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1 801183295
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.1026301787
Short name	T1108
Test name
Test status
Simulation time	74315800 ps
CPU time	15.76 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:25:39 PM PDT 24
Peak memory	274800 kb
Host	smart-7bd64db7-a3e2-4d77-ae9b-68e5b7ea6b71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026301787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1026301787
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.3978705267
Short name	T67
Test name
Test status
Simulation time	57574400 ps
CPU time	21.16 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:25:28 PM PDT 24
Peak memory	265540 kb
Host	smart-8470f98c-0d65-420f-b5b4-b975a6f6cbb8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978705267 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.3978705267
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.2736169619
Short name	T1091
Test name
Test status
Simulation time	20485774500 ps
CPU time	2410.4 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 08:05:16 PM PDT 24
Peak memory	265136 kb
Host	smart-ac166c61-2967-4e92-b55e-2608d57509d1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2736169619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.2736169619
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.400732473
Short name	T542
Test name
Test status
Simulation time	2144291000 ps
CPU time	831.41 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:38:55 PM PDT 24
Peak memory	270488 kb
Host	smart-bd9a71d2-53a0-415e-bd7d-a786fdf6efa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=400732473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.400732473
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1055073960
Short name	T87
Test name
Test status
Simulation time	10019683800 ps
CPU time	174.16 seconds
Started	Jul 10 07:25:18 PM PDT 24
Finished	Jul 10 07:28:15 PM PDT 24
Peak memory	294868 kb
Host	smart-f5ff2582-a2ed-47ae-8bba-0d3be656777c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055073960 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1055073960
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.4092567108
Short name	T482
Test name
Test status
Simulation time	15894400 ps
CPU time	13.63 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:25:20 PM PDT 24
Peak memory	265136 kb
Host	smart-c530725f-604a-4e7d-b8a0-978f2a1c94cc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092567108 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.4092567108
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.179429124
Short name	T821
Test name
Test status
Simulation time	320244143100 ps
CPU time	889.08 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:39:55 PM PDT 24
Peak memory	264056 kb
Host	smart-352c8c1a-f944-4327-9112-dac2326a1a82
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179429124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.flash_ctrl_hw_rma_reset.179429124
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3680298113
Short name	T297
Test name
Test status
Simulation time	14518996800 ps
CPU time	140 seconds
Started	Jul 10 07:24:56 PM PDT 24
Finished	Jul 10 07:27:21 PM PDT 24
Peak memory	262868 kb
Host	smart-a0323bfd-008c-41f2-b89e-adea55910643
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680298113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.3680298113
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.2294432940
Short name	T316
Test name
Test status
Simulation time	2136609400 ps
CPU time	220.68 seconds
Started	Jul 10 07:25:07 PM PDT 24
Finished	Jul 10 07:28:49 PM PDT 24
Peak memory	291060 kb
Host	smart-7a8523e1-4d4d-4fdf-aa93-c583cf0de361
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294432940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_intr_rd.2294432940
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3905072180
Short name	T546
Test name
Test status
Simulation time	9012667900 ps
CPU time	227.31 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:29:10 PM PDT 24
Peak memory	290948 kb
Host	smart-941ae572-b386-4060-a1f6-a7daa1cdd56d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905072180 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3905072180
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.3214540084
Short name	T974
Test name
Test status
Simulation time	9806425600 ps
CPU time	76.22 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:26:39 PM PDT 24
Peak memory	265208 kb
Host	smart-86be898c-c218-4ef4-aa85-63d0ed322872
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214540084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.3214540084
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.537753529
Short name	T28
Test name
Test status
Simulation time	192929905100 ps
CPU time	197.76 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 07:28:23 PM PDT 24
Peak memory	259900 kb
Host	smart-f3af27e3-700c-4831-9d1e-c624d70230b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537 753529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.537753529
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.2951059777
Short name	T629
Test name
Test status
Simulation time	963675800 ps
CPU time	85.66 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:26:30 PM PDT 24
Peak memory	262632 kb
Host	smart-67e3bde4-e0ee-4e2f-9860-1e3a541c4ccb
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951059777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.2951059777
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.293133530
Short name	T592
Test name
Test status
Simulation time	11948982200 ps
CPU time	166.96 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:27:52 PM PDT 24
Peak memory	265148 kb
Host	smart-1810b7bf-ea43-4dd5-afcc-4c2ba4774485
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293133530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.293133530
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.184191814
Short name	T154
Test name
Test status
Simulation time	36056100 ps
CPU time	110.41 seconds
Started	Jul 10 07:25:02 PM PDT 24
Finished	Jul 10 07:26:56 PM PDT 24
Peak memory	264412 kb
Host	smart-96352f09-bb94-4121-9d24-a3fb03842417
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184191814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp _reset.184191814
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.738713911
Short name	T738
Test name
Test status
Simulation time	85221000 ps
CPU time	438.61 seconds
Started	Jul 10 07:24:58 PM PDT 24
Finished	Jul 10 07:32:21 PM PDT 24
Peak memory	263232 kb
Host	smart-c9ddece1-3e6b-4b65-adb5-c29feed5ccf2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=738713911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.738713911
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.2876170285
Short name	T601
Test name
Test status
Simulation time	21107800 ps
CPU time	13.92 seconds
Started	Jul 10 07:25:06 PM PDT 24
Finished	Jul 10 07:25:22 PM PDT 24
Peak memory	265160 kb
Host	smart-4353b6ef-99c8-4f02-ac99-0fd1de98a2e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876170285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.2876170285
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.316055722
Short name	T567
Test name
Test status
Simulation time	382782400 ps
CPU time	951.23 seconds
Started	Jul 10 07:25:00 PM PDT 24
Finished	Jul 10 07:40:55 PM PDT 24
Peak memory	283884 kb
Host	smart-1777d60a-c075-4306-b579-6bd28f9e2d37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=316055722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.316055722
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.538850594
Short name	T783
Test name
Test status
Simulation time	285823200 ps
CPU time	31.59 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:25:55 PM PDT 24
Peak memory	275656 kb
Host	smart-b900782e-8bf0-4434-a86d-2db4100e8dc1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538850594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.538850594
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.4221490429
Short name	T726
Test name
Test status
Simulation time	4155938200 ps
CPU time	118.32 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:27:05 PM PDT 24
Peak memory	281748 kb
Host	smart-4fd74c11-7628-44dc-b822-aabd6d53b240
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221490429 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_ro.4221490429
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.1341013392
Short name	T930
Test name
Test status
Simulation time	2533355400 ps
CPU time	121.09 seconds
Started	Jul 10 07:25:05 PM PDT 24
Finished	Jul 10 07:27:08 PM PDT 24
Peak memory	281812 kb
Host	smart-2ae68203-1d68-4889-be43-3a9bd02c131e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1341013392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.1341013392
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.3079593786
Short name	T657
Test name
Test status
Simulation time	592825300 ps
CPU time	119.07 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:27:22 PM PDT 24
Peak memory	290400 kb
Host	smart-391a0054-9036-4f7b-8ab3-87eb48d95756
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079593786 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3079593786
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.3481268907
Short name	T435
Test name
Test status
Simulation time	8262935300 ps
CPU time	545.44 seconds
Started	Jul 10 07:25:03 PM PDT 24
Finished	Jul 10 07:34:12 PM PDT 24
Peak memory	314532 kb
Host	smart-0e956511-b718-464a-92f8-ddf46f1ff821
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481268907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.flash_ctrl_rw.3481268907
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_derr.1095738341
Short name	T663
Test name
Test status
Simulation time	13019673400 ps
CPU time	638.47 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:35:43 PM PDT 24
Peak memory	330956 kb
Host	smart-f52ce30c-1347-4d7d-b5be-b3570f3d7c55
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095738341 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 6.flash_ctrl_rw_derr.1095738341
Directory	/workspace/6.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.1493616134
Short name	T722
Test name
Test status
Simulation time	92191700 ps
CPU time	27.77 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:25:51 PM PDT 24
Peak memory	268444 kb
Host	smart-3e82f208-413c-4f8c-88fb-02f63fdd36b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493616134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.1493616134
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2856489567
Short name	T939
Test name
Test status
Simulation time	60568700 ps
CPU time	32.61 seconds
Started	Jul 10 07:25:05 PM PDT 24
Finished	Jul 10 07:25:40 PM PDT 24
Peak memory	268512 kb
Host	smart-a819dc08-1e08-40cd-9efd-cca799f6b347
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856489567 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.2856489567
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.274758872
Short name	T794
Test name
Test status
Simulation time	6784619800 ps
CPU time	664.56 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:36:11 PM PDT 24
Peak memory	313008 kb
Host	smart-f86176c3-892c-4736-b374-b672ef8c643a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274758872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_se rr.274758872
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.2257852528
Short name	T860
Test name
Test status
Simulation time	5248748500 ps
CPU time	61.27 seconds
Started	Jul 10 07:25:03 PM PDT 24
Finished	Jul 10 07:26:07 PM PDT 24
Peak memory	264744 kb
Host	smart-7501f9f1-f074-4e51-a938-5fca13276c4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257852528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2257852528
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.2766790448
Short name	T41
Test name
Test status
Simulation time	15277500 ps
CPU time	51.92 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:25:57 PM PDT 24
Peak memory	271328 kb
Host	smart-7c42cfab-6ef1-4973-92fa-5ef5a6f9f8c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766790448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2766790448
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.348811670
Short name	T876
Test name
Test status
Simulation time	2354870500 ps
CPU time	196.12 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:28:21 PM PDT 24
Peak memory	259504 kb
Host	smart-cbeb96ae-9e41-449d-abcb-4af58fba2c76
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348811670 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.flash_ctrl_wo.348811670
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.435483924
Short name	T442
Test name
Test status
Simulation time	29142200 ps
CPU time	13.67 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:33 PM PDT 24
Peak memory	274912 kb
Host	smart-68b7c424-01f0-43d5-93c6-21face86234c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435483924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.435483924
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.131176936
Short name	T810
Test name
Test status
Simulation time	248772500 ps
CPU time	110.54 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:11 PM PDT 24
Peak memory	261072 kb
Host	smart-6432057d-ab25-4b4e-92a7-9007337d72cc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131176936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot p_reset.131176936
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.790960068
Short name	T489
Test name
Test status
Simulation time	14595100 ps
CPU time	15.82 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:30:37 PM PDT 24
Peak memory	275048 kb
Host	smart-4431bc21-f201-48de-95c8-19551e720051
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790960068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.790960068
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.1891096506
Short name	T477
Test name
Test status
Simulation time	158062900 ps
CPU time	131.34 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:32:31 PM PDT 24
Peak memory	260128 kb
Host	smart-828db010-afff-41d5-b92b-250bc270ed1b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891096506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.1891096506
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.1872688831
Short name	T887
Test name
Test status
Simulation time	182715800 ps
CPU time	13.29 seconds
Started	Jul 10 07:30:17 PM PDT 24
Finished	Jul 10 07:30:32 PM PDT 24
Peak memory	274932 kb
Host	smart-8d018d68-9ed8-4713-845f-153fef72bfbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872688831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1872688831
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.3528307446
Short name	T633
Test name
Test status
Simulation time	82388400 ps
CPU time	131.62 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:32 PM PDT 24
Peak memory	260164 kb
Host	smart-3dd37dd0-692c-4746-bc43-723f1960a6b7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528307446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.3528307446
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.377809496
Short name	T544
Test name
Test status
Simulation time	13732000 ps
CPU time	13.29 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:33 PM PDT 24
Peak memory	274960 kb
Host	smart-bb680da2-98e9-40e6-be22-0efd2a438978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377809496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.377809496
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.2719467806
Short name	T167
Test name
Test status
Simulation time	59402700 ps
CPU time	110.59 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:32:09 PM PDT 24
Peak memory	264784 kb
Host	smart-2fc1ee2d-281b-40c1-85d8-4ce5ebbcb6d7
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719467806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o tp_reset.2719467806
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.2781020053
Short name	T642
Test name
Test status
Simulation time	29385400 ps
CPU time	15.88 seconds
Started	Jul 10 07:30:22 PM PDT 24
Finished	Jul 10 07:30:39 PM PDT 24
Peak memory	284364 kb
Host	smart-959d521e-b149-49e2-aef1-db5fdde4de62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781020053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2781020053
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.3552452032
Short name	T846
Test name
Test status
Simulation time	128674200 ps
CPU time	111.34 seconds
Started	Jul 10 07:30:22 PM PDT 24
Finished	Jul 10 07:32:14 PM PDT 24
Peak memory	260192 kb
Host	smart-9e7b956a-a57e-4b82-b4c0-775fd8debb85
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552452032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.3552452032
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.130866425
Short name	T436
Test name
Test status
Simulation time	28947000 ps
CPU time	16.19 seconds
Started	Jul 10 07:30:21 PM PDT 24
Finished	Jul 10 07:30:39 PM PDT 24
Peak memory	274932 kb
Host	smart-3d1eadf5-50a1-4eda-a6f1-a7e1a0b3b0eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130866425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.130866425
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.38031885
Short name	T679
Test name
Test status
Simulation time	151126200 ps
CPU time	134 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:32:33 PM PDT 24
Peak memory	260368 kb
Host	smart-3376f629-7109-4aeb-9ab7-b0df07f513fa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38031885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp _reset.38031885
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.240295882
Short name	T872
Test name
Test status
Simulation time	21481300 ps
CPU time	16.25 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	284424 kb
Host	smart-590b41fd-d2af-401e-832f-8a19979d073f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240295882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.240295882
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.3180854774
Short name	T1008
Test name
Test status
Simulation time	144379700 ps
CPU time	132.26 seconds
Started	Jul 10 07:30:22 PM PDT 24
Finished	Jul 10 07:32:35 PM PDT 24
Peak memory	261100 kb
Host	smart-72e0b52d-fad5-4683-a874-d3dc9c56bbbb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180854774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o tp_reset.3180854774
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.569958037
Short name	T795
Test name
Test status
Simulation time	74041400 ps
CPU time	16.16 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:35 PM PDT 24
Peak memory	284348 kb
Host	smart-657a571e-d8a9-4ad4-bf66-8a937d2e4d9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=569958037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.569958037
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.3154577135
Short name	T1072
Test name
Test status
Simulation time	129779000 ps
CPU time	133.08 seconds
Started	Jul 10 07:30:22 PM PDT 24
Finished	Jul 10 07:32:36 PM PDT 24
Peak memory	260236 kb
Host	smart-79e6a43f-c0cc-4334-9785-bd6038128119
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154577135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.3154577135
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.380699493
Short name	T423
Test name
Test status
Simulation time	24256000 ps
CPU time	15.57 seconds
Started	Jul 10 07:30:21 PM PDT 24
Finished	Jul 10 07:30:38 PM PDT 24
Peak memory	284468 kb
Host	smart-fe22a65e-d729-43ce-860f-df8f581de22d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380699493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.380699493
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.3880624118
Short name	T352
Test name
Test status
Simulation time	76568600 ps
CPU time	110.04 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:10 PM PDT 24
Peak memory	260296 kb
Host	smart-a84b7a03-8645-4409-b579-68aefe952b3f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880624118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.3880624118
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.1709410179
Short name	T403
Test name
Test status
Simulation time	42598300 ps
CPU time	13.42 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:33 PM PDT 24
Peak memory	284428 kb
Host	smart-4f102b00-93e1-460f-90e7-ef676d8b38a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709410179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1709410179
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.3655349905
Short name	T628
Test name
Test status
Simulation time	93807400 ps
CPU time	130.33 seconds
Started	Jul 10 07:30:17 PM PDT 24
Finished	Jul 10 07:32:29 PM PDT 24
Peak memory	261180 kb
Host	smart-5bfb3a27-4360-4d35-aa84-e814051c464d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655349905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.3655349905
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.3778879671
Short name	T97
Test name
Test status
Simulation time	153370900 ps
CPU time	13.75 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:25:44 PM PDT 24
Peak memory	258360 kb
Host	smart-c31c4fed-a155-4e59-ad81-055dffe3c607
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778879671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3 778879671
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.819683738
Short name	T739
Test name
Test status
Simulation time	48588900 ps
CPU time	13.62 seconds
Started	Jul 10 07:25:31 PM PDT 24
Finished	Jul 10 07:25:45 PM PDT 24
Peak memory	274812 kb
Host	smart-bbe41119-14f1-4f94-81dc-e7d5d68a3dbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819683738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.819683738
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.725094179
Short name	T753
Test name
Test status
Simulation time	10496900 ps
CPU time	20.17 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:25:42 PM PDT 24
Peak memory	273636 kb
Host	smart-a53f798c-3d0b-4af0-9f27-09aaa9b1fd16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725094179 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.725094179
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.3413793919
Short name	T212
Test name
Test status
Simulation time	20960365100 ps
CPU time	2506.95 seconds
Started	Jul 10 07:25:09 PM PDT 24
Finished	Jul 10 08:06:57 PM PDT 24
Peak memory	264992 kb
Host	smart-ad594d42-bb6f-4c21-9964-9d25f409c797
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3413793919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3413793919
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.4188403164
Short name	T684
Test name
Test status
Simulation time	1431453300 ps
CPU time	881.56 seconds
Started	Jul 10 07:25:11 PM PDT 24
Finished	Jul 10 07:39:54 PM PDT 24
Peak memory	272796 kb
Host	smart-1138c3fb-0d91-4b59-a5c3-a513968acf02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188403164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.4188403164
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.207692607
Short name	T801
Test name
Test status
Simulation time	387678600 ps
CPU time	26 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:25:49 PM PDT 24
Peak memory	262492 kb
Host	smart-7bb05faa-d460-4dfe-98b5-3449c6d54189
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207692607 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.207692607
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2173711853
Short name	T160
Test name
Test status
Simulation time	10020504900 ps
CPU time	71.99 seconds
Started	Jul 10 07:25:27 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	299064 kb
Host	smart-5d6c10f5-687b-46cd-9ce7-3fc968fed778
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173711853 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2173711853
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1920307346
Short name	T768
Test name
Test status
Simulation time	27180400 ps
CPU time	13.66 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:25:44 PM PDT 24
Peak memory	265068 kb
Host	smart-c44905e8-7e0f-4e11-8db2-5ed3296e60ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920307346 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1920307346
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.382634672
Short name	T590
Test name
Test status
Simulation time	760549851400 ps
CPU time	1025.39 seconds
Started	Jul 10 07:25:05 PM PDT 24
Finished	Jul 10 07:42:13 PM PDT 24
Peak memory	265156 kb
Host	smart-3989ee7c-dc5c-42dc-ab44-be10c62966c5
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382634672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.flash_ctrl_hw_rma_reset.382634672
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.2994160270
Short name	T418
Test name
Test status
Simulation time	3432886700 ps
CPU time	138.14 seconds
Started	Jul 10 07:25:05 PM PDT 24
Finished	Jul 10 07:27:25 PM PDT 24
Peak memory	263044 kb
Host	smart-c4f66874-bba6-4371-bbf8-17868986923a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994160270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.2994160270
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.3585301571
Short name	T937
Test name
Test status
Simulation time	3310942800 ps
CPU time	130.4 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:27:34 PM PDT 24
Peak memory	293964 kb
Host	smart-1a58c240-899a-46ea-a93f-f9549d4bff30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585301571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.3585301571
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3488318823
Short name	T310
Test name
Test status
Simulation time	120046517800 ps
CPU time	354.43 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:31:19 PM PDT 24
Peak memory	284792 kb
Host	smart-b2f920d8-20d9-40bf-a731-8de21181d880
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488318823 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3488318823
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.3829067997
Short name	T620
Test name
Test status
Simulation time	7864010400 ps
CPU time	70.04 seconds
Started	Jul 10 07:25:22 PM PDT 24
Finished	Jul 10 07:26:35 PM PDT 24
Peak memory	265212 kb
Host	smart-de86e95a-0a6a-4ce7-895a-f064f91a99b3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829067997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.3829067997
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2497092545
Short name	T818
Test name
Test status
Simulation time	76580045900 ps
CPU time	206.07 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:28:50 PM PDT 24
Peak memory	265228 kb
Host	smart-fb3c8f3b-2141-4cde-bc55-635d0dc658cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249 7092545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2497092545
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.2117814914
Short name	T778
Test name
Test status
Simulation time	7581682100 ps
CPU time	71.72 seconds
Started	Jul 10 07:25:14 PM PDT 24
Finished	Jul 10 07:26:26 PM PDT 24
Peak memory	262780 kb
Host	smart-898a51af-c393-4a18-a4b3-fd636c332143
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117814914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2117814914
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3430521815
Short name	T492
Test name
Test status
Simulation time	29591700 ps
CPU time	13.46 seconds
Started	Jul 10 07:25:29 PM PDT 24
Finished	Jul 10 07:25:44 PM PDT 24
Peak memory	265020 kb
Host	smart-c7e823b1-0968-4796-a4c1-b98c7aa9ce8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430521815 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3430521815
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.1349644244
Short name	T1059
Test name
Test status
Simulation time	11392382800 ps
CPU time	324.15 seconds
Started	Jul 10 07:25:04 PM PDT 24
Finished	Jul 10 07:30:31 PM PDT 24
Peak memory	274756 kb
Host	smart-ea5a02c5-eb8e-4c90-8034-f3d74c6f00be
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349644244 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.1349644244
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.3722761361
Short name	T926
Test name
Test status
Simulation time	59584500 ps
CPU time	132.56 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:27:35 PM PDT 24
Peak memory	264844 kb
Host	smart-c2d61e6f-2a38-43c5-a8ca-77bb2b27f483
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722761361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.3722761361
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.62988375
Short name	T871
Test name
Test status
Simulation time	51337300 ps
CPU time	197.14 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:28:41 PM PDT 24
Peak memory	263116 kb
Host	smart-47190a40-9438-4a5c-adb5-e75966884a42
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=62988375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.62988375
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.3818874376
Short name	T433
Test name
Test status
Simulation time	13062615700 ps
CPU time	204.75 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	265292 kb
Host	smart-f2d657cb-c181-4d53-9cc9-749d475d681c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818874376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.3818874376
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.2062878216
Short name	T1062
Test name
Test status
Simulation time	103392500 ps
CPU time	231.26 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:29:15 PM PDT 24
Peak memory	279976 kb
Host	smart-cde99c64-38ac-4b43-90bc-0b2ab0135b6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062878216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.2062878216
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.1636748877
Short name	T1064
Test name
Test status
Simulation time	270620400 ps
CPU time	35.8 seconds
Started	Jul 10 07:25:20 PM PDT 24
Finished	Jul 10 07:25:59 PM PDT 24
Peak memory	275688 kb
Host	smart-c2511d3a-d63a-4e40-ae3c-1d53e30da042
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636748877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_re_evict.1636748877
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.2136413525
Short name	T410
Test name
Test status
Simulation time	9689709000 ps
CPU time	129.14 seconds
Started	Jul 10 07:25:11 PM PDT 24
Finished	Jul 10 07:27:21 PM PDT 24
Peak memory	281244 kb
Host	smart-db6cc194-93ab-4ecb-8b38-c528caeb1027
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136413525 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.2136413525
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.2060808475
Short name	T921
Test name
Test status
Simulation time	707705900 ps
CPU time	130.88 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:27:35 PM PDT 24
Peak memory	281972 kb
Host	smart-79d06b08-6a94-4ad7-9f29-0349d55a1c03
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060808475 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2060808475
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.817809055
Short name	T90
Test name
Test status
Simulation time	57633491200 ps
CPU time	635.39 seconds
Started	Jul 10 07:25:12 PM PDT 24
Finished	Jul 10 07:35:48 PM PDT 24
Peak memory	314420 kb
Host	smart-890dbf37-f59e-4b9c-8b19-6de7e40af593
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817809055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.817809055
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.1600970397
Short name	T953
Test name
Test status
Simulation time	19991772500 ps
CPU time	599.03 seconds
Started	Jul 10 07:25:22 PM PDT 24
Finished	Jul 10 07:35:24 PM PDT 24
Peak memory	327012 kb
Host	smart-33114f2b-f142-462d-bfbd-b23f647cf7fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600970397 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_rw_derr.1600970397
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.1372548439
Short name	T461
Test name
Test status
Simulation time	33356500 ps
CPU time	28.7 seconds
Started	Jul 10 07:25:19 PM PDT 24
Finished	Jul 10 07:25:50 PM PDT 24
Peak memory	273224 kb
Host	smart-5457e33f-2a89-4c5b-b975-3b29e664b522
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372548439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.1372548439
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.806815064
Short name	T996
Test name
Test status
Simulation time	41414200 ps
CPU time	30.76 seconds
Started	Jul 10 07:25:24 PM PDT 24
Finished	Jul 10 07:25:57 PM PDT 24
Peak memory	275644 kb
Host	smart-bc153fe1-f315-48b1-b494-23e8a0c73443
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806815064 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.806815064
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.4042838863
Short name	T365
Test name
Test status
Simulation time	3187186000 ps
CPU time	66.66 seconds
Started	Jul 10 07:25:21 PM PDT 24
Finished	Jul 10 07:26:31 PM PDT 24
Peak memory	263724 kb
Host	smart-63ae1573-d5ad-4129-aeb1-af7565bde872
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042838863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.4042838863
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.2743461387
Short name	T1037
Test name
Test status
Simulation time	20247200 ps
CPU time	99.43 seconds
Started	Jul 10 07:25:01 PM PDT 24
Finished	Jul 10 07:26:44 PM PDT 24
Peak memory	277272 kb
Host	smart-ae043efc-bbf4-4f2b-b768-a821a06a8aed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743461387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2743461387
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.3704221050
Short name	T811
Test name
Test status
Simulation time	6145803900 ps
CPU time	144.56 seconds
Started	Jul 10 07:25:12 PM PDT 24
Finished	Jul 10 07:27:38 PM PDT 24
Peak memory	265312 kb
Host	smart-7d67c825-2c8a-4b64-82d4-756698bab049
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704221050 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.3704221050
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.2988780637
Short name	T1095
Test name
Test status
Simulation time	27168200 ps
CPU time	13.77 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:30:43 PM PDT 24
Peak memory	274944 kb
Host	smart-ff8e3bbe-6929-4d0a-b8ca-62ed74b9906a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988780637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2988780637
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.274438646
Short name	T594
Test name
Test status
Simulation time	128735500 ps
CPU time	110.55 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:11 PM PDT 24
Peak memory	263232 kb
Host	smart-5f70808d-9381-4d1b-981b-e3cd4635fc1b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274438646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot p_reset.274438646
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.3440674273
Short name	T438
Test name
Test status
Simulation time	16922300 ps
CPU time	16.28 seconds
Started	Jul 10 07:30:18 PM PDT 24
Finished	Jul 10 07:30:36 PM PDT 24
Peak memory	275008 kb
Host	smart-1aa4f868-9740-4c82-b4bd-0044e95ab259
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3440674273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3440674273
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.1192775137
Short name	T1025
Test name
Test status
Simulation time	380613100 ps
CPU time	130.64 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:32 PM PDT 24
Peak memory	261076 kb
Host	smart-80889f94-1285-4810-87cd-9c03fb7ba708
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192775137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.1192775137
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.747389703
Short name	T857
Test name
Test status
Simulation time	47114700 ps
CPU time	16.1 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:30:38 PM PDT 24
Peak memory	274904 kb
Host	smart-5914fef6-a891-4b44-82e8-be33d632b5bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747389703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.747389703
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.2934320852
Short name	T765
Test name
Test status
Simulation time	45836300 ps
CPU time	108.25 seconds
Started	Jul 10 07:30:23 PM PDT 24
Finished	Jul 10 07:32:13 PM PDT 24
Peak memory	265428 kb
Host	smart-2fa55560-c446-468c-b119-14e61fd52d0d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934320852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.2934320852
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.372169962
Short name	T800
Test name
Test status
Simulation time	23795300 ps
CPU time	16.31 seconds
Started	Jul 10 07:30:28 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	274840 kb
Host	smart-3f7f5982-ebf4-438b-85e9-57b3436af7d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372169962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.372169962
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.193180638
Short name	T163
Test name
Test status
Simulation time	147087900 ps
CPU time	132.22 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:32 PM PDT 24
Peak memory	260356 kb
Host	smart-d0836cd4-5250-4cf8-9072-9e84b7e12167
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193180638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_ot p_reset.193180638
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.2257410644
Short name	T1004
Test name
Test status
Simulation time	15196900 ps
CPU time	13.27 seconds
Started	Jul 10 07:30:20 PM PDT 24
Finished	Jul 10 07:30:35 PM PDT 24
Peak memory	275044 kb
Host	smart-a69a6236-1f84-4652-a7ea-f04f004d16d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257410644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2257410644
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.1737772125
Short name	T901
Test name
Test status
Simulation time	36012900 ps
CPU time	110.83 seconds
Started	Jul 10 07:30:19 PM PDT 24
Finished	Jul 10 07:32:11 PM PDT 24
Peak memory	260392 kb
Host	smart-84b68358-3ba8-4795-8e3d-6c164efd7763
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737772125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o tp_reset.1737772125
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.1330351400
Short name	T888
Test name
Test status
Simulation time	16809500 ps
CPU time	15.65 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	275036 kb
Host	smart-a10fea49-5092-43f4-9f75-8c661008433b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330351400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1330351400
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.3669329494
Short name	T723
Test name
Test status
Simulation time	146164900 ps
CPU time	132.09 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:32:43 PM PDT 24
Peak memory	260180 kb
Host	smart-75f27fef-a8b3-41d2-85a8-71b345994c0e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669329494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o tp_reset.3669329494
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.975036272
Short name	T401
Test name
Test status
Simulation time	44469700 ps
CPU time	15.94 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:30:46 PM PDT 24
Peak memory	284248 kb
Host	smart-eb3e2e8f-143e-4576-aa52-251e215bfd6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=975036272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.975036272
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.153610658
Short name	T476
Test name
Test status
Simulation time	92223600 ps
CPU time	109.72 seconds
Started	Jul 10 07:30:32 PM PDT 24
Finished	Jul 10 07:32:23 PM PDT 24
Peak memory	260160 kb
Host	smart-516f11e3-31fc-4223-8eec-3ef647e58634
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153610658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot p_reset.153610658
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.2658734244
Short name	T1014
Test name
Test status
Simulation time	21862500 ps
CPU time	15.83 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	274872 kb
Host	smart-08d1499a-3352-462f-bd24-1360c932bdf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658734244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2658734244
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.864348839
Short name	T596
Test name
Test status
Simulation time	144316300 ps
CPU time	111.69 seconds
Started	Jul 10 07:30:29 PM PDT 24
Finished	Jul 10 07:32:22 PM PDT 24
Peak memory	265140 kb
Host	smart-611f4ccd-409e-45d3-9db8-fe63f6da30f8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864348839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_ot p_reset.864348839
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.2257209574
Short name	T623
Test name
Test status
Simulation time	13474800 ps
CPU time	15.57 seconds
Started	Jul 10 07:30:28 PM PDT 24
Finished	Jul 10 07:30:44 PM PDT 24
Peak memory	274912 kb
Host	smart-8240e40c-1d56-402f-967e-4aea1ac7b4e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257209574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2257209574
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.2089753537
Short name	T640
Test name
Test status
Simulation time	74327400 ps
CPU time	130.76 seconds
Started	Jul 10 07:30:31 PM PDT 24
Finished	Jul 10 07:32:42 PM PDT 24
Peak memory	265156 kb
Host	smart-54d74885-9108-45b0-a4fa-a00e2f968cdd
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089753537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o tp_reset.2089753537
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.2980944719
Short name	T1087
Test name
Test status
Simulation time	25451400 ps
CPU time	13.71 seconds
Started	Jul 10 07:30:30 PM PDT 24
Finished	Jul 10 07:30:45 PM PDT 24
Peak memory	284372 kb
Host	smart-a3915eb1-5cfb-4b12-aad8-e66fd84df036
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980944719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2980944719
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.2166978589
Short name	T894
Test name
Test status
Simulation time	35737200 ps
CPU time	109.48 seconds
Started	Jul 10 07:30:30 PM PDT 24
Finished	Jul 10 07:32:20 PM PDT 24
Peak memory	264704 kb
Host	smart-624c618a-e67b-4928-9c58-74c254950f4d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166978589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.2166978589
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.3529269801
Short name	T18
Test name
Test status
Simulation time	196933600 ps
CPU time	14.09 seconds
Started	Jul 10 07:25:37 PM PDT 24
Finished	Jul 10 07:25:52 PM PDT 24
Peak memory	258308 kb
Host	smart-6f375298-9e00-4c96-941d-719e14174a61
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529269801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3 529269801
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.771837877
Short name	T775
Test name
Test status
Simulation time	55130400 ps
CPU time	16.36 seconds
Started	Jul 10 07:25:37 PM PDT 24
Finished	Jul 10 07:25:55 PM PDT 24
Peak memory	284272 kb
Host	smart-e45a9dd8-fafd-413e-94e1-0e00edf9955e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771837877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.771837877
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.1308153508
Short name	T81
Test name
Test status
Simulation time	26385500 ps
CPU time	20.72 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:25:58 PM PDT 24
Peak memory	273648 kb
Host	smart-c9e675e5-d5a1-4735-afee-5b18465cc819
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308153508 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.1308153508
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.1758360207
Short name	T797
Test name
Test status
Simulation time	6495188200 ps
CPU time	2647.69 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 08:09:37 PM PDT 24
Peak memory	262864 kb
Host	smart-ef1fe1a2-c114-4551-b1c7-73b7c5bf82b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1758360207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1758360207
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.4279115616
Short name	T752
Test name
Test status
Simulation time	1762501200 ps
CPU time	884.72 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:40:15 PM PDT 24
Peak memory	273140 kb
Host	smart-2ec50273-0555-45d2-9995-41cb8cba5f36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4279115616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.4279115616
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.2448460465
Short name	T459
Test name
Test status
Simulation time	711163200 ps
CPU time	22.58 seconds
Started	Jul 10 07:25:33 PM PDT 24
Finished	Jul 10 07:25:57 PM PDT 24
Peak memory	262580 kb
Host	smart-8360c870-ceb6-40bf-84f3-85aa567ca566
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448460465 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2448460465
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3029974733
Short name	T843
Test name
Test status
Simulation time	10034241300 ps
CPU time	52.34 seconds
Started	Jul 10 07:25:35 PM PDT 24
Finished	Jul 10 07:26:28 PM PDT 24
Peak memory	277700 kb
Host	smart-455ece72-445b-4ac3-a8da-94ed5e16e02a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029974733 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3029974733
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3511196737
Short name	T146
Test name
Test status
Simulation time	15335800 ps
CPU time	13.56 seconds
Started	Jul 10 07:25:40 PM PDT 24
Finished	Jul 10 07:25:54 PM PDT 24
Peak memory	265032 kb
Host	smart-5eeca993-c8c0-49af-8ae2-4555e3eb5214
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511196737 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3511196737
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.4193334553
Short name	T156
Test name
Test status
Simulation time	160175741700 ps
CPU time	876.72 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:40:06 PM PDT 24
Peak memory	264392 kb
Host	smart-00dfd0f9-1a6e-4aed-a5b3-f0a463973d7c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193334553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.4193334553
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.26470174
Short name	T498
Test name
Test status
Simulation time	9369060100 ps
CPU time	199.06 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:28:49 PM PDT 24
Peak memory	262848 kb
Host	smart-d55582ea-c17f-4d9a-8fd4-da0cb819e06b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26470174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_ sec_otp.26470174
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.851340579
Short name	T1052
Test name
Test status
Simulation time	864711000 ps
CPU time	127.38 seconds
Started	Jul 10 07:25:35 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	293928 kb
Host	smart-38aca7f3-88bf-4857-a8c3-a7518b9efb7d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851340579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash _ctrl_intr_rd.851340579
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1672522142
Short name	T396
Test name
Test status
Simulation time	24489175000 ps
CPU time	254.68 seconds
Started	Jul 10 07:25:34 PM PDT 24
Finished	Jul 10 07:29:50 PM PDT 24
Peak memory	290960 kb
Host	smart-d9bab0ad-8b38-460e-b782-8734ca380b8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672522142 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1672522142
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.1249319523
Short name	T613
Test name
Test status
Simulation time	5067235200 ps
CPU time	77.86 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:26:56 PM PDT 24
Peak memory	265348 kb
Host	smart-7b26857b-4b9f-4ead-afb7-5fbf8fade903
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249319523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.1249319523
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3968664726
Short name	T858
Test name
Test status
Simulation time	27819516200 ps
CPU time	189.68 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:28:47 PM PDT 24
Peak memory	265420 kb
Host	smart-4f0e200b-646b-409c-b814-51490eb99c32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396 8664726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3968664726
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.496330313
Short name	T132
Test name
Test status
Simulation time	4263427800 ps
CPU time	71.81 seconds
Started	Jul 10 07:25:27 PM PDT 24
Finished	Jul 10 07:26:40 PM PDT 24
Peak memory	262616 kb
Host	smart-c166b7c7-d1fa-4e29-b4ac-8046d183036a
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496330313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.496330313
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1044502780
Short name	T1024
Test name
Test status
Simulation time	52183700 ps
CPU time	13.38 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:25:51 PM PDT 24
Peak memory	260248 kb
Host	smart-e1e79d9f-9afc-4944-aa5d-fe7dd8a6e56b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044502780 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.1044502780
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.1447143026
Short name	T624
Test name
Test status
Simulation time	40207178500 ps
CPU time	302.71 seconds
Started	Jul 10 07:25:29 PM PDT 24
Finished	Jul 10 07:30:34 PM PDT 24
Peak memory	274788 kb
Host	smart-e56b3114-89a6-400b-97ae-4c6db74e1a74
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447143026 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.1447143026
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.2719522320
Short name	T428
Test name
Test status
Simulation time	39502400 ps
CPU time	133.53 seconds
Started	Jul 10 07:25:29 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	260352 kb
Host	smart-4dbe652c-646d-44ac-9285-b205e571aabb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719522320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.2719522320
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.2493916046
Short name	T40
Test name
Test status
Simulation time	768976200 ps
CPU time	203.45 seconds
Started	Jul 10 07:25:27 PM PDT 24
Finished	Jul 10 07:28:52 PM PDT 24
Peak memory	263192 kb
Host	smart-17cb81b2-a55a-4682-9d78-167a925a7d1c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2493916046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.2493916046
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.3775199363
Short name	T632
Test name
Test status
Simulation time	77520400 ps
CPU time	13.85 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:25:52 PM PDT 24
Peak memory	265320 kb
Host	smart-cb1b567e-90b5-459a-a5c3-9ef025fd4efb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775199363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.3775199363
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.3342728891
Short name	T769
Test name
Test status
Simulation time	884075100 ps
CPU time	1067.36 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:43:17 PM PDT 24
Peak memory	286252 kb
Host	smart-19eab12a-54d1-4028-8e96-9e39705a64d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342728891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3342728891
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.3961807514
Short name	T198
Test name
Test status
Simulation time	119030400 ps
CPU time	32.56 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:26:10 PM PDT 24
Peak memory	275688 kb
Host	smart-0e815de8-9fd7-424e-b92c-185dfdda89d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961807514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.3961807514
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.2096409474
Short name	T744
Test name
Test status
Simulation time	1096776800 ps
CPU time	129.26 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:27:39 PM PDT 24
Peak memory	289996 kb
Host	smart-d879fc20-e127-4564-b92e-e6d2385678e6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096409474 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.2096409474
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.3007630563
Short name	T987
Test name
Test status
Simulation time	5213619200 ps
CPU time	131.07 seconds
Started	Jul 10 07:25:35 PM PDT 24
Finished	Jul 10 07:27:47 PM PDT 24
Peak memory	295192 kb
Host	smart-368b38c1-74b0-425a-aaf5-ba9c0c8a4f99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007630563 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3007630563
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.2233136010
Short name	T815
Test name
Test status
Simulation time	10178292500 ps
CPU time	608.65 seconds
Started	Jul 10 07:25:38 PM PDT 24
Finished	Jul 10 07:35:48 PM PDT 24
Peak memory	329832 kb
Host	smart-32f93641-61c8-48d9-9d47-84ed2d31bda6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233136010 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_rw_derr.2233136010
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.4268006908
Short name	T268
Test name
Test status
Simulation time	352404300 ps
CPU time	30.49 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:26:07 PM PDT 24
Peak memory	268504 kb
Host	smart-e44fa353-4253-4742-a56c-e3b6b32eed8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268006908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_rw_evict.4268006908
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3367662736
Short name	T413
Test name
Test status
Simulation time	73095100 ps
CPU time	28.4 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:26:06 PM PDT 24
Peak memory	268508 kb
Host	smart-1382744b-b691-4d9c-b254-96970317de9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367662736 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3367662736
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.1098085479
Short name	T779
Test name
Test status
Simulation time	16823743500 ps
CPU time	558.67 seconds
Started	Jul 10 07:25:38 PM PDT 24
Finished	Jul 10 07:34:57 PM PDT 24
Peak memory	312776 kb
Host	smart-2f1a7cab-4dcf-4949-bb3d-6c540ef98c3e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098085479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s err.1098085479
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.1788063627
Short name	T30
Test name
Test status
Simulation time	347828900 ps
CPU time	51.58 seconds
Started	Jul 10 07:25:38 PM PDT 24
Finished	Jul 10 07:26:30 PM PDT 24
Peak memory	263600 kb
Host	smart-50785449-afd1-493b-bfd2-c177d5e392d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788063627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1788063627
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.119778561
Short name	T527
Test name
Test status
Simulation time	44849700 ps
CPU time	99.5 seconds
Started	Jul 10 07:25:28 PM PDT 24
Finished	Jul 10 07:27:09 PM PDT 24
Peak memory	277636 kb
Host	smart-b6713ecc-2f14-4324-bd19-1bb840d9750b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=119778561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.119778561
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.3733016977
Short name	T776
Test name
Test status
Simulation time	9438726500 ps
CPU time	204.71 seconds
Started	Jul 10 07:25:31 PM PDT 24
Finished	Jul 10 07:28:56 PM PDT 24
Peak memory	259924 kb
Host	smart-8566bded-6350-468d-88c3-ff21b28e60df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733016977 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_wo.3733016977
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.3665147544
Short name	T793
Test name
Test status
Simulation time	32293100 ps
CPU time	13.68 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:16 PM PDT 24
Peak memory	258260 kb
Host	smart-39d6b3c3-84d5-4570-b7e2-1c1c63386c02
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665147544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3 665147544
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.3340962914
Short name	T886
Test name
Test status
Simulation time	77851100 ps
CPU time	13.45 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:17 PM PDT 24
Peak memory	274828 kb
Host	smart-f5e3623f-b395-4f5e-91b3-4a41a2469363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340962914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3340962914
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.3082118715
Short name	T335
Test name
Test status
Simulation time	17619800 ps
CPU time	20.76 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:24 PM PDT 24
Peak memory	273636 kb
Host	smart-3d15f352-8e68-40b8-a32b-bdf4d957d5ca
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082118715 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.3082118715
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.1514028945
Short name	T990
Test name
Test status
Simulation time	25149483000 ps
CPU time	2615.99 seconds
Started	Jul 10 07:25:46 PM PDT 24
Finished	Jul 10 08:09:23 PM PDT 24
Peak memory	262872 kb
Host	smart-4e982054-c8d9-4316-afd0-3dc02797c9c5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1514028945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1514028945
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.3633512792
Short name	T1090
Test name
Test status
Simulation time	392506400 ps
CPU time	944.79 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:41:34 PM PDT 24
Peak memory	273444 kb
Host	smart-518d1150-b17c-4a5e-a8c1-e5a560363fed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633512792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3633512792
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.3793752986
Short name	T7
Test name
Test status
Simulation time	125451600 ps
CPU time	22.87 seconds
Started	Jul 10 07:25:39 PM PDT 24
Finished	Jul 10 07:26:02 PM PDT 24
Peak memory	263536 kb
Host	smart-47479b03-ec01-4a0e-aacc-d3da0cb0d592
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793752986 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3793752986
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2641640274
Short name	T273
Test name
Test status
Simulation time	10020010500 ps
CPU time	63.8 seconds
Started	Jul 10 07:26:00 PM PDT 24
Finished	Jul 10 07:27:05 PM PDT 24
Peak memory	265484 kb
Host	smart-c7dc8e17-5cf4-474e-8e24-59a8cf56621a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641640274 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2641640274
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2098085059
Short name	T169
Test name
Test status
Simulation time	160175838100 ps
CPU time	892.69 seconds
Started	Jul 10 07:25:37 PM PDT 24
Finished	Jul 10 07:40:31 PM PDT 24
Peak memory	261028 kb
Host	smart-24dd0ea4-8482-4b49-b652-3d5021d7d422
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098085059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.2098085059
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.4243623651
Short name	T299
Test name
Test status
Simulation time	6034972600 ps
CPU time	123.33 seconds
Started	Jul 10 07:25:40 PM PDT 24
Finished	Jul 10 07:27:44 PM PDT 24
Peak memory	262140 kb
Host	smart-419e726c-f0eb-42b2-a613-f0dee00e4cc8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243623651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h w_sec_otp.4243623651
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.3465870178
Short name	T313
Test name
Test status
Simulation time	751014900 ps
CPU time	108.54 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:27:37 PM PDT 24
Peak memory	294228 kb
Host	smart-25f0ee03-1c10-41a6-9007-ea6b78cc25bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465870178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.3465870178
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3156657926
Short name	T965
Test name
Test status
Simulation time	8520874000 ps
CPU time	154.56 seconds
Started	Jul 10 07:25:49 PM PDT 24
Finished	Jul 10 07:28:25 PM PDT 24
Peak memory	294360 kb
Host	smart-83b51f10-3d55-4c92-bb3f-cccf229f8540
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156657926 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3156657926
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.1533738547
Short name	T820
Test name
Test status
Simulation time	5520506600 ps
CPU time	88.66 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:27:18 PM PDT 24
Peak memory	260688 kb
Host	smart-4d419e07-9bb5-4ca1-aedb-dc05fc964416
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533738547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.1533738547
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.813480503
Short name	T941
Test name
Test status
Simulation time	22679279900 ps
CPU time	185.06 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:28:54 PM PDT 24
Peak memory	259884 kb
Host	smart-912e5712-db85-479c-821a-c98289d28b8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813 480503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.813480503
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.1308764033
Short name	T781
Test name
Test status
Simulation time	8390850500 ps
CPU time	79.4 seconds
Started	Jul 10 07:25:51 PM PDT 24
Finished	Jul 10 07:27:11 PM PDT 24
Peak memory	262724 kb
Host	smart-9e8fbd11-68cd-4ec9-9016-d399ad9ab039
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308764033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1308764033
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1935743699
Short name	T149
Test name
Test status
Simulation time	25952400 ps
CPU time	13.45 seconds
Started	Jul 10 07:26:04 PM PDT 24
Finished	Jul 10 07:26:18 PM PDT 24
Peak memory	265116 kb
Host	smart-701b1256-3bbb-4468-b57a-b577ccce26f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935743699 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1935743699
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.1737820507
Short name	T683
Test name
Test status
Simulation time	12252461500 ps
CPU time	893.51 seconds
Started	Jul 10 07:25:39 PM PDT 24
Finished	Jul 10 07:40:33 PM PDT 24
Peak memory	274004 kb
Host	smart-3c278536-a445-4364-a224-16327550823f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737820507 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.1737820507
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.2183727941
Short name	T659
Test name
Test status
Simulation time	1405982900 ps
CPU time	125.22 seconds
Started	Jul 10 07:25:36 PM PDT 24
Finished	Jul 10 07:27:42 PM PDT 24
Peak memory	263224 kb
Host	smart-81f2eeb9-2657-4027-bca4-5e5c366b8917
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2183727941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2183727941
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.4058040725
Short name	T763
Test name
Test status
Simulation time	80027900 ps
CPU time	13.76 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:26:03 PM PDT 24
Peak memory	259164 kb
Host	smart-539dacde-d797-4cee-b977-4940bf6e48de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058040725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.4058040725
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.456865080
Short name	T144
Test name
Test status
Simulation time	170033400 ps
CPU time	353.98 seconds
Started	Jul 10 07:25:37 PM PDT 24
Finished	Jul 10 07:31:32 PM PDT 24
Peak memory	281640 kb
Host	smart-41064be3-01fd-4421-aba8-dc2091ff05e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456865080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.456865080
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.1098350561
Short name	T1055
Test name
Test status
Simulation time	182869000 ps
CPU time	30.88 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:26:34 PM PDT 24
Peak memory	275688 kb
Host	smart-418017e0-2786-449d-896a-70134b9887b9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098350561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.1098350561
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.689611871
Short name	T228
Test name
Test status
Simulation time	576319100 ps
CPU time	141.97 seconds
Started	Jul 10 07:25:49 PM PDT 24
Finished	Jul 10 07:28:12 PM PDT 24
Peak memory	281936 kb
Host	smart-c8747d14-0959-448a-a728-eace36270500
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 689611871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.689611871
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.3737168372
Short name	T98
Test name
Test status
Simulation time	453040900 ps
CPU time	118.38 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:27:47 PM PDT 24
Peak memory	281808 kb
Host	smart-3f37a5e9-0eea-4796-8c67-8de15f5c3ed9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737168372 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3737168372
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.2399564461
Short name	T425
Test name
Test status
Simulation time	12789059200 ps
CPU time	539.36 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:34:49 PM PDT 24
Peak memory	310064 kb
Host	smart-77cf8912-24f2-4c82-a624-2e36a417a528
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399564461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.flash_ctrl_rw.2399564461
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict.3336347828
Short name	T1056
Test name
Test status
Simulation time	70451300 ps
CPU time	30.7 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:26:19 PM PDT 24
Peak memory	275676 kb
Host	smart-339bf4ae-bc62-4f3e-82e9-d528c1854bf7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336347828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_rw_evict.3336347828
Directory	/workspace/9.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1778970490
Short name	T25
Test name
Test status
Simulation time	66291600 ps
CPU time	29.33 seconds
Started	Jul 10 07:25:45 PM PDT 24
Finished	Jul 10 07:26:15 PM PDT 24
Peak memory	268516 kb
Host	smart-c11bbddc-8643-41f8-8809-4521ba3fb183
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778970490 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1778970490
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.1936708325
Short name	T540
Test name
Test status
Simulation time	4806477800 ps
CPU time	850.88 seconds
Started	Jul 10 07:25:49 PM PDT 24
Finished	Jul 10 07:40:01 PM PDT 24
Peak memory	320908 kb
Host	smart-beea5310-2e89-4300-a41d-6425657857d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936708325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s err.1936708325
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.1384166026
Short name	T471
Test name
Test status
Simulation time	9407276500 ps
CPU time	85.91 seconds
Started	Jul 10 07:26:02 PM PDT 24
Finished	Jul 10 07:27:29 PM PDT 24
Peak memory	263708 kb
Host	smart-9f37bce3-bd4c-45e2-9cbe-1b0b01b8fec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1384166026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1384166026
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.1625419058
Short name	T1043
Test name
Test status
Simulation time	41681200 ps
CPU time	96.32 seconds
Started	Jul 10 07:25:38 PM PDT 24
Finished	Jul 10 07:27:15 PM PDT 24
Peak memory	275796 kb
Host	smart-af7d4324-9ec0-4164-ab42-5fe553ac33eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625419058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1625419058
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.4078464607
Short name	T851
Test name
Test status
Simulation time	11836072000 ps
CPU time	215.11 seconds
Started	Jul 10 07:25:48 PM PDT 24
Finished	Jul 10 07:29:24 PM PDT 24
Peak memory	265316 kb
Host	smart-d15b9952-d8ba-453d-8d0c-7ac897da82ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078464607 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.flash_ctrl_wo.4078464607
Directory	/workspace/9.flash_ctrl_wo/latest

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