Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23856826	1		T1	2538		T2	33495		T3	503
full_word	7642596	1		T1	383		T2	473		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31499102	1		T1	2921		T2	33968		T3	505
auto[TlIntgErrCmd]	114	1		T107	9		T108	11		T239	3
auto[TlIntgErrData]	106	1		T107	5		T108	4		T239	3
auto[TlIntgErrBoth]	100	1		T107	6		T108	5		T239	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26995211	1		T1	2724		T2	33505		T3	497
auto[1]	4504211	1		T1	197		T2	463		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23175045	1		T1	2492		T2	33464		T3	496
auto[TlIntgErrNone]	partial	auto[1]	681485	1		T1	46		T2	31		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	3820021	1		T1	232		T2	41		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3822551	1		T1	151		T2	432		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T107	4		T108	3		T267	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T107	5		T108	5		T239	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T267	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T108	3		T267	1		T370	2
auto[TlIntgErrData]	partial	auto[0]	49	1		T108	3		T239	3		T267	4
auto[TlIntgErrData]	partial	auto[1]	47	1		T107	3		T267	3		T269	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T107	2		T268	1		T369	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T108	1		T366	1		T371	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T107	2		T108	3		T239	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T107	4		T108	2		T239	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T267	1		T269	1		T372	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T366	1		T268	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16016	1		T106	858		T110	910		T111	588
full_word	3967670	1		T1	18		T2	116		T6	11655

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3983391	1		T1	18		T2	116		T6	11655
auto[TlIntgErrCmd]	96	1		T107	8		T108	7		T239	3
auto[TlIntgErrData]	111	1		T107	7		T108	6		T239	5
auto[TlIntgErrBoth]	88	1		T107	4		T108	4		T239	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3963190	1		T1	18		T2	116		T6	11655
auto[1]	20496	1		T106	1093		T110	1461		T111	750

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1068	1		T106	65		T110	23		T111	24
auto[TlIntgErrNone]	partial	auto[1]	14685	1		T106	793		T110	887		T111	564
auto[TlIntgErrNone]	full_word	auto[0]	3962005	1		T1	18		T2	116		T6	11655
auto[TlIntgErrNone]	full_word	auto[1]	5633	1		T106	300		T110	574		T111	186
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T107	4		T108	1		T239	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T107	4		T108	3		T239	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T108	1		T366	2		T368	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T108	2		T366	1		T369	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T107	2		T108	4		T267	3
auto[TlIntgErrData]	partial	auto[1]	52	1		T107	4		T108	2		T239	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T239	1		T269	1		T370	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T107	1		T364	1		T370	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T107	1		T108	2		T239	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T107	2		T108	2		T267	6
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T367	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T107	1		T370	1		T373	1