SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_tb.dut.u_lc_creator_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_escalate_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_iso_part_sw_wr_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_nvm_debug_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_owner_seed_sw_rw_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_tb.dut.u_lc_seed_hw_rd_en_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 83 | 1 | T126 | 2 | T227 | 1 | T312 | 4 | |||
others[1] | 74 | 1 | T33 | 1 | T126 | 1 | T227 | 3 | |||
others[2] | 81 | 1 | T33 | 3 | T227 | 1 | T312 | 1 | |||
others[3] | 131 | 1 | T33 | 2 | T126 | 3 | T227 | 4 | |||
false | 26610 | 1 | T2 | 1 | T3 | 9 | T4 | 800 | |||
true | 21808 | 1 | T1 | 3 | T2 | 1 | T4 | 754 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 3 | 1 | T102 | 1 | T103 | 1 | T375 | 1 | |||
others[1] | 3 | 1 | T78 | 1 | T376 | 1 | T377 | 1 | |||
others[2] | 6 | 1 | T101 | 1 | T378 | 1 | T379 | 1 | |||
others[3] | 10 | 1 | T74 | 1 | T100 | 1 | T77 | 1 | |||
false | 11929 | 1 | T1 | 2 | T2 | 1 | T3 | 9 | |||
true | 2 | 1 | T380 | 1 | T381 | 1 | - | - |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2355 | 1 | T4 | 112 | T48 | 18 | T32 | 2 | |||
others[1] | 2314 | 1 | T4 | 74 | T48 | 31 | T33 | 1 | |||
others[2] | 2198 | 1 | T4 | 63 | T48 | 12 | T33 | 1 | |||
others[3] | 3861 | 1 | T4 | 150 | T48 | 55 | T33 | 1 | |||
false | 7078 | 1 | T1 | 2 | T2 | 1 | T3 | 9 | |||
true | 1514 | 1 | T1 | 1 | T2 | 1 | T6 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2258 | 1 | T4 | 89 | T48 | 22 | T32 | 2 | |||
others[1] | 2339 | 1 | T4 | 97 | T48 | 25 | T33 | 1 | |||
others[2] | 2284 | 1 | T4 | 76 | T48 | 35 | T33 | 2 | |||
others[3] | 3939 | 1 | T4 | 133 | T48 | 34 | T53 | 90 | |||
false | 7031 | 1 | T1 | 2 | T2 | 1 | T3 | 9 | |||
true | 1512 | 1 | T1 | 1 | T2 | 1 | T6 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2305 | 1 | T4 | 92 | T48 | 25 | T53 | 54 | |||
others[1] | 2245 | 1 | T4 | 79 | T48 | 21 | T53 | 47 | |||
others[2] | 2197 | 1 | T4 | 102 | T17 | 1 | T48 | 28 | |||
others[3] | 3853 | 1 | T4 | 127 | T48 | 44 | T32 | 2 | |||
false | 7533 | 1 | T1 | 2 | T2 | 1 | T3 | 9 | |||
true | 38 | 1 | T56 | 1 | T116 | 1 | T382 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 77 | 1 | T33 | 2 | T126 | 4 | T227 | 2 | |||
others[1] | 89 | 1 | T33 | 2 | T126 | 2 | T312 | 1 | |||
others[2] | 86 | 1 | T33 | 2 | T126 | 1 | T227 | 2 | |||
others[3] | 123 | 1 | T33 | 4 | T126 | 2 | T227 | 3 | |||
false | 26555 | 1 | T2 | 1 | T3 | 9 | T4 | 804 | |||
true | 21563 | 1 | T1 | 3 | T2 | 1 | T4 | 729 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 7472 | 1 | T4 | 287 | T48 | 83 | T32 | 7 | |||
others[1] | 7411 | 1 | T4 | 238 | T48 | 100 | T32 | 1 | |||
others[2] | 7292 | 1 | T4 | 255 | T48 | 74 | T32 | 3 | |||
others[3] | 12320 | 1 | T3 | 3 | T4 | 471 | T48 | 158 | |||
false | 3663 | 1 | T3 | 3 | T4 | 122 | T48 | 35 | |||
true | 18677 | 1 | T1 | 2 | T2 | 1 | T3 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |