Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1523284844	1520093096	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1523284844	400611281	0	0
GntImpliesValid_A	1523284844	400611281	0	0
GrantKnown_A	1523284844	1520093096	0	0
IdxKnown_A	1523284844	1520093096	0	0
IndexIsCorrect_A	1523284844	400611281	0	0
NoReadyValidNoGrant_A	1523284844	178433321	0	0
Priority_A	1523284844	423997708	0	0
ReadyAndValidImplyGrant_A	1523284844	400611281	0	0
ReqAndReadyImplyGrant_A	1523284844	400611281	0	0
ReqImpliesValid_A	1523284844	423997708	0	0
ValidKnown_A	1523284844	1520093096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	1520093096	0	0
T1	26512	25828	0	0
T2	277432	277108	0	0
T3	12312	9336	0	0
T4	1644240	1570188	0	0
T5	4496	4128	0	0
T6	243176	242916	0	0
T7	554124	553924	0	0
T16	1697908	1697588	0	0
T17	3892	3644	0	0
T18	20944	20712	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	400611281	0	0
T1	26512	8368	0	0
T2	277432	134454	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	42730	0	0
T7	554124	269442	0	0
T16	1697908	567182	0	0
T17	3892	64	0	0
T18	20944	5978	0	0
T23	0	12	0	0
T26	0	14828	0	0
T36	0	40698	0	0
T46	0	47798	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	400611281	0	0
T1	26512	8368	0	0
T2	277432	134454	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	42730	0	0
T7	554124	269442	0	0
T16	1697908	567182	0	0
T17	3892	64	0	0
T18	20944	5978	0	0
T23	0	12	0	0
T26	0	14828	0	0
T36	0	40698	0	0
T46	0	47798	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	1520093096	0	0
T1	26512	25828	0	0
T2	277432	277108	0	0
T3	12312	9336	0	0
T4	1644240	1570188	0	0
T5	4496	4128	0	0
T6	243176	242916	0	0
T7	554124	553924	0	0
T16	1697908	1697588	0	0
T17	3892	3644	0	0
T18	20944	20712	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	1520093096	0	0
T1	26512	25828	0	0
T2	277432	277108	0	0
T3	12312	9336	0	0
T4	1644240	1570188	0	0
T5	4496	4128	0	0
T6	243176	242916	0	0
T7	554124	553924	0	0
T16	1697908	1697588	0	0
T17	3892	3644	0	0
T18	20944	20712	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	400611281	0	0
T1	26512	8368	0	0
T2	277432	134454	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	42730	0	0
T7	554124	269442	0	0
T16	1697908	567182	0	0
T17	3892	64	0	0
T18	20944	5978	0	0
T23	0	12	0	0
T26	0	14828	0	0
T36	0	40698	0	0
T46	0	47798	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	178433321	0	0
T1	26512	1358	0	0
T2	277432	766	0	0
T3	12312	512	0	0
T4	1644240	94000	0	0
T5	4496	286	0	0
T6	243176	75944	0	0
T7	554124	1606	0	0
T16	1697908	213826	0	0
T17	3892	256	0	0
T18	20944	746	0	0
T23	0	48	0	0
T26	0	48542	0	0
T36	0	61370	0	0
T46	0	62920	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	423997708	0	0
T1	26512	8368	0	0
T2	277432	134618	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	51302	0	0
T7	554124	269728	0	0
T16	1697908	686278	0	0
T17	3892	64	0	0
T18	20944	5992	0	0
T23	0	12	0	0
T26	0	16342	0	0
T36	0	44922	0	0
T46	0	59788	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	400611281	0	0
T1	26512	8368	0	0
T2	277432	134454	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	42730	0	0
T7	554124	269442	0	0
T16	1697908	567182	0	0
T17	3892	64	0	0
T18	20944	5978	0	0
T23	0	12	0	0
T26	0	14828	0	0
T36	0	40698	0	0
T46	0	47798	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	400611281	0	0
T1	26512	8368	0	0
T2	277432	134454	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	42730	0	0
T7	554124	269442	0	0
T16	1697908	567182	0	0
T17	3892	64	0	0
T18	20944	5978	0	0
T23	0	12	0	0
T26	0	14828	0	0
T36	0	40698	0	0
T46	0	47798	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	423997708	0	0
T1	26512	8368	0	0
T2	277432	134618	0	0
T3	12312	152	0	0
T4	1644240	351232	0	0
T5	4496	84	0	0
T6	243176	51302	0	0
T7	554124	269728	0	0
T16	1697908	686278	0	0
T17	3892	64	0	0
T18	20944	5992	0	0
T23	0	12	0	0
T26	0	16342	0	0
T36	0	44922	0	0
T46	0	59788	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1523284844	1520093096	0	0
T1	26512	25828	0	0
T2	277432	277108	0	0
T3	12312	9336	0	0
T4	1644240	1570188	0	0
T5	4496	4128	0	0
T6	243176	242916	0	0
T7	554124	553924	0	0
T16	1697908	1697588	0	0
T17	3892	3644	0	0
T18	20944	20712	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380821211	380023274	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380821211	107407266	0	0
GntImpliesValid_A	380821211	107407266	0	0
GrantKnown_A	380821211	380023274	0	0
IdxKnown_A	380821211	380023274	0	0
IndexIsCorrect_A	380821211	107407266	0	0
NoReadyValidNoGrant_A	380821211	46424231	0	0
Priority_A	380821211	113127431	0	0
ReadyAndValidImplyGrant_A	380821211	107407266	0	0
ReqAndReadyImplyGrant_A	380821211	107407266	0	0
ReqImpliesValid_A	380821211	113127431	0	0
ValidKnown_A	380821211	380023274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407266	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407266	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407266	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	46424231	0	0
T1	6628	617	0	0
T2	69358	286	0	0
T3	3078	256	0	0
T4	411060	47000	0	0
T5	1124	143	0	0
T6	60794	18638	0	0
T7	138531	505	0	0
T16	424477	61940	0	0
T17	973	128	0	0
T18	5236	291	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	113127431	0	0
T1	6628	3371	0	0
T2	69358	66603	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	13172	0	0
T7	138531	1937	0	0
T16	424477	183749	0	0
T17	973	32	0	0
T18	5236	1968	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407266	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407266	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	113127431	0	0
T1	6628	3371	0	0
T2	69358	66603	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	13172	0	0
T7	138531	1937	0	0
T16	424477	183749	0	0
T17	973	32	0	0
T18	5236	1968	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380821211	380023274	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380821211	107407214	0	0
GntImpliesValid_A	380821211	107407214	0	0
GrantKnown_A	380821211	380023274	0	0
IdxKnown_A	380821211	380023274	0	0
IndexIsCorrect_A	380821211	107407214	0	0
NoReadyValidNoGrant_A	380821211	46424266	0	0
Priority_A	380821211	113127344	0	0
ReadyAndValidImplyGrant_A	380821211	107407214	0	0
ReqAndReadyImplyGrant_A	380821211	107407214	0	0
ReqImpliesValid_A	380821211	113127344	0	0
ValidKnown_A	380821211	380023274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407214	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407214	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407214	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	46424266	0	0
T1	6628	617	0	0
T2	69358	286	0	0
T3	3078	256	0	0
T4	411060	47000	0	0
T5	1124	143	0	0
T6	60794	18638	0	0
T7	138531	505	0	0
T16	424477	61940	0	0
T17	973	128	0	0
T18	5236	291	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	113127344	0	0
T1	6628	3371	0	0
T2	69358	66603	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	13172	0	0
T7	138531	1937	0	0
T16	424477	183749	0	0
T17	973	32	0	0
T18	5236	1968	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407214	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	107407214	0	0
T1	6628	3371	0	0
T2	69358	66556	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	10892	0	0
T7	138531	1884	0	0
T16	424477	150044	0	0
T17	973	32	0	0
T18	5236	1964	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	113127344	0	0
T1	6628	3371	0	0
T2	69358	66603	0	0
T3	3078	76	0	0
T4	411060	175616	0	0
T5	1124	42	0	0
T6	60794	13172	0	0
T7	138531	1937	0	0
T16	424477	183749	0	0
T17	973	32	0	0
T18	5236	1968	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380821211	380023274	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380821211	92898438	0	0
GntImpliesValid_A	380821211	92898438	0	0
GrantKnown_A	380821211	380023274	0	0
IdxKnown_A	380821211	380023274	0	0
IndexIsCorrect_A	380821211	92898438	0	0
NoReadyValidNoGrant_A	380821211	42792412	0	0
Priority_A	380821211	98871504	0	0
ReadyAndValidImplyGrant_A	380821211	92898438	0	0
ReqAndReadyImplyGrant_A	380821211	92898438	0	0
ReqImpliesValid_A	380821211	98871504	0	0
ValidKnown_A	380821211	380023274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898438	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898438	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898438	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	42792412	0	0
T1	6628	62	0	0
T2	69358	97	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	19334	0	0
T7	138531	298	0	0
T16	424477	44973	0	0
T17	973	0	0	0
T18	5236	82	0	0
T23	0	24	0	0
T26	0	24271	0	0
T36	0	30685	0	0
T46	0	31460	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	98871504	0	0
T1	6628	813	0	0
T2	69358	706	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	12479	0	0
T7	138531	132927	0	0
T16	424477	159390	0	0
T17	973	0	0	0
T18	5236	1028	0	0
T23	0	6	0	0
T26	0	8171	0	0
T36	0	22461	0	0
T46	0	29894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898438	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898438	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	98871504	0	0
T1	6628	813	0	0
T2	69358	706	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	12479	0	0
T7	138531	132927	0	0
T16	424477	159390	0	0
T17	973	0	0	0
T18	5236	1028	0	0
T23	0	6	0	0
T26	0	8171	0	0
T36	0	22461	0	0
T46	0	29894	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380821211	380023274	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	380821211	92898363	0	0
GntImpliesValid_A	380821211	92898363	0	0
GrantKnown_A	380821211	380023274	0	0
IdxKnown_A	380821211	380023274	0	0
IndexIsCorrect_A	380821211	92898363	0	0
NoReadyValidNoGrant_A	380821211	42792412	0	0
Priority_A	380821211	98871429	0	0
ReadyAndValidImplyGrant_A	380821211	92898363	0	0
ReqAndReadyImplyGrant_A	380821211	92898363	0	0
ReqImpliesValid_A	380821211	98871429	0	0
ValidKnown_A	380821211	380023274	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898363	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898363	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898363	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	42792412	0	0
T1	6628	62	0	0
T2	69358	97	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	19334	0	0
T7	138531	298	0	0
T16	424477	44973	0	0
T17	973	0	0	0
T18	5236	82	0	0
T23	0	24	0	0
T26	0	24271	0	0
T36	0	30685	0	0
T46	0	31460	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	98871429	0	0
T1	6628	813	0	0
T2	69358	706	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	12479	0	0
T7	138531	132927	0	0
T16	424477	159390	0	0
T17	973	0	0	0
T18	5236	1028	0	0
T23	0	6	0	0
T26	0	8171	0	0
T36	0	22461	0	0
T46	0	29894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898363	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	92898363	0	0
T1	6628	813	0	0
T2	69358	671	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	10473	0	0
T7	138531	132837	0	0
T16	424477	133547	0	0
T17	973	0	0	0
T18	5236	1025	0	0
T23	0	6	0	0
T26	0	7414	0	0
T36	0	20349	0	0
T46	0	23899	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	98871429	0	0
T1	6628	813	0	0
T2	69358	706	0	0
T3	3078	0	0	0
T4	411060	0	0	0
T5	1124	0	0	0
T6	60794	12479	0	0
T7	138531	132927	0	0
T16	424477	159390	0	0
T17	973	0	0	0
T18	5236	1028	0	0
T23	0	6	0	0
T26	0	8171	0	0
T36	0	22461	0	0
T46	0	29894	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380821211	380023274	0	0
T1	6628	6457	0	0
T2	69358	69277	0	0
T3	3078	2334	0	0
T4	411060	392547	0	0
T5	1124	1032	0	0
T6	60794	60729	0	0
T7	138531	138481	0	0
T16	424477	424397	0	0
T17	973	911	0	0
T18	5236	5178	0	0