Module Definition
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Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 100.00 98.56 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 100.00 98.56 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_region_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_sw_sel

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_region_sel

Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_hw_sel

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Module : flash_mp_data_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T62,T271
11CoveredT23,T36,T39

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T25
11CoveredT1,T23,T36

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T20,T124
11CoveredT1,T6,T23

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T36,T20
11CoveredT6,T26,T36

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T21,T124
11CoveredT1,T16,T38

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T12,T38
11CoveredT6,T26,T36

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T36,T20
11CoveredT16,T26,T23

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T16
11CoveredT1,T2,T4

Branch Coverage for Module : flash_mp_data_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T62,T271
11CoveredT39,T20,T38

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T25
11CoveredT36,T39,T41

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T20,T124
11CoveredT1,T23,T39

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T20,T124
11CoveredT46,T39,T69

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T21,T124
11CoveredT1,T16,T31

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T12,T38
11CoveredT36,T39,T69

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T20,T124
11CoveredT16,T69,T37

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T16,T23
11CoveredT1,T2,T4

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T3,T104,T112
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT271,T272,T273
11CoveredT23,T36,T39

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T20,T246
11CoveredT1,T23,T39

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T271,T274
11CoveredT6,T39,T38

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T20,T35
11CoveredT6,T26,T36

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T275,T276
11CoveredT1,T16,T38

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT20,T41,T8
11CoveredT6,T26,T36

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT23,T20,T149
11CoveredT26,T23,T38

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T6,T16
11CoveredT1,T2,T6

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%