SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 8368 | 8368 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 158951719 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8368 | 8368 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T5 | 8 | 8 | 0 | 0 |
T6 | 8 | 8 | 0 | 0 |
T7 | 8 | 8 | 0 | 0 |
T16 | 8 | 8 | 0 | 0 |
T17 | 8 | 8 | 0 | 0 |
T18 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 158951719 | 0 | 0 |
T1 | 6628 | 1792 | 0 | 0 |
T2 | 69358 | 0 | 0 | 0 |
T3 | 3078 | 6 | 0 | 0 |
T4 | 411060 | 165528 | 0 | 0 |
T5 | 2248 | 0 | 0 | 0 |
T6 | 60794 | 0 | 0 | 0 |
T7 | 138531 | 256 | 0 | 0 |
T16 | 848954 | 13850 | 0 | 0 |
T17 | 1946 | 0 | 0 | 0 |
T18 | 10472 | 0 | 0 | 0 |
T26 | 63742 | 0 | 0 | 0 |
T39 | 0 | 6900 | 0 | 0 |
T46 | 0 | 7250 | 0 | 0 |
T68 | 0 | 606 | 0 | 0 |
T69 | 0 | 8800 | 0 | 0 |
T74 | 0 | 256 | 0 | 0 |
T104 | 0 | 18 | 0 | 0 |
T115 | 400459 | 0 | 0 | 0 |
T127 | 162726 | 655360 | 0 | 0 |
T128 | 0 | 655360 | 0 | 0 |
T129 | 0 | 506 | 0 | 0 |
T130 | 0 | 256 | 0 | 0 |
T131 | 0 | 589824 | 0 | 0 |
T132 | 0 | 12800 | 0 | 0 |
T133 | 0 | 524288 | 0 | 0 |
T134 | 0 | 256 | 0 | 0 |
T135 | 0 | 12800 | 0 | 0 |
T136 | 0 | 12800 | 0 | 0 |
T137 | 4443 | 0 | 0 | 0 |
T138 | 1483 | 0 | 0 | 0 |
T139 | 1287 | 0 | 0 | 0 |
T140 | 3739 | 0 | 0 | 0 |
T141 | 2831 | 0 | 0 | 0 |
T142 | 2698 | 0 | 0 | 0 |
T143 | 250794 | 0 | 0 | 0 |
T144 | 153078 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T6 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 61544174 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 61544174 | 0 | 0 |
T1 | 6628 | 1280 | 0 | 0 |
T2 | 69358 | 66436 | 0 | 0 |
T3 | 3078 | 0 | 0 | 0 |
T4 | 411060 | 0 | 0 | 0 |
T5 | 1124 | 0 | 0 | 0 |
T6 | 60794 | 0 | 0 | 0 |
T7 | 138531 | 1580 | 0 | 0 |
T16 | 424477 | 131950 | 0 | 0 |
T17 | 973 | 0 | 0 | 0 |
T18 | 5236 | 1600 | 0 | 0 |
T19 | 0 | 65836 | 0 | 0 |
T23 | 0 | 50 | 0 | 0 |
T39 | 0 | 5850 | 0 | 0 |
T46 | 0 | 34500 | 0 | 0 |
T68 | 0 | 28356 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 12239239 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 12239239 | 0 | 0 |
T1 | 6628 | 1792 | 0 | 0 |
T2 | 69358 | 0 | 0 | 0 |
T3 | 3078 | 6 | 0 | 0 |
T4 | 411060 | 165528 | 0 | 0 |
T5 | 1124 | 0 | 0 | 0 |
T6 | 60794 | 0 | 0 | 0 |
T7 | 138531 | 256 | 0 | 0 |
T16 | 424477 | 12550 | 0 | 0 |
T17 | 973 | 0 | 0 | 0 |
T18 | 5236 | 0 | 0 | 0 |
T39 | 0 | 6750 | 0 | 0 |
T46 | 0 | 7250 | 0 | 0 |
T68 | 0 | 606 | 0 | 0 |
T69 | 0 | 6850 | 0 | 0 |
T104 | 0 | 18 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T8,T9,T127 |
1 | 0 | Covered | T46,T69,T40 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 2464250 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 2464250 | 0 | 0 |
T115 | 400459 | 0 | 0 | 0 |
T127 | 162726 | 655360 | 0 | 0 |
T128 | 0 | 655360 | 0 | 0 |
T129 | 0 | 506 | 0 | 0 |
T130 | 0 | 256 | 0 | 0 |
T131 | 0 | 589824 | 0 | 0 |
T132 | 0 | 12800 | 0 | 0 |
T133 | 0 | 524288 | 0 | 0 |
T134 | 0 | 256 | 0 | 0 |
T135 | 0 | 12800 | 0 | 0 |
T136 | 0 | 12800 | 0 | 0 |
T137 | 4443 | 0 | 0 | 0 |
T138 | 1483 | 0 | 0 | 0 |
T139 | 1287 | 0 | 0 | 0 |
T140 | 3739 | 0 | 0 | 0 |
T141 | 2831 | 0 | 0 | 0 |
T142 | 2698 | 0 | 0 | 0 |
T143 | 250794 | 0 | 0 | 0 |
T144 | 153078 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T16,T39,T69 |
1 | 0 | Covered | T1,T6,T16 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 2599921 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 2599921 | 0 | 0 |
T5 | 1124 | 0 | 0 | 0 |
T11 | 1187 | 0 | 0 | 0 |
T16 | 424477 | 1300 | 0 | 0 |
T17 | 973 | 0 | 0 | 0 |
T18 | 5236 | 0 | 0 | 0 |
T23 | 2421 | 0 | 0 | 0 |
T26 | 63742 | 0 | 0 | 0 |
T28 | 0 | 13500 | 0 | 0 |
T36 | 141914 | 0 | 0 | 0 |
T39 | 0 | 150 | 0 | 0 |
T46 | 120763 | 0 | 0 | 0 |
T47 | 0 | 200 | 0 | 0 |
T68 | 96870 | 0 | 0 | 0 |
T69 | 0 | 1950 | 0 | 0 |
T74 | 0 | 256 | 0 | 0 |
T76 | 0 | 100 | 0 | 0 |
T123 | 0 | 900 | 0 | 0 |
T124 | 0 | 349 | 0 | 0 |
T145 | 0 | 256 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T2,T7 |
1 | 0 | Covered | T1,T2,T6 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 60849619 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 60849619 | 0 | 0 |
T1 | 6628 | 512 | 0 | 0 |
T2 | 69358 | 606 | 0 | 0 |
T3 | 3078 | 0 | 0 | 0 |
T4 | 411060 | 0 | 0 | 0 |
T5 | 1124 | 0 | 0 | 0 |
T6 | 60794 | 0 | 0 | 0 |
T7 | 138531 | 132790 | 0 | 0 |
T16 | 424477 | 110900 | 0 | 0 |
T17 | 973 | 0 | 0 | 0 |
T18 | 5236 | 850 | 0 | 0 |
T19 | 0 | 256 | 0 | 0 |
T39 | 0 | 5300 | 0 | 0 |
T46 | 0 | 19400 | 0 | 0 |
T68 | 0 | 26438 | 0 | 0 |
T69 | 0 | 88550 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T31,T49 |
1 | 0 | Covered | T1,T31,T21 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 7110488 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 7110488 | 0 | 0 |
T1 | 6628 | 256 | 0 | 0 |
T2 | 69358 | 0 | 0 | 0 |
T3 | 3078 | 0 | 0 | 0 |
T4 | 411060 | 0 | 0 | 0 |
T5 | 1124 | 0 | 0 | 0 |
T6 | 60794 | 0 | 0 | 0 |
T7 | 138531 | 0 | 0 | 0 |
T16 | 424477 | 0 | 0 | 0 |
T17 | 973 | 0 | 0 | 0 |
T18 | 5236 | 0 | 0 | 0 |
T31 | 0 | 89900 | 0 | 0 |
T49 | 0 | 506 | 0 | 0 |
T145 | 0 | 786688 | 0 | 0 |
T146 | 0 | 300544 | 0 | 0 |
T147 | 0 | 353280 | 0 | 0 |
T148 | 0 | 100 | 0 | 0 |
T149 | 0 | 256 | 0 | 0 |
T150 | 0 | 128000 | 0 | 0 |
T151 | 0 | 495616 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T146,T147,T145 |
1 | 0 | Covered | T49,T8,T9 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 6056074 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 6056074 | 0 | 0 |
T27 | 2866 | 0 | 0 | 0 |
T88 | 241185 | 0 | 0 | 0 |
T127 | 0 | 589824 | 0 | 0 |
T128 | 0 | 524288 | 0 | 0 |
T131 | 0 | 393216 | 0 | 0 |
T145 | 0 | 786432 | 0 | 0 |
T146 | 819002 | 262144 | 0 | 0 |
T147 | 509320 | 327680 | 0 | 0 |
T150 | 0 | 12800 | 0 | 0 |
T151 | 0 | 393216 | 0 | 0 |
T152 | 0 | 131072 | 0 | 0 |
T153 | 0 | 556 | 0 | 0 |
T154 | 1540 | 0 | 0 | 0 |
T155 | 1568 | 0 | 0 | 0 |
T156 | 2213 | 0 | 0 | 0 |
T157 | 137001 | 0 | 0 | 0 |
T158 | 1494 | 0 | 0 | 0 |
T159 | 60834 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T24,T49,T146 |
1 | 0 | Covered | T24,T49,T8 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1046 | 1046 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 380821211 | 6087954 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1046 | 1046 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 380821211 | 6087954 | 0 | 0 |
T24 | 2656 | 50 | 0 | 0 |
T49 | 11474 | 150 | 0 | 0 |
T53 | 204136 | 0 | 0 | 0 |
T76 | 693 | 0 | 0 | 0 |
T97 | 2510 | 0 | 0 | 0 |
T102 | 884 | 0 | 0 | 0 |
T127 | 0 | 589824 | 0 | 0 |
T128 | 0 | 524288 | 0 | 0 |
T145 | 0 | 786432 | 0 | 0 |
T146 | 0 | 262144 | 0 | 0 |
T147 | 0 | 327680 | 0 | 0 |
T150 | 0 | 25600 | 0 | 0 |
T151 | 0 | 393216 | 0 | 0 |
T152 | 0 | 131072 | 0 | 0 |
T160 | 3641 | 0 | 0 | 0 |
T161 | 1294 | 0 | 0 | 0 |
T162 | 162347 | 0 | 0 | 0 |
T163 | 3186 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |