Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24561545	1		T1	78899		T2	1278		T3	149
full_word	7771875	1		T1	29209		T2	1558		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32333100	1		T1	108108		T2	2836		T3	151
auto[TlIntgErrCmd]	112	1		T66	7		T93	9		T241	6
auto[TlIntgErrData]	105	1		T66	4		T93	6		T241	6
auto[TlIntgErrBoth]	103	1		T66	9		T93	5		T241	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27763974	1		T1	85273		T2	2481		T3	143
auto[1]	4569446	1		T1	22835		T2	355		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23829678	1		T1	77522		T2	1173		T3	143
auto[TlIntgErrNone]	partial	auto[1]	731572	1		T1	1377		T2	105		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	3934155	1		T1	7751		T2	1308		T4	3266
auto[TlIntgErrNone]	full_word	auto[1]	3837695	1		T1	21458		T2	250		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T66	5		T93	5		T241	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T66	2		T93	3		T241	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T253	1		T330	1		T327	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T93	1		T241	1		T322	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T66	1		T93	3		T241	2
auto[TlIntgErrData]	partial	auto[1]	51	1		T66	2		T93	3		T241	4
auto[TlIntgErrData]	full_word	auto[0]	6	1		T331	2		T250	1		T327	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T66	1		T331	1		T332	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T66	3		T93	2		T241	6
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T66	6		T93	2		T241	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T333	1		T334	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T93	1		T322	1		T332	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20529	1		T91	1431		T92	982		T66	17
full_word	4054260	1		T2	16637		T20	8		T5	104

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4074491	1		T2	16637		T20	8		T5	104
auto[TlIntgErrCmd]	95	1		T66	6		T93	4		T241	6
auto[TlIntgErrData]	107	1		T66	3		T93	7		T241	7
auto[TlIntgErrBoth]	96	1		T66	10		T93	6		T241	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4048650	1		T2	16637		T20	8		T5	104
auto[1]	26139	1		T91	1642		T92	1374		T66	12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1114	1		T91	78		T92	64		T188	28
auto[TlIntgErrNone]	partial	auto[1]	19146	1		T91	1353		T92	918		T188	425
auto[TlIntgErrNone]	full_word	auto[0]	4047419	1		T2	16637		T20	8		T5	104
auto[TlIntgErrNone]	full_word	auto[1]	6812	1		T91	289		T92	456		T188	127
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T66	2		T93	1		T241	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T66	4		T93	3		T241	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T241	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T322	1		T330	1		T326	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T66	1		T93	1		T241	3
auto[TlIntgErrData]	partial	auto[1]	55	1		T66	2		T93	4		T241	4
auto[TlIntgErrData]	full_word	auto[0]	7	1		T93	1		T325	2		T330	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T93	1		T322	1		T332	2
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T66	4		T93	3		T241	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T66	4		T93	3		T253	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T241	1		T322	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	11	1		T66	2		T241	1		T322	1